diff options
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-1.d | 42 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-1.s | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-1.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-1.l | 33 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-2.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-2.l | 33 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-3.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-3.l | 33 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-4.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad-4.l | 65 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/d128_the-bad.s | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/the-1.d | 522 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/the-1.s | 10 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/the-bad-1.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/aarch64/the-bad-1.l | 513 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-dis-2.c | 982 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 118 |
18 files changed, 2251 insertions, 139 deletions
diff --git a/gas/testsuite/gas/aarch64/d128_the-1.d b/gas/testsuite/gas/aarch64/d128_the-1.d new file mode 100644 index 0000000..1215f23 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-1.d @@ -0,0 +1,42 @@ +#name: Test of FEAT_THE quadword Instructions. +#as: -march=armv9.4-a+the+d128 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: 19200e04 rcwcasp x0, x1, x4, x5, \[x16\] +.*: 19a00e04 rcwcaspa x0, x1, x4, x5, \[x16\] +.*: 19e00e04 rcwcaspal x0, x1, x4, x5, \[x16\] +.*: 19600e04 rcwcaspl x0, x1, x4, x5, \[x16\] +.*: 59200e04 rcwscasp x0, x1, x4, x5, \[x16\] +.*: 59a00e04 rcwscaspa x0, x1, x4, x5, \[x16\] +.*: 59e00e04 rcwscaspal x0, x1, x4, x5, \[x16\] +.*: 59600e04 rcwscaspl x0, x1, x4, x5, \[x16\] +.*: 19259200 rcwclrp x0, x5, \[x16\] +.*: 19a59200 rcwclrpa x0, x5, \[x16\] +.*: 19e59200 rcwclrpal x0, x5, \[x16\] +.*: 19659200 rcwclrpl x0, x5, \[x16\] +.*: 59259200 rcwsclrp x0, x5, \[x16\] +.*: 59a59200 rcwsclrpa x0, x5, \[x16\] +.*: 59e59200 rcwsclrpal x0, x5, \[x16\] +.*: 59659200 rcwsclrpl x0, x5, \[x16\] +.*: 1925a200 rcwswpp x0, x5, \[x16\] +.*: 19a5a200 rcwswppa x0, x5, \[x16\] +.*: 19e5a200 rcwswppal x0, x5, \[x16\] +.*: 1965a200 rcwswppl x0, x5, \[x16\] +.*: 5925a200 rcwsswpp x0, x5, \[x16\] +.*: 59a5a200 rcwsswppa x0, x5, \[x16\] +.*: 59e5a200 rcwsswppal x0, x5, \[x16\] +.*: 5965a200 rcwsswppl x0, x5, \[x16\] +.*: 1925b200 rcwsetp x0, x5, \[x16\] +.*: 19a5b200 rcwsetpa x0, x5, \[x16\] +.*: 19e5b200 rcwsetpal x0, x5, \[x16\] +.*: 1965b200 rcwsetpl x0, x5, \[x16\] +.*: 5925b200 rcwssetp x0, x5, \[x16\] +.*: 59a5b200 rcwssetpa x0, x5, \[x16\] +.*: 59e5b200 rcwssetpal x0, x5, \[x16\] +.*: 5965b200 rcwssetpl x0, x5, \[x16\] diff --git a/gas/testsuite/gas/aarch64/d128_the-1.s b/gas/testsuite/gas/aarch64/d128_the-1.s new file mode 100644 index 0000000..2835b00 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-1.s @@ -0,0 +1,7 @@ + .text + .irp op casp, caspa, caspal, caspl, scasp, scaspa, scaspal, scaspl + rcw\op x0, x1, x4, x5, [x16] + .endr + .irp op clrp, clrpa, clrpal, clrpl, sclrp, sclrpa, sclrpal, sclrpl, swpp, swppa, swppal, swppl, sswpp, sswppa, sswppal, sswppl, setp, setpa, setpal, setpl, ssetp, ssetpa, ssetpal, ssetpl + rcw\op x0, x5, [x16] + .endr diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-1.d b/gas/testsuite/gas/aarch64/d128_the-bad-1.d new file mode 100644 index 0000000..7906fad --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-1.d @@ -0,0 +1,4 @@ +#name: Test of illegal FEAT_THE quadword Instructions. +#as: -march=armv9.4-a+the +#source: d128_the-1.s +#error_output: d128_the-bad-1.l diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-1.l b/gas/testsuite/gas/aarch64/d128_the-bad-1.l new file mode 100644 index 0000000..9de9791 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-1.l @@ -0,0 +1,33 @@ +[^ :]+: Assembler messages: +.*: Error: selected processor does not support `rcwcasp x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspa x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspal x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspl x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscasp x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspa x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspal x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspl x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswpp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswpp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpl x0,x5,\[x16\]' diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-2.d b/gas/testsuite/gas/aarch64/d128_the-bad-2.d new file mode 100644 index 0000000..4f4e902 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-2.d @@ -0,0 +1,4 @@ +#name: Test of illegal FEAT_D128 quadword Instructions. +#as: -march=armv9.4-a+d128 +#source: d128_the-1.s +#error_output: d128_the-bad-2.l diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-2.l b/gas/testsuite/gas/aarch64/d128_the-bad-2.l new file mode 100644 index 0000000..9de9791 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-2.l @@ -0,0 +1,33 @@ +[^ :]+: Assembler messages: +.*: Error: selected processor does not support `rcwcasp x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspa x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspal x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspl x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscasp x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspa x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspal x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspl x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswpp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswpp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpl x0,x5,\[x16\]' diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-3.d b/gas/testsuite/gas/aarch64/d128_the-bad-3.d new file mode 100644 index 0000000..bcd70ea --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-3.d @@ -0,0 +1,4 @@ +#name: Test of illegal quadword Instructions. +#as: -march=armv9.4-a +#source: d128_the-1.s +#error_output: d128_the-bad-3.l diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-3.l b/gas/testsuite/gas/aarch64/d128_the-bad-3.l new file mode 100644 index 0000000..9de9791 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-3.l @@ -0,0 +1,33 @@ +[^ :]+: Assembler messages: +.*: Error: selected processor does not support `rcwcasp x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspa x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspal x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwcaspl x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscasp x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspa x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspal x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwscaspl x0,x1,x4,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwclrpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsclrpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswpp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwswppl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswpp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsswppl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwsetpl x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetp x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpa x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpal x0,x5,\[x16\]' +.*: Error: selected processor does not support `rcwssetpl x0,x5,\[x16\]' diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-4.d b/gas/testsuite/gas/aarch64/d128_the-bad-4.d new file mode 100644 index 0000000..5be8a81 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-4.d @@ -0,0 +1,4 @@ +#name: Test of FEAT_THE Instructions wrong operands. +#as: -march=armv9.4-a+d128+the +#source: d128_the-bad.s +#error_output: d128_the-bad-4.l diff --git a/gas/testsuite/gas/aarch64/d128_the-bad-4.l b/gas/testsuite/gas/aarch64/d128_the-bad-4.l new file mode 100644 index 0000000..bbe6092 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad-4.l @@ -0,0 +1,65 @@ +[^ :]+: Assembler messages: +.*: Error: reg pair must start from even reg at operand 1 -- `rcwcasp x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwcasp x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwcaspa x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwcaspa x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwcaspal x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwcaspal x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwcaspl x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwcaspl x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwscasp x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwscasp x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwscaspa x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwscaspa x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwscaspal x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwscaspal x0,x1,x5,x6,\[x16\]' +.*: Error: reg pair must start from even reg at operand 1 -- `rcwscaspl x1,x2,x4,x5,\[x16\]' +.*: Error: reg pair must start from even reg at operand 3 -- `rcwscaspl x0,x1,x5,x6,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwclrp x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwclrpa x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwclrpal x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwclrpl x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsclrp x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsclrpa x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsclrpal x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsclrpl x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwswpp x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwswppa x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwswppal x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwswppl x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsswpp x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsswppa x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsswppal x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsswppl x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsetp x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsetpa x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsetpal x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwsetpl x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwssetp x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwssetpa x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwssetpal x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 2 -- `rcwssetpl x0,x31,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwclrp x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwclrpa x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwclrpal x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwclrpl x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsclrp x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsclrpa x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsclrpal x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsclrpl x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwswpp x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwswppa x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwswppal x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwswppl x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsswpp x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsswppa x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsswppal x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsswppl x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsetp x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsetpa x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsetpal x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwsetpl x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwssetp x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwssetpa x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwssetpal x31,x0,\[x16\]' +.*: Error: expected an integer or zero register at operand 1 -- `rcwssetpl x31,x0,\[x16\]' diff --git a/gas/testsuite/gas/aarch64/d128_the-bad.s b/gas/testsuite/gas/aarch64/d128_the-bad.s new file mode 100644 index 0000000..d88e189 --- /dev/null +++ b/gas/testsuite/gas/aarch64/d128_the-bad.s @@ -0,0 +1,11 @@ + .text + .irp op casp, caspa, caspal, caspl, scasp, scaspa, scaspal, scaspl + rcw\op x1, x2, x4, x5, [x16] + rcw\op x0, x1, x5, x6, [x16] + .endr + .irp op clrp, clrpa, clrpal, clrpl, sclrp, sclrpa, sclrpal, sclrpl, swpp, swppa, swppal, swppl, sswpp, sswppa, sswppal, sswppl, setp, setpa, setpal, setpl, ssetp, ssetpa, ssetpal, ssetpl + rcw\op x0, x31, [x16] + .endr + .irp op clrp, clrpa, clrpal, clrpl, sclrp, sclrpa, sclrpal, sclrpl, swpp, swppa, swppal, swppl, sswpp, sswppa, sswppal, sswppl, setp, setpa, setpal, setpl, ssetp, ssetpa, ssetpal, ssetpl + rcw\op x31, x0, [x16] + .endr diff --git a/gas/testsuite/gas/aarch64/the-1.d b/gas/testsuite/gas/aarch64/the-1.d new file mode 100644 index 0000000..4d2e0ae --- /dev/null +++ b/gas/testsuite/gas/aarch64/the-1.d @@ -0,0 +1,522 @@ +#name: Test of FEAT_THE Instructions. +#as: -march=armv9.4-a+the +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: 19200822 rcwcas x0, x2, \[x1\] +.*: 19200832 rcwcas x0, x18, \[x1\] +.*: 19200902 rcwcas x0, x2, \[x8\] +.*: 19200912 rcwcas x0, x18, \[x8\] +.*: 19200a22 rcwcas x0, x2, \[x17\] +.*: 19200a32 rcwcas x0, x18, \[x17\] +.*: 19200b22 rcwcas x0, x2, \[x25\] +.*: 19200b32 rcwcas x0, x18, \[x25\] +.*: 19300822 rcwcas x16, x2, \[x1\] +.*: 19300832 rcwcas x16, x18, \[x1\] +.*: 19300902 rcwcas x16, x2, \[x8\] +.*: 19300912 rcwcas x16, x18, \[x8\] +.*: 19300a22 rcwcas x16, x2, \[x17\] +.*: 19300a32 rcwcas x16, x18, \[x17\] +.*: 19300b22 rcwcas x16, x2, \[x25\] +.*: 19300b32 rcwcas x16, x18, \[x25\] +.*: 19a00822 rcwcasa x0, x2, \[x1\] +.*: 19a00832 rcwcasa x0, x18, \[x1\] +.*: 19a00902 rcwcasa x0, x2, \[x8\] +.*: 19a00912 rcwcasa x0, x18, \[x8\] +.*: 19a00a22 rcwcasa x0, x2, \[x17\] +.*: 19a00a32 rcwcasa x0, x18, \[x17\] +.*: 19a00b22 rcwcasa x0, x2, \[x25\] +.*: 19a00b32 rcwcasa x0, x18, \[x25\] +.*: 19b00822 rcwcasa x16, x2, \[x1\] +.*: 19b00832 rcwcasa x16, x18, \[x1\] +.*: 19b00902 rcwcasa x16, x2, \[x8\] +.*: 19b00912 rcwcasa x16, x18, \[x8\] +.*: 19b00a22 rcwcasa x16, x2, \[x17\] +.*: 19b00a32 rcwcasa x16, x18, \[x17\] +.*: 19b00b22 rcwcasa x16, x2, \[x25\] +.*: 19b00b32 rcwcasa x16, x18, \[x25\] +.*: 19e00822 rcwcasal x0, x2, \[x1\] +.*: 19e00832 rcwcasal x0, x18, \[x1\] +.*: 19e00902 rcwcasal x0, x2, \[x8\] +.*: 19e00912 rcwcasal x0, x18, \[x8\] +.*: 19e00a22 rcwcasal x0, x2, \[x17\] +.*: 19e00a32 rcwcasal x0, x18, \[x17\] +.*: 19e00b22 rcwcasal x0, x2, \[x25\] +.*: 19e00b32 rcwcasal x0, x18, \[x25\] +.*: 19f00822 rcwcasal x16, x2, \[x1\] +.*: 19f00832 rcwcasal x16, x18, \[x1\] +.*: 19f00902 rcwcasal x16, x2, \[x8\] +.*: 19f00912 rcwcasal x16, x18, \[x8\] +.*: 19f00a22 rcwcasal x16, x2, \[x17\] +.*: 19f00a32 rcwcasal x16, x18, \[x17\] +.*: 19f00b22 rcwcasal x16, x2, \[x25\] +.*: 19f00b32 rcwcasal x16, x18, \[x25\] +.*: 19600822 rcwcasl x0, x2, \[x1\] +.*: 19600832 rcwcasl x0, x18, \[x1\] +.*: 19600902 rcwcasl x0, x2, \[x8\] +.*: 19600912 rcwcasl x0, x18, \[x8\] +.*: 19600a22 rcwcasl x0, x2, \[x17\] +.*: 19600a32 rcwcasl x0, x18, \[x17\] +.*: 19600b22 rcwcasl x0, x2, \[x25\] +.*: 19600b32 rcwcasl x0, x18, \[x25\] +.*: 19700822 rcwcasl x16, x2, \[x1\] +.*: 19700832 rcwcasl x16, x18, \[x1\] +.*: 19700902 rcwcasl x16, x2, \[x8\] +.*: 19700912 rcwcasl x16, x18, \[x8\] +.*: 19700a22 rcwcasl x16, x2, \[x17\] +.*: 19700a32 rcwcasl x16, x18, \[x17\] +.*: 19700b22 rcwcasl x16, x2, \[x25\] +.*: 19700b32 rcwcasl x16, x18, \[x25\] +.*: 59200822 rcwscas x0, x2, \[x1\] +.*: 59200832 rcwscas x0, x18, \[x1\] +.*: 59200902 rcwscas x0, x2, \[x8\] +.*: 59200912 rcwscas x0, x18, \[x8\] +.*: 59200a22 rcwscas x0, x2, \[x17\] +.*: 59200a32 rcwscas x0, x18, \[x17\] +.*: 59200b22 rcwscas x0, x2, \[x25\] +.*: 59200b32 rcwscas x0, x18, \[x25\] +.*: 59300822 rcwscas x16, x2, \[x1\] +.*: 59300832 rcwscas x16, x18, \[x1\] +.*: 59300902 rcwscas x16, x2, \[x8\] +.*: 59300912 rcwscas x16, x18, \[x8\] +.*: 59300a22 rcwscas x16, x2, \[x17\] +.*: 59300a32 rcwscas x16, x18, \[x17\] +.*: 59300b22 rcwscas x16, x2, \[x25\] +.*: 59300b32 rcwscas x16, x18, \[x25\] +.*: 59a00822 rcwscasa x0, x2, \[x1\] +.*: 59a00832 rcwscasa x0, x18, \[x1\] +.*: 59a00902 rcwscasa x0, x2, \[x8\] +.*: 59a00912 rcwscasa x0, x18, \[x8\] +.*: 59a00a22 rcwscasa x0, x2, \[x17\] +.*: 59a00a32 rcwscasa x0, x18, \[x17\] +.*: 59a00b22 rcwscasa x0, x2, \[x25\] +.*: 59a00b32 rcwscasa x0, x18, \[x25\] +.*: 59b00822 rcwscasa x16, x2, \[x1\] +.*: 59b00832 rcwscasa x16, x18, \[x1\] +.*: 59b00902 rcwscasa x16, x2, \[x8\] +.*: 59b00912 rcwscasa x16, x18, \[x8\] +.*: 59b00a22 rcwscasa x16, x2, \[x17\] +.*: 59b00a32 rcwscasa x16, x18, \[x17\] +.*: 59b00b22 rcwscasa x16, x2, \[x25\] +.*: 59b00b32 rcwscasa x16, x18, \[x25\] +.*: 59e00822 rcwscasal x0, x2, \[x1\] +.*: 59e00832 rcwscasal x0, x18, \[x1\] +.*: 59e00902 rcwscasal x0, x2, \[x8\] +.*: 59e00912 rcwscasal x0, x18, \[x8\] +.*: 59e00a22 rcwscasal x0, x2, \[x17\] +.*: 59e00a32 rcwscasal x0, x18, \[x17\] +.*: 59e00b22 rcwscasal x0, x2, \[x25\] +.*: 59e00b32 rcwscasal x0, x18, \[x25\] +.*: 59f00822 rcwscasal x16, x2, \[x1\] +.*: 59f00832 rcwscasal x16, x18, \[x1\] +.*: 59f00902 rcwscasal x16, x2, \[x8\] +.*: 59f00912 rcwscasal x16, x18, \[x8\] +.*: 59f00a22 rcwscasal x16, x2, \[x17\] +.*: 59f00a32 rcwscasal x16, x18, \[x17\] +.*: 59f00b22 rcwscasal x16, x2, \[x25\] +.*: 59f00b32 rcwscasal x16, x18, \[x25\] +.*: 59600822 rcwscasl x0, x2, \[x1\] +.*: 59600832 rcwscasl x0, x18, \[x1\] +.*: 59600902 rcwscasl x0, x2, \[x8\] +.*: 59600912 rcwscasl x0, x18, \[x8\] +.*: 59600a22 rcwscasl x0, x2, \[x17\] +.*: 59600a32 rcwscasl x0, x18, \[x17\] +.*: 59600b22 rcwscasl x0, x2, \[x25\] +.*: 59600b32 rcwscasl x0, x18, \[x25\] +.*: 59700822 rcwscasl x16, x2, \[x1\] +.*: 59700832 rcwscasl x16, x18, \[x1\] +.*: 59700902 rcwscasl x16, x2, \[x8\] +.*: 59700912 rcwscasl x16, x18, \[x8\] +.*: 59700a22 rcwscasl x16, x2, \[x17\] +.*: 59700a32 rcwscasl x16, x18, \[x17\] +.*: 59700b22 rcwscasl x16, x2, \[x25\] +.*: 59700b32 rcwscasl x16, x18, \[x25\] +.*: 38209022 rcwclr x0, x2, \[x1\] +.*: 38209032 rcwclr x0, x18, \[x1\] +.*: 38209102 rcwclr x0, x2, \[x8\] +.*: 38209112 rcwclr x0, x18, \[x8\] +.*: 38209222 rcwclr x0, x2, \[x17\] +.*: 38209232 rcwclr x0, x18, \[x17\] +.*: 38209322 rcwclr x0, x2, \[x25\] +.*: 38209332 rcwclr x0, x18, \[x25\] +.*: 38309022 rcwclr x16, x2, \[x1\] +.*: 38309032 rcwclr x16, x18, \[x1\] +.*: 38309102 rcwclr x16, x2, \[x8\] +.*: 38309112 rcwclr x16, x18, \[x8\] +.*: 38309222 rcwclr x16, x2, \[x17\] +.*: 38309232 rcwclr x16, x18, \[x17\] +.*: 38309322 rcwclr x16, x2, \[x25\] +.*: 38309332 rcwclr x16, x18, \[x25\] +.*: 38a09022 rcwclra x0, x2, \[x1\] +.*: 38a09032 rcwclra x0, x18, \[x1\] +.*: 38a09102 rcwclra x0, x2, \[x8\] +.*: 38a09112 rcwclra x0, x18, \[x8\] +.*: 38a09222 rcwclra x0, x2, \[x17\] +.*: 38a09232 rcwclra x0, x18, \[x17\] +.*: 38a09322 rcwclra x0, x2, \[x25\] +.*: 38a09332 rcwclra x0, x18, \[x25\] +.*: 38b09022 rcwclra x16, x2, \[x1\] +.*: 38b09032 rcwclra x16, x18, \[x1\] +.*: 38b09102 rcwclra x16, x2, \[x8\] +.*: 38b09112 rcwclra x16, x18, \[x8\] +.*: 38b09222 rcwclra x16, x2, \[x17\] +.*: 38b09232 rcwclra x16, x18, \[x17\] +.*: 38b09322 rcwclra x16, x2, \[x25\] +.*: 38b09332 rcwclra x16, x18, \[x25\] +.*: 38e09022 rcwclral x0, x2, \[x1\] +.*: 38e09032 rcwclral x0, x18, \[x1\] +.*: 38e09102 rcwclral x0, x2, \[x8\] +.*: 38e09112 rcwclral x0, x18, \[x8\] +.*: 38e09222 rcwclral x0, x2, \[x17\] +.*: 38e09232 rcwclral x0, x18, \[x17\] +.*: 38e09322 rcwclral x0, x2, \[x25\] +.*: 38e09332 rcwclral x0, x18, \[x25\] +.*: 38f09022 rcwclral x16, x2, \[x1\] +.*: 38f09032 rcwclral x16, x18, \[x1\] +.*: 38f09102 rcwclral x16, x2, \[x8\] +.*: 38f09112 rcwclral x16, x18, \[x8\] +.*: 38f09222 rcwclral x16, x2, \[x17\] +.*: 38f09232 rcwclral x16, x18, \[x17\] +.*: 38f09322 rcwclral x16, x2, \[x25\] +.*: 38f09332 rcwclral x16, x18, \[x25\] +.*: 38609022 rcwclrl x0, x2, \[x1\] +.*: 38609032 rcwclrl x0, x18, \[x1\] +.*: 38609102 rcwclrl x0, x2, \[x8\] +.*: 38609112 rcwclrl x0, x18, \[x8\] +.*: 38609222 rcwclrl x0, x2, \[x17\] +.*: 38609232 rcwclrl x0, x18, \[x17\] +.*: 38609322 rcwclrl x0, x2, \[x25\] +.*: 38609332 rcwclrl x0, x18, \[x25\] +.*: 38709022 rcwclrl x16, x2, \[x1\] +.*: 38709032 rcwclrl x16, x18, \[x1\] +.*: 38709102 rcwclrl x16, x2, \[x8\] +.*: 38709112 rcwclrl x16, x18, \[x8\] +.*: 38709222 rcwclrl x16, x2, \[x17\] +.*: 38709232 rcwclrl x16, x18, \[x17\] +.*: 38709322 rcwclrl x16, x2, \[x25\] +.*: 38709332 rcwclrl x16, x18, \[x25\] +.*: 78209022 rcwsclr x0, x2, \[x1\] +.*: 78209032 rcwsclr x0, x18, \[x1\] +.*: 78209102 rcwsclr x0, x2, \[x8\] +.*: 78209112 rcwsclr x0, x18, \[x8\] +.*: 78209222 rcwsclr x0, x2, \[x17\] +.*: 78209232 rcwsclr x0, x18, \[x17\] +.*: 78209322 rcwsclr x0, x2, \[x25\] +.*: 78209332 rcwsclr x0, x18, \[x25\] +.*: 78309022 rcwsclr x16, x2, \[x1\] +.*: 78309032 rcwsclr x16, x18, \[x1\] +.*: 78309102 rcwsclr x16, x2, \[x8\] +.*: 78309112 rcwsclr x16, x18, \[x8\] +.*: 78309222 rcwsclr x16, x2, \[x17\] +.*: 78309232 rcwsclr x16, x18, \[x17\] +.*: 78309322 rcwsclr x16, x2, \[x25\] +.*: 78309332 rcwsclr x16, x18, \[x25\] +.*: 78a09022 rcwsclra x0, x2, \[x1\] +.*: 78a09032 rcwsclra x0, x18, \[x1\] +.*: 78a09102 rcwsclra x0, x2, \[x8\] +.*: 78a09112 rcwsclra x0, x18, \[x8\] +.*: 78a09222 rcwsclra x0, x2, \[x17\] +.*: 78a09232 rcwsclra x0, x18, \[x17\] +.*: 78a09322 rcwsclra x0, x2, \[x25\] +.*: 78a09332 rcwsclra x0, x18, \[x25\] +.*: 78b09022 rcwsclra x16, x2, \[x1\] +.*: 78b09032 rcwsclra x16, x18, \[x1\] +.*: 78b09102 rcwsclra x16, x2, \[x8\] +.*: 78b09112 rcwsclra x16, x18, \[x8\] +.*: 78b09222 rcwsclra x16, x2, \[x17\] +.*: 78b09232 rcwsclra x16, x18, \[x17\] +.*: 78b09322 rcwsclra x16, x2, \[x25\] +.*: 78b09332 rcwsclra x16, x18, \[x25\] +.*: 78e09022 rcwsclral x0, x2, \[x1\] +.*: 78e09032 rcwsclral x0, x18, \[x1\] +.*: 78e09102 rcwsclral x0, x2, \[x8\] +.*: 78e09112 rcwsclral x0, x18, \[x8\] +.*: 78e09222 rcwsclral x0, x2, \[x17\] +.*: 78e09232 rcwsclral x0, x18, \[x17\] +.*: 78e09322 rcwsclral x0, x2, \[x25\] +.*: 78e09332 rcwsclral x0, x18, \[x25\] +.*: 78f09022 rcwsclral x16, x2, \[x1\] +.*: 78f09032 rcwsclral x16, x18, \[x1\] +.*: 78f09102 rcwsclral x16, x2, \[x8\] +.*: 78f09112 rcwsclral x16, x18, \[x8\] +.*: 78f09222 rcwsclral x16, x2, \[x17\] +.*: 78f09232 rcwsclral x16, x18, \[x17\] +.*: 78f09322 rcwsclral x16, x2, \[x25\] +.*: 78f09332 rcwsclral x16, x18, \[x25\] +.*: 78609022 rcwsclrl x0, x2, \[x1\] +.*: 78609032 rcwsclrl x0, x18, \[x1\] +.*: 78609102 rcwsclrl x0, x2, \[x8\] +.*: 78609112 rcwsclrl x0, x18, \[x8\] +.*: 78609222 rcwsclrl x0, x2, \[x17\] +.*: 78609232 rcwsclrl x0, x18, \[x17\] +.*: 78609322 rcwsclrl x0, x2, \[x25\] +.*: 78609332 rcwsclrl x0, x18, \[x25\] +.*: 78709022 rcwsclrl x16, x2, \[x1\] +.*: 78709032 rcwsclrl x16, x18, \[x1\] +.*: 78709102 rcwsclrl x16, x2, \[x8\] +.*: 78709112 rcwsclrl x16, x18, \[x8\] +.*: 78709222 rcwsclrl x16, x2, \[x17\] +.*: 78709232 rcwsclrl x16, x18, \[x17\] +.*: 78709322 rcwsclrl x16, x2, \[x25\] +.*: 78709332 rcwsclrl x16, x18, \[x25\] +.*: 3820a022 rcwswp x0, x2, \[x1\] +.*: 3820a032 rcwswp x0, x18, \[x1\] +.*: 3820a102 rcwswp x0, x2, \[x8\] +.*: 3820a112 rcwswp x0, x18, \[x8\] +.*: 3820a222 rcwswp x0, x2, \[x17\] +.*: 3820a232 rcwswp x0, x18, \[x17\] +.*: 3820a322 rcwswp x0, x2, \[x25\] +.*: 3820a332 rcwswp x0, x18, \[x25\] +.*: 3830a022 rcwswp x16, x2, \[x1\] +.*: 3830a032 rcwswp x16, x18, \[x1\] +.*: 3830a102 rcwswp x16, x2, \[x8\] +.*: 3830a112 rcwswp x16, x18, \[x8\] +.*: 3830a222 rcwswp x16, x2, \[x17\] +.*: 3830a232 rcwswp x16, x18, \[x17\] +.*: 3830a322 rcwswp x16, x2, \[x25\] +.*: 3830a332 rcwswp x16, x18, \[x25\] +.*: 38a0a022 rcwswpa x0, x2, \[x1\] +.*: 38a0a032 rcwswpa x0, x18, \[x1\] +.*: 38a0a102 rcwswpa x0, x2, \[x8\] +.*: 38a0a112 rcwswpa x0, x18, \[x8\] +.*: 38a0a222 rcwswpa x0, x2, \[x17\] +.*: 38a0a232 rcwswpa x0, x18, \[x17\] +.*: 38a0a322 rcwswpa x0, x2, \[x25\] +.*: 38a0a332 rcwswpa x0, x18, \[x25\] +.*: 38b0a022 rcwswpa x16, x2, \[x1\] +.*: 38b0a032 rcwswpa x16, x18, \[x1\] +.*: 38b0a102 rcwswpa x16, x2, \[x8\] +.*: 38b0a112 rcwswpa x16, x18, \[x8\] +.*: 38b0a222 rcwswpa x16, x2, \[x17\] +.*: 38b0a232 rcwswpa x16, x18, \[x17\] +.*: 38b0a322 rcwswpa x16, x2, \[x25\] +.*: 38b0a332 rcwswpa x16, x18, \[x25\] +.*: 38e0a022 rcwswpal x0, x2, \[x1\] +.*: 38e0a032 rcwswpal x0, x18, \[x1\] +.*: 38e0a102 rcwswpal x0, x2, \[x8\] +.*: 38e0a112 rcwswpal x0, x18, \[x8\] +.*: 38e0a222 rcwswpal x0, x2, \[x17\] +.*: 38e0a232 rcwswpal x0, x18, \[x17\] +.*: 38e0a322 rcwswpal x0, x2, \[x25\] +.*: 38e0a332 rcwswpal x0, x18, \[x25\] +.*: 38f0a022 rcwswpal x16, x2, \[x1\] +.*: 38f0a032 rcwswpal x16, x18, \[x1\] +.*: 38f0a102 rcwswpal x16, x2, \[x8\] +.*: 38f0a112 rcwswpal x16, x18, \[x8\] +.*: 38f0a222 rcwswpal x16, x2, \[x17\] +.*: 38f0a232 rcwswpal x16, x18, \[x17\] +.*: 38f0a322 rcwswpal x16, x2, \[x25\] +.*: 38f0a332 rcwswpal x16, x18, \[x25\] +.*: 3860a022 rcwswpl x0, x2, \[x1\] +.*: 3860a032 rcwswpl x0, x18, \[x1\] +.*: 3860a102 rcwswpl x0, x2, \[x8\] +.*: 3860a112 rcwswpl x0, x18, \[x8\] +.*: 3860a222 rcwswpl x0, x2, \[x17\] +.*: 3860a232 rcwswpl x0, x18, \[x17\] +.*: 3860a322 rcwswpl x0, x2, \[x25\] +.*: 3860a332 rcwswpl x0, x18, \[x25\] +.*: 3870a022 rcwswpl x16, x2, \[x1\] +.*: 3870a032 rcwswpl x16, x18, \[x1\] +.*: 3870a102 rcwswpl x16, x2, \[x8\] +.*: 3870a112 rcwswpl x16, x18, \[x8\] +.*: 3870a222 rcwswpl x16, x2, \[x17\] +.*: 3870a232 rcwswpl x16, x18, \[x17\] +.*: 3870a322 rcwswpl x16, x2, \[x25\] +.*: 3870a332 rcwswpl x16, x18, \[x25\] +.*: 7820a022 rcwsswp x0, x2, \[x1\] +.*: 7820a032 rcwsswp x0, x18, \[x1\] +.*: 7820a102 rcwsswp x0, x2, \[x8\] +.*: 7820a112 rcwsswp x0, x18, \[x8\] +.*: 7820a222 rcwsswp x0, x2, \[x17\] +.*: 7820a232 rcwsswp x0, x18, \[x17\] +.*: 7820a322 rcwsswp x0, x2, \[x25\] +.*: 7820a332 rcwsswp x0, x18, \[x25\] +.*: 7830a022 rcwsswp x16, x2, \[x1\] +.*: 7830a032 rcwsswp x16, x18, \[x1\] +.*: 7830a102 rcwsswp x16, x2, \[x8\] +.*: 7830a112 rcwsswp x16, x18, \[x8\] +.*: 7830a222 rcwsswp x16, x2, \[x17\] +.*: 7830a232 rcwsswp x16, x18, \[x17\] +.*: 7830a322 rcwsswp x16, x2, \[x25\] +.*: 7830a332 rcwsswp x16, x18, \[x25\] +.*: 78a0a022 rcwsswpa x0, x2, \[x1\] +.*: 78a0a032 rcwsswpa x0, x18, \[x1\] +.*: 78a0a102 rcwsswpa x0, x2, \[x8\] +.*: 78a0a112 rcwsswpa x0, x18, \[x8\] +.*: 78a0a222 rcwsswpa x0, x2, \[x17\] +.*: 78a0a232 rcwsswpa x0, x18, \[x17\] +.*: 78a0a322 rcwsswpa x0, x2, \[x25\] +.*: 78a0a332 rcwsswpa x0, x18, \[x25\] +.*: 78b0a022 rcwsswpa x16, x2, \[x1\] +.*: 78b0a032 rcwsswpa x16, x18, \[x1\] +.*: 78b0a102 rcwsswpa x16, x2, \[x8\] +.*: 78b0a112 rcwsswpa x16, x18, \[x8\] +.*: 78b0a222 rcwsswpa x16, x2, \[x17\] +.*: 78b0a232 rcwsswpa x16, x18, \[x17\] +.*: 78b0a322 rcwsswpa x16, x2, \[x25\] +.*: 78b0a332 rcwsswpa x16, x18, \[x25\] +.*: 78e0a022 rcwsswpal x0, x2, \[x1\] +.*: 78e0a032 rcwsswpal x0, x18, \[x1\] +.*: 78e0a102 rcwsswpal x0, x2, \[x8\] +.*: 78e0a112 rcwsswpal x0, x18, \[x8\] +.*: 78e0a222 rcwsswpal x0, x2, \[x17\] +.*: 78e0a232 rcwsswpal x0, x18, \[x17\] +.*: 78e0a322 rcwsswpal x0, x2, \[x25\] +.*: 78e0a332 rcwsswpal x0, x18, \[x25\] +.*: 78f0a022 rcwsswpal x16, x2, \[x1\] +.*: 78f0a032 rcwsswpal x16, x18, \[x1\] +.*: 78f0a102 rcwsswpal x16, x2, \[x8\] +.*: 78f0a112 rcwsswpal x16, x18, \[x8\] +.*: 78f0a222 rcwsswpal x16, x2, \[x17\] +.*: 78f0a232 rcwsswpal x16, x18, \[x17\] +.*: 78f0a322 rcwsswpal x16, x2, \[x25\] +.*: 78f0a332 rcwsswpal x16, x18, \[x25\] +.*: 7860a022 rcwsswpl x0, x2, \[x1\] +.*: 7860a032 rcwsswpl x0, x18, \[x1\] +.*: 7860a102 rcwsswpl x0, x2, \[x8\] +.*: 7860a112 rcwsswpl x0, x18, \[x8\] +.*: 7860a222 rcwsswpl x0, x2, \[x17\] +.*: 7860a232 rcwsswpl x0, x18, \[x17\] +.*: 7860a322 rcwsswpl x0, x2, \[x25\] +.*: 7860a332 rcwsswpl x0, x18, \[x25\] +.*: 7870a022 rcwsswpl x16, x2, \[x1\] +.*: 7870a032 rcwsswpl x16, x18, \[x1\] +.*: 7870a102 rcwsswpl x16, x2, \[x8\] +.*: 7870a112 rcwsswpl x16, x18, \[x8\] +.*: 7870a222 rcwsswpl x16, x2, \[x17\] +.*: 7870a232 rcwsswpl x16, x18, \[x17\] +.*: 7870a322 rcwsswpl x16, x2, \[x25\] +.*: 7870a332 rcwsswpl x16, x18, \[x25\] +.*: 3820b022 rcwset x0, x2, \[x1\] +.*: 3820b032 rcwset x0, x18, \[x1\] +.*: 3820b102 rcwset x0, x2, \[x8\] +.*: 3820b112 rcwset x0, x18, \[x8\] +.*: 3820b222 rcwset x0, x2, \[x17\] +.*: 3820b232 rcwset x0, x18, \[x17\] +.*: 3820b322 rcwset x0, x2, \[x25\] +.*: 3820b332 rcwset x0, x18, \[x25\] +.*: 3830b022 rcwset x16, x2, \[x1\] +.*: 3830b032 rcwset x16, x18, \[x1\] +.*: 3830b102 rcwset x16, x2, \[x8\] +.*: 3830b112 rcwset x16, x18, \[x8\] +.*: 3830b222 rcwset x16, x2, \[x17\] +.*: 3830b232 rcwset x16, x18, \[x17\] +.*: 3830b322 rcwset x16, x2, \[x25\] +.*: 3830b332 rcwset x16, x18, \[x25\] +.*: 38a0b022 rcwseta x0, x2, \[x1\] +.*: 38a0b032 rcwseta x0, x18, \[x1\] +.*: 38a0b102 rcwseta x0, x2, \[x8\] +.*: 38a0b112 rcwseta x0, x18, \[x8\] +.*: 38a0b222 rcwseta x0, x2, \[x17\] +.*: 38a0b232 rcwseta x0, x18, \[x17\] +.*: 38a0b322 rcwseta x0, x2, \[x25\] +.*: 38a0b332 rcwseta x0, x18, \[x25\] +.*: 38b0b022 rcwseta x16, x2, \[x1\] +.*: 38b0b032 rcwseta x16, x18, \[x1\] +.*: 38b0b102 rcwseta x16, x2, \[x8\] +.*: 38b0b112 rcwseta x16, x18, \[x8\] +.*: 38b0b222 rcwseta x16, x2, \[x17\] +.*: 38b0b232 rcwseta x16, x18, \[x17\] +.*: 38b0b322 rcwseta x16, x2, \[x25\] +.*: 38b0b332 rcwseta x16, x18, \[x25\] +.*: 38e0b022 rcwsetal x0, x2, \[x1\] +.*: 38e0b032 rcwsetal x0, x18, \[x1\] +.*: 38e0b102 rcwsetal x0, x2, \[x8\] +.*: 38e0b112 rcwsetal x0, x18, \[x8\] +.*: 38e0b222 rcwsetal x0, x2, \[x17\] +.*: 38e0b232 rcwsetal x0, x18, \[x17\] +.*: 38e0b322 rcwsetal x0, x2, \[x25\] +.*: 38e0b332 rcwsetal x0, x18, \[x25\] +.*: 38f0b022 rcwsetal x16, x2, \[x1\] +.*: 38f0b032 rcwsetal x16, x18, \[x1\] +.*: 38f0b102 rcwsetal x16, x2, \[x8\] +.*: 38f0b112 rcwsetal x16, x18, \[x8\] +.*: 38f0b222 rcwsetal x16, x2, \[x17\] +.*: 38f0b232 rcwsetal x16, x18, \[x17\] +.*: 38f0b322 rcwsetal x16, x2, \[x25\] +.*: 38f0b332 rcwsetal x16, x18, \[x25\] +.*: 3860b022 rcwsetl x0, x2, \[x1\] +.*: 3860b032 rcwsetl x0, x18, \[x1\] +.*: 3860b102 rcwsetl x0, x2, \[x8\] +.*: 3860b112 rcwsetl x0, x18, \[x8\] +.*: 3860b222 rcwsetl x0, x2, \[x17\] +.*: 3860b232 rcwsetl x0, x18, \[x17\] +.*: 3860b322 rcwsetl x0, x2, \[x25\] +.*: 3860b332 rcwsetl x0, x18, \[x25\] +.*: 3870b022 rcwsetl x16, x2, \[x1\] +.*: 3870b032 rcwsetl x16, x18, \[x1\] +.*: 3870b102 rcwsetl x16, x2, \[x8\] +.*: 3870b112 rcwsetl x16, x18, \[x8\] +.*: 3870b222 rcwsetl x16, x2, \[x17\] +.*: 3870b232 rcwsetl x16, x18, \[x17\] +.*: 3870b322 rcwsetl x16, x2, \[x25\] +.*: 3870b332 rcwsetl x16, x18, \[x25\] +.*: 7820b022 rcwsset x0, x2, \[x1\] +.*: 7820b032 rcwsset x0, x18, \[x1\] +.*: 7820b102 rcwsset x0, x2, \[x8\] +.*: 7820b112 rcwsset x0, x18, \[x8\] +.*: 7820b222 rcwsset x0, x2, \[x17\] +.*: 7820b232 rcwsset x0, x18, \[x17\] +.*: 7820b322 rcwsset x0, x2, \[x25\] +.*: 7820b332 rcwsset x0, x18, \[x25\] +.*: 7830b022 rcwsset x16, x2, \[x1\] +.*: 7830b032 rcwsset x16, x18, \[x1\] +.*: 7830b102 rcwsset x16, x2, \[x8\] +.*: 7830b112 rcwsset x16, x18, \[x8\] +.*: 7830b222 rcwsset x16, x2, \[x17\] +.*: 7830b232 rcwsset x16, x18, \[x17\] +.*: 7830b322 rcwsset x16, x2, \[x25\] +.*: 7830b332 rcwsset x16, x18, \[x25\] +.*: 78a0b022 rcwsseta x0, x2, \[x1\] +.*: 78a0b032 rcwsseta x0, x18, \[x1\] +.*: 78a0b102 rcwsseta x0, x2, \[x8\] +.*: 78a0b112 rcwsseta x0, x18, \[x8\] +.*: 78a0b222 rcwsseta x0, x2, \[x17\] +.*: 78a0b232 rcwsseta x0, x18, \[x17\] +.*: 78a0b322 rcwsseta x0, x2, \[x25\] +.*: 78a0b332 rcwsseta x0, x18, \[x25\] +.*: 78b0b022 rcwsseta x16, x2, \[x1\] +.*: 78b0b032 rcwsseta x16, x18, \[x1\] +.*: 78b0b102 rcwsseta x16, x2, \[x8\] +.*: 78b0b112 rcwsseta x16, x18, \[x8\] +.*: 78b0b222 rcwsseta x16, x2, \[x17\] +.*: 78b0b232 rcwsseta x16, x18, \[x17\] +.*: 78b0b322 rcwsseta x16, x2, \[x25\] +.*: 78b0b332 rcwsseta x16, x18, \[x25\] +.*: 78e0b022 rcwssetal x0, x2, \[x1\] +.*: 78e0b032 rcwssetal x0, x18, \[x1\] +.*: 78e0b102 rcwssetal x0, x2, \[x8\] +.*: 78e0b112 rcwssetal x0, x18, \[x8\] +.*: 78e0b222 rcwssetal x0, x2, \[x17\] +.*: 78e0b232 rcwssetal x0, x18, \[x17\] +.*: 78e0b322 rcwssetal x0, x2, \[x25\] +.*: 78e0b332 rcwssetal x0, x18, \[x25\] +.*: 78f0b022 rcwssetal x16, x2, \[x1\] +.*: 78f0b032 rcwssetal x16, x18, \[x1\] +.*: 78f0b102 rcwssetal x16, x2, \[x8\] +.*: 78f0b112 rcwssetal x16, x18, \[x8\] +.*: 78f0b222 rcwssetal x16, x2, \[x17\] +.*: 78f0b232 rcwssetal x16, x18, \[x17\] +.*: 78f0b322 rcwssetal x16, x2, \[x25\] +.*: 78f0b332 rcwssetal x16, x18, \[x25\] +.*: 7860b022 rcwssetl x0, x2, \[x1\] +.*: 7860b032 rcwssetl x0, x18, \[x1\] +.*: 7860b102 rcwssetl x0, x2, \[x8\] +.*: 7860b112 rcwssetl x0, x18, \[x8\] +.*: 7860b222 rcwssetl x0, x2, \[x17\] +.*: 7860b232 rcwssetl x0, x18, \[x17\] +.*: 7860b322 rcwssetl x0, x2, \[x25\] +.*: 7860b332 rcwssetl x0, x18, \[x25\] +.*: 7870b022 rcwssetl x16, x2, \[x1\] +.*: 7870b032 rcwssetl x16, x18, \[x1\] +.*: 7870b102 rcwssetl x16, x2, \[x8\] +.*: 7870b112 rcwssetl x16, x18, \[x8\] +.*: 7870b222 rcwssetl x16, x2, \[x17\] +.*: 7870b232 rcwssetl x16, x18, \[x17\] +.*: 7870b322 rcwssetl x16, x2, \[x25\] +.*: 7870b332 rcwssetl x16, x18, \[x25\] diff --git a/gas/testsuite/gas/aarch64/the-1.s b/gas/testsuite/gas/aarch64/the-1.s new file mode 100644 index 0000000..7432373 --- /dev/null +++ b/gas/testsuite/gas/aarch64/the-1.s @@ -0,0 +1,10 @@ + .text + .irp op cas, casa, casal, casl, scas, scasa, scasal, scasl, clr, clra, clral, clrl, sclr, sclra, sclral, sclrl, swp, swpa, swpal, swpl, sswp, sswpa, sswpal, sswpl, set, seta, setal, setl, sset, sseta, ssetal, ssetl + .irp reg1 x0, x16 + .irp reg2 x1, x8, x17, x25 + .irp reg3 x2, x18 + rcw\op \reg1, \reg3, [\reg2] + .endr + .endr + .endr + .endr diff --git a/gas/testsuite/gas/aarch64/the-bad-1.d b/gas/testsuite/gas/aarch64/the-bad-1.d new file mode 100644 index 0000000..238ce59 --- /dev/null +++ b/gas/testsuite/gas/aarch64/the-bad-1.d @@ -0,0 +1,4 @@ +#name: Illegal test of FEAT_THE instructions. +#source: the-1.s +#as: -march=armv9.4-a +#error_output: the-bad-1.l diff --git a/gas/testsuite/gas/aarch64/the-bad-1.l b/gas/testsuite/gas/aarch64/the-bad-1.l new file mode 100644 index 0000000..99e49f3 --- /dev/null +++ b/gas/testsuite/gas/aarch64/the-bad-1.l @@ -0,0 +1,513 @@ +[^ :]+: Assembler messages: +.*: Error: selected processor does not support `rcwcas x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcas x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcas x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcas x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcas x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcas x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcas x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcas x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcas x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcas x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcas x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcas x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcas x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcas x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcas x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcas x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcasa x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcasa x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcasa x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcasa x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcasa x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcasa x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcasa x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcasa x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcasa x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcasa x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcasa x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcasa x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcasa x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcasa x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcasa x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcasa x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcasal x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcasal x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcasal x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcasal x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcasal x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcasal x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcasal x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcasal x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcasal x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcasal x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcasal x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcasal x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcasal x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcasal x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcasal x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcasal x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcasl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcasl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcasl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcasl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcasl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcasl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcasl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcasl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwcasl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwcasl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwcasl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwcasl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwcasl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwcasl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwcasl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwcasl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscas x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscas x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscas x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscas x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscas x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscas x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscas x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscas x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscas x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscas x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscas x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscas x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscas x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscas x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscas x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscas x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscasa x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscasa x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscasa x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscasa x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscasa x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscasa x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscasa x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscasa x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscasa x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscasa x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscasa x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscasa x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscasa x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscasa x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscasa x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscasa x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscasal x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscasal x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscasal x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscasal x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscasal x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscasal x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscasal x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscasal x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscasal x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscasal x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscasal x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscasal x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscasal x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscasal x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscasal x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscasal x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscasl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscasl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscasl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscasl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscasl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscasl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscasl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscasl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwscasl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwscasl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwscasl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwscasl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwscasl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwscasl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwscasl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwscasl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclr x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclr x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclr x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclr x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclr x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclr x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclr x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclr x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclr x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclr x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclr x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclr x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclr x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclr x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclr x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclr x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclra x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclra x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclra x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclra x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclra x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclra x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclra x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclra x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclra x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclra x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclra x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclra x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclra x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclra x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclra x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclra x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclral x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclral x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclral x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclral x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclral x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclral x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclral x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclral x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclral x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclral x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclral x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclral x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclral x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclral x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclral x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclral x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclrl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclrl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclrl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclrl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclrl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclrl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclrl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclrl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwclrl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwclrl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwclrl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwclrl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwclrl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwclrl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwclrl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwclrl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclr x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclr x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclr x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclr x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclr x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclr x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclr x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclr x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclr x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclr x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclr x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclr x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclr x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclr x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclr x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclr x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclra x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclra x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclra x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclra x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclra x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclra x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclra x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclra x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclra x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclra x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclra x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclra x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclra x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclra x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclra x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclra x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclral x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclral x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclral x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclral x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclral x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclral x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclral x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclral x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclral x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclral x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclral x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclral x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclral x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclral x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclral x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclral x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclrl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclrl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclrl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclrl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclrl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclrl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclrl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclrl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsclrl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsclrl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsclrl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsclrl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsclrl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsclrl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsclrl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsclrl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswp x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswp x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswp x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswp x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswp x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswp x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswp x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswp x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswp x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswp x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswp x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswp x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswp x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswp x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswp x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswp x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswpa x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswpa x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswpa x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswpa x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswpa x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswpa x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswpa x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswpa x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswpa x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswpa x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswpa x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswpa x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswpa x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswpa x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswpa x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswpa x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswpal x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswpal x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswpal x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswpal x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswpal x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswpal x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswpal x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswpal x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswpal x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswpal x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswpal x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswpal x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswpal x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswpal x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswpal x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswpal x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswpl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswpl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswpl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswpl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswpl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswpl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswpl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswpl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwswpl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwswpl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwswpl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwswpl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwswpl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwswpl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwswpl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwswpl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswp x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswp x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswp x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswp x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswp x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswp x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswp x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswp x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswp x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswp x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswp x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswp x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswp x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswp x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswp x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswp x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswpa x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswpa x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswpa x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswpa x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswpa x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswpa x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswpa x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswpa x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswpa x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswpa x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswpa x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswpa x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswpa x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswpa x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswpa x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswpa x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswpal x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswpal x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswpal x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswpal x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswpal x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswpal x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswpal x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswpal x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswpal x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswpal x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswpal x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswpal x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswpal x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswpal x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswpal x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswpal x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswpl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswpl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswpl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswpl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswpl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswpl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswpl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswpl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsswpl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsswpl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsswpl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsswpl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsswpl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsswpl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsswpl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsswpl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwset x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwset x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwset x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwset x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwset x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwset x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwset x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwset x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwset x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwset x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwset x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwset x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwset x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwset x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwset x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwset x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwseta x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwseta x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwseta x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwseta x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwseta x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwseta x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwseta x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwseta x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwseta x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwseta x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwseta x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwseta x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwseta x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwseta x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwseta x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwseta x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsetal x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsetal x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsetal x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsetal x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsetal x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsetal x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsetal x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsetal x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsetal x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsetal x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsetal x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsetal x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsetal x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsetal x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsetal x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsetal x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsetl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsetl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsetl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsetl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsetl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsetl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsetl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsetl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsetl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsetl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsetl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsetl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsetl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsetl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsetl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsetl x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsset x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsset x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsset x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsset x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsset x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsset x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsset x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsset x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsset x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsset x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsset x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsset x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsset x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsset x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsset x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsset x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsseta x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsseta x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsseta x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsseta x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsseta x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsseta x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsseta x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsseta x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwsseta x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwsseta x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwsseta x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwsseta x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwsseta x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwsseta x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwsseta x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwsseta x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwssetal x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwssetal x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwssetal x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwssetal x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwssetal x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwssetal x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwssetal x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwssetal x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwssetal x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwssetal x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwssetal x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwssetal x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwssetal x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwssetal x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwssetal x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwssetal x16,x18,\[x25\]' +.*: Error: selected processor does not support `rcwssetl x0,x2,\[x1\]' +.*: Error: selected processor does not support `rcwssetl x0,x18,\[x1\]' +.*: Error: selected processor does not support `rcwssetl x0,x2,\[x8\]' +.*: Error: selected processor does not support `rcwssetl x0,x18,\[x8\]' +.*: Error: selected processor does not support `rcwssetl x0,x2,\[x17\]' +.*: Error: selected processor does not support `rcwssetl x0,x18,\[x17\]' +.*: Error: selected processor does not support `rcwssetl x0,x2,\[x25\]' +.*: Error: selected processor does not support `rcwssetl x0,x18,\[x25\]' +.*: Error: selected processor does not support `rcwssetl x16,x2,\[x1\]' +.*: Error: selected processor does not support `rcwssetl x16,x18,\[x1\]' +.*: Error: selected processor does not support `rcwssetl x16,x2,\[x8\]' +.*: Error: selected processor does not support `rcwssetl x16,x18,\[x8\]' +.*: Error: selected processor does not support `rcwssetl x16,x2,\[x17\]' +.*: Error: selected processor does not support `rcwssetl x16,x18,\[x17\]' +.*: Error: selected processor does not support `rcwssetl x16,x2,\[x25\]' +.*: Error: selected processor does not support `rcwssetl x16,x18,\[x25\]' diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index a459887..a13fdcd 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -959,6 +959,7 @@ enum aarch64_insn_class bfloat16, cssc, gcs, + the, }; /* Opcode enumerators. */ diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index b543bd3..cfaecb5 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -7019,11 +7019,99 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx111000xx1xxxxx101000xxxxxxxxxx - st64bv0. */ - return 994; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000001xxxxx101000xxxxxxxxxx + rcwswp. */ + return 3247; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01111000001xxxxx101000xxxxxxxxxx + rcwsswp. */ + return 3255; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11111000001xxxxx101000xxxxxxxxxx + st64bv0. */ + return 994; + } + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000101xxxxx101000xxxxxxxxxx + rcwswpa. */ + return 3248; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000101xxxxx101000xxxxxxxxxx + rcwsswpa. */ + return 3256; + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000011xxxxx101000xxxxxxxxxx + rcwswpl. */ + return 3250; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000011xxxxx101000xxxxxxxxxx + rcwsswpl. */ + return 3258; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000111xxxxx101000xxxxxxxxxx + rcwswpal. */ + return 3249; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000111xxxxx101000xxxxxxxxxx + rcwsswpal. */ + return 3257; + } + } + } } } else @@ -7294,11 +7382,99 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx111000xx1xxxxx100100xxxxxxxxxx - st64b. */ - return 992; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000001xxxxx100100xxxxxxxxxx + rcwclr. */ + return 3215; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01111000001xxxxx100100xxxxxxxxxx + rcwsclr. */ + return 3223; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11111000001xxxxx100100xxxxxxxxxx + st64b. */ + return 992; + } + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000101xxxxx100100xxxxxxxxxx + rcwclra. */ + return 3216; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000101xxxxx100100xxxxxxxxxx + rcwsclra. */ + return 3224; + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000011xxxxx100100xxxxxxxxxx + rcwclrl. */ + return 3218; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000011xxxxx100100xxxxxxxxxx + rcwsclrl. */ + return 3226; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000111xxxxx100100xxxxxxxxxx + rcwclral. */ + return 3217; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000111xxxxx100100xxxxxxxxxx + rcwsclral. */ + return 3225; + } + } + } } } else @@ -7577,11 +7753,99 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx111000xx1xxxxx101100xxxxxxxxxx - st64bv. */ - return 993; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000001xxxxx101100xxxxxxxxxx + rcwset. */ + return 3231; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01111000001xxxxx101100xxxxxxxxxx + rcwsset. */ + return 3239; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11111000001xxxxx101100xxxxxxxxxx + st64bv. */ + return 993; + } + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000101xxxxx101100xxxxxxxxxx + rcwseta. */ + return 3232; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000101xxxxx101100xxxxxxxxxx + rcwsseta. */ + return 3240; + } + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000011xxxxx101100xxxxxxxxxx + rcwsetl. */ + return 3234; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000011xxxxx101100xxxxxxxxxx + rcwssetl. */ + return 3242; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0111000111xxxxx101100xxxxxxxxxx + rcwsetal. */ + return 3233; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1111000111xxxxx101100xxxxxxxxxx + rcwssetal. */ + return 3241; + } + } + } } } else @@ -8101,51 +8365,139 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 12) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001001xxxxx0xx000xxxxxxxxxx - stzgm. */ - return 964; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001001xxxxx0x0000xxxxxxxxxx + stzgm. */ + return 964; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001001xxxxx1x0000xxxxxxxxxx + swpp. */ + return 1194; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001001xxxxx1xx000xxxxxxxxxx - swpp. */ - return 1194; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001001xxxxxxx1000xxxxxxxxxx + rcwswpp. */ + return 3251; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001001xxxxxxx1000xxxxxxxxxx + rcwsswpp. */ + return 3259; + } } } else { if (((word >> 13) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001001xxxxxxx0100xxxxxxxxxx - ldclrp. */ - return 1186; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001001xxxxx0x0100xxxxxxxxxx + ldclrp. */ + return 1186; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001001xxxxx1x0100xxxxxxxxxx + rcwclrp. */ + return 3219; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001001xxxxx1x0100xxxxxxxxxx + rcwsclrp. */ + return 3227; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001001xxxxxxx1100xxxxxxxxxx - ldsetp. */ - return 1190; + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001001xxxxx0x1100xxxxxxxxxx + ldsetp. */ + return 1190; + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001001xxxxx1x1100xxxxxxxxxx + rcwsetp. */ + return 3235; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001001xxxxx1x1100xxxxxxxxxx + rcwssetp. */ + return 3243; + } + } } } } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100100xxxxxxxxxx10xxxxxxxxxx - stg. */ - return 881; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x001100100xxxxxxxxxx10xxxxxxxxxx + rcwcas. */ + return 3199; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0101100100xxxxxxxxxx10xxxxxxxxxx + rcwscas. */ + return 3207; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 1101100100xxxxxxxxxx10xxxxxxxxxx + stg. */ + return 881; + } + } } } else @@ -8347,11 +8699,33 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001001xxxxxxxxxx1xxxxxxxxxx - stg. */ - return 885; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001001xxxxxxxxxx1xxxxxxxxxx + rcwcasp. */ + return 3203; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001001xxxxxxxxxx1xxxxxxxxxx + rcwscasp. */ + return 3211; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11011001001xxxxxxxxxx1xxxxxxxxxx + stg. */ + return 885; + } + } } } } @@ -8441,49 +8815,137 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 12) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x0011001011xxxxxxxx000xxxxxxxxxx - swppl. */ - return 1197; - } - else - { if (((word >> 13) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0011001011xxxxxxx0100xxxxxxxxxx - ldclrpl. */ - return 1189; + x0011001011xxxxxxx0000xxxxxxxxxx + swppl. */ + return 1197; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x0011001011xxxxxxx1100xxxxxxxxxx - ldsetpl. */ - return 1193; + x0011001011xxxxxxx1000xxxxxxxxxx + rcwswppl. */ + return 3254; + } + } + else + { + if (((word >> 13) & 0x1) == 0) + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001011xxxxx0x0100xxxxxxxxxx + ldclrpl. */ + return 1189; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001011xxxxx1x0100xxxxxxxxxx + rcwclrpl. */ + return 3222; + } + } + else + { + if (((word >> 15) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001011xxxxx0x1100xxxxxxxxxx + ldsetpl. */ + return 1193; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001011xxxxx1x1100xxxxxxxxxx + rcwsetpl. */ + return 3238; + } } } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1011001011xxxxxxxxx00xxxxxxxxxx - ldg. */ - return 934; + if (((word >> 31) & 0x1) == 0) + { + if (((word >> 12) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001011xxxxxxxx000xxxxxxxxxx + rcwsswppl. */ + return 3262; + } + else + { + if (((word >> 13) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001011xxxxxxx0100xxxxxxxxxx + rcwsclrpl. */ + return 3230; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001011xxxxxxx1100xxxxxxxxxx + rcwssetpl. */ + return 3246; + } + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11011001011xxxxxxxxx00xxxxxxxxxx + ldg. */ + return 934; + } } } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100101xxxxxxxxxx10xxxxxxxxxx - stzg. */ - return 882; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x001100101xxxxxxxxxx10xxxxxxxxxx + rcwcasl. */ + return 3202; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0101100101xxxxxxxxxx10xxxxxxxxxx + rcwscasl. */ + return 3210; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 1101100101xxxxxxxxxx10xxxxxxxxxx + stzg. */ + return 882; + } + } } } else @@ -8663,11 +9125,33 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001011xxxxxxxxxx1xxxxxxxxxx - stzg. */ - return 886; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001011xxxxxxxxxx1xxxxxxxxxx + rcwcaspl. */ + return 3206; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001011xxxxxxxxxx1xxxxxxxxxx + rcwscaspl. */ + return 3214; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11011001011xxxxxxxxxx1xxxxxxxxxx + stzg. */ + return 886; + } + } } } } @@ -8767,42 +9251,86 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 12) & 0x1) == 0) { - if (((word >> 15) & 0x1) == 0) + if (((word >> 13) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001101xxxxx0xx000xxxxxxxxxx - stgm. */ - return 963; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001101xxxxx0x0000xxxxxxxxxx + stgm. */ + return 963; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001111xxxxx0x0000xxxxxxxxxx + ldgm. */ + return 962; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001111xxxxx0xx000xxxxxxxxxx - ldgm. */ - return 962; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001101xxxxx1x0000xxxxxxxxxx + swppa. */ + return 1195; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001111xxxxx1x0000xxxxxxxxxx + swppal. */ + return 1196; + } } } else { if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001101xxxxx1xx000xxxxxxxxxx - swppa. */ - return 1195; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001101xxxxxxx1000xxxxxxxxxx + rcwswppa. */ + return 3252; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001101xxxxxxx1000xxxxxxxxxx + rcwsswppa. */ + return 3260; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001111xxxxx1xx000xxxxxxxxxx - swppal. */ - return 1196; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001111xxxxxxx1000xxxxxxxxxx + rcwswppal. */ + return 3253; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001111xxxxxxx1000xxxxxxxxxx + rcwsswppal. */ + return 3261; + } } } } @@ -8810,40 +9338,128 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 13) & 0x1) == 0) { - if (((word >> 22) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001101xxxxxxx0100xxxxxxxxxx - ldclrpa. */ - return 1187; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001101xxxxx0x0100xxxxxxxxxx + ldclrpa. */ + return 1187; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001111xxxxx0x0100xxxxxxxxxx + ldclrpal. */ + return 1188; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001111xxxxxxx0100xxxxxxxxxx - ldclrpal. */ - return 1188; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001101xxxxx1x0100xxxxxxxxxx + rcwclrpa. */ + return 3220; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001101xxxxx1x0100xxxxxxxxxx + rcwsclrpa. */ + return 3228; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001111xxxxx1x0100xxxxxxxxxx + rcwclrpal. */ + return 3221; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001111xxxxx1x0100xxxxxxxxxx + rcwsclrpal. */ + return 3229; + } + } } } else { - if (((word >> 22) & 0x1) == 0) + if (((word >> 15) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001101xxxxxxx1100xxxxxxxxxx - ldsetpa. */ - return 1191; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001101xxxxx0x1100xxxxxxxxxx + ldsetpa. */ + return 1191; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + xx011001111xxxxx0x1100xxxxxxxxxx + ldsetpal. */ + return 1192; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001111xxxxxxx1100xxxxxxxxxx - ldsetpal. */ - return 1192; + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001101xxxxx1x1100xxxxxxxxxx + rcwsetpa. */ + return 3236; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001101xxxxx1x1100xxxxxxxxxx + rcwssetpa. */ + return 3244; + } + } + else + { + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001111xxxxx1x1100xxxxxxxxxx + rcwsetpal. */ + return 3237; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1011001111xxxxx1x1100xxxxxxxxxx + rcwssetpal. */ + return 3245; + } + } } } } @@ -8853,19 +9469,63 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100110xxxxxxxxxx10xxxxxxxxxx - st2g. */ - return 883; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x001100110xxxxxxxxxx10xxxxxxxxxx + rcwcasa. */ + return 3200; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0101100110xxxxxxxxxx10xxxxxxxxxx + rcwscasa. */ + return 3208; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 1101100110xxxxxxxxxx10xxxxxxxxxx + st2g. */ + return 883; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx01100111xxxxxxxxxx10xxxxxxxxxx - stz2g. */ - return 884; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x001100111xxxxxxxxxx10xxxxxxxxxx + rcwcasal. */ + return 3201; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 0101100111xxxxxxxxxx10xxxxxxxxxx + rcwscasal. */ + return 3209; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 1101100111xxxxxxxxxx10xxxxxxxxxx + stz2g. */ + return 884; + } + } } } } @@ -9180,19 +9840,63 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001101xxxxxxxxxx1xxxxxxxxxx - st2g. */ - return 887; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001101xxxxxxxxxx1xxxxxxxxxx + rcwcaspa. */ + return 3204; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001101xxxxxxxxxx1xxxxxxxxxx + rcwscaspa. */ + return 3212; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11011001101xxxxxxxxxx1xxxxxxxxxx + st2g. */ + return 887; + } + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx011001111xxxxxxxxxx1xxxxxxxxxx - stz2g. */ - return 888; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0011001111xxxxxxxxxx1xxxxxxxxxx + rcwcaspal. */ + return 3205; + } + else + { + if (((word >> 31) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 01011001111xxxxxxxxxx1xxxxxxxxxx + rcwscaspal. */ + return 3213; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + 11011001111xxxxxxxxxx1xxxxxxxxxx + stz2g. */ + return 888; + } + } } } } diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 288b3dd..2ddeca9 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1189,6 +1189,12 @@ QLF5(X, X, X, X, NIL), \ } +/* e.g. RCWCASP <Xt1>, <Xt1+1>, <Xt2>, <Xt2+1>, [<Xn|SP>{,#0}]. */ +#define QL_X4NIL \ +{ \ + QLF5(X, X, X, X, NIL), \ +} + /* e.g. STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}]. */ #define QL_R3_LDST_EXC \ { \ @@ -2604,6 +2610,10 @@ static const aarch64_feature_set aarch64_feature_ite = AARCH64_FEATURE (ITE); static const aarch64_feature_set aarch64_feature_d128 = AARCH64_FEATURE (D128); +static const aarch64_feature_set aarch64_feature_the = + AARCH64_FEATURE (THE); +static const aarch64_feature_set aarch64_feature_d128_the = + AARCH64_FEATURES (2, D128, THE); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2668,6 +2678,8 @@ static const aarch64_feature_set aarch64_feature_d128 = #define GCS &aarch64_feature_gcs #define ITE &aarch64_feature_ite #define D128 &aarch64_feature_d128 +#define THE &aarch64_feature_the +#define D128_THE &aarch64_feature_d128_the #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2823,6 +2835,10 @@ static const aarch64_feature_set aarch64_feature_d128 = { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } #define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } +#define THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, the, 0, THE, OPS, QUALS, FLAGS, 0, 0, NULL } +#define D128_THE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, the, 0, D128_THE, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -6154,6 +6170,108 @@ const struct aarch64_opcode aarch64_opcode_table[] = ITE_INSN ("trcit", 0xd50b72e0, 0xffffffe0, ic_system, OP1 (Rt), QL_I1X, F_ALIAS), +/* Read check write compare and swap doubleword in memory instructions. */ + THE_INSN("rcwcas", 0x19200800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwcasa", 0x19a00800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwcasal", 0x19e00800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwcasl", 0x19600800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write compare and swap quadword in memory instructions. */ + D128_THE_INSN("rcwcasp", 0x19200c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + D128_THE_INSN("rcwcaspa", 0x19a00c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + D128_THE_INSN("rcwcaspal", 0x19e00c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + D128_THE_INSN("rcwcaspl", 0x19600c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + +/* Read check write software compare and swap doubleword in memory + instructions. */ + THE_INSN("rcwscas", 0x59200800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwscasa", 0x59a00800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwscasal", 0x59e00800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwscasl", 0x59600800, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software compare and swap quadword in memory + instructions. */ + D128_THE_INSN("rcwscasp", 0x59200c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + D128_THE_INSN("rcwscaspa", 0x59a00c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + D128_THE_INSN("rcwscaspal", 0x59e00c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + D128_THE_INSN("rcwscaspl", 0x59600c00, 0xffe0fc00, OP5 (Rs, PAIRREG, Rt, PAIRREG, ADDR_SIMPLE), QL_X4NIL, 0), + +/* Read check write atomic bit clear on doubleword in memory instructions. */ + THE_INSN("rcwclr", 0x38209000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwclra", 0x38a09000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwclral", 0x38e09000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwclrl", 0x38609000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write atomic bit clear on quadword in memory instructions. */ + D128_THE_INSN("rcwclrp", 0x19209000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwclrpa", 0x19a09000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwclrpal", 0x19e09000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwclrpl", 0x19609000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software atomic bit clear on doubleword in memory + instructions. */ + THE_INSN("rcwsclr", 0x78209000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsclra", 0x78a09000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsclral", 0x78e09000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsclrl", 0x78609000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software atomic bit clear on quadword in memory + instructions. */ + D128_THE_INSN("rcwsclrp", 0x59209000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsclrpa", 0x59a09000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsclrpal", 0x59e09000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsclrpl", 0x59609000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write atomic bit set on doubleword in memory instructions. */ + THE_INSN("rcwset", 0x3820b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwseta", 0x38a0b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsetal", 0x38e0b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsetl", 0x3860b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write atomic bit set on quadword in memory instructions. */ + D128_THE_INSN("rcwsetp", 0x1920b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsetpa", 0x19a0b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsetpal", 0x19e0b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsetpl", 0x1960b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software atomic bit set on doubleword in memory + instructions. */ + THE_INSN("rcwsset", 0x7820b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsseta", 0x78a0b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwssetal", 0x78e0b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwssetl", 0x7860b000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software atomic bit set on quadword in memory + instructions. */ + D128_THE_INSN("rcwssetp", 0x5920b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwssetpa", 0x59a0b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwssetpal", 0x59e0b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwssetpl", 0x5960b000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write swap doubleword in memory instructions. */ + THE_INSN("rcwswp", 0x3820a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwswpa", 0x38a0a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwswpal", 0x38e0a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwswpl", 0x3860a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write swap quadword in memory instructions. */ + D128_THE_INSN("rcwswpp", 0x1920a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwswppa", 0x19a0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwswppal", 0x19e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwswppl", 0x1960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software swap doubleword in memory instructions. */ + THE_INSN("rcwsswp", 0x7820a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsswpa", 0x78a0a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsswpal", 0x78e0a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + THE_INSN("rcwsswpl", 0x7860a000, 0xffe0fc00, OP3 (Rs, Rt, ADDR_SIMPLE), QL_X2NIL, 0), + +/* Read check write software swap quadword in memory instructions. */ + D128_THE_INSN("rcwsswpp", 0x5920a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsswppa", 0x59a0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsswppal", 0x59e0a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + D128_THE_INSN("rcwsswppl", 0x5960a000, 0xffe0fc00, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, 0), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; |