diff options
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-0.d | 15 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-0.s | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-1.d | 18 | ||||
| -rw-r--r-- | gas/testsuite/gas/arc/nps400-1.s | 12 | ||||
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/arc.h | 1 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 15 | ||||
| -rw-r--r-- | opcodes/arc-nps400-tbl.h | 11 | ||||
| -rw-r--r-- | opcodes/arc-opc.c | 147 |
10 files changed, 232 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index ff3c35e4..25c0ee6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * testsuite/gas/arc/nps400-0.d: New file. + * testsuite/gas/arc/nps400-0.s: New file. + * testsuite/gas/arc/nps400-1.d: New file. + * testsuite/gas/arc/nps400-1.s: New file. + +2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * config/tc-arc.c (find_opcode_match): Move lnflg, and i declarations to start of block. Reset code on all flags before attempting to match them. Handle multiple hits on the same flag. diff --git a/gas/testsuite/gas/arc/nps400-0.d b/gas/testsuite/gas/arc/nps400-0.d new file mode 100644 index 0000000..a34a4d5 --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-0.d @@ -0,0 +1,15 @@ +#as: -mcpu=nps400 +#readelf: -h + +#... + Class: ELF32 + Data: 2's complement, .* endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: ARCompact + Version: 0x1 +#... + Flags: 0x307, NPS400, v3 no-legacy-syscalls ABI +#...
\ No newline at end of file diff --git a/gas/testsuite/gas/arc/nps400-0.s b/gas/testsuite/gas/arc/nps400-0.s new file mode 100644 index 0000000..2b6cc1d --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-0.s @@ -0,0 +1,2 @@ + .text + nop diff --git a/gas/testsuite/gas/arc/nps400-1.d b/gas/testsuite/gas/arc/nps400-1.d new file mode 100644 index 0000000..294356a --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-1.d @@ -0,0 +1,18 @@ +#as: -mcpu=nps400 +#objdump: -dr + +.*: +file format .*arc.* + +Disassembly of section .text: + +[0-9a-f]+ <.*>: + 0: 4821 1485 movb r0,r0,r1,0x4,0x5,0x6 + 4: 4881 1485 movb r0,r0,r12,0x4,0x5,0x6 + 8: 4f81 1485 movb r15,r15,r12,0x4,0x5,0x6 + c: 4821 9485 movb.cl r0,r1,0x4,0x5,0x6 + 10: 48c1 9485 movb.cl r0,r14,0x4,0x5,0x6 + 14: 4d21 9485 movb.cl r13,r1,0x4,0x5,0x6 + 18: 4808 04d2 movh r0,r0,0x4d2 + 1c: 4868 ffff movh r3,r3,0xffff + 20: 4818 04d2 movh.cl r0,0x4d2 + 24: 4878 ffff movh.cl r3,0xffff diff --git a/gas/testsuite/gas/arc/nps400-1.s b/gas/testsuite/gas/arc/nps400-1.s new file mode 100644 index 0000000..34d43d0 --- /dev/null +++ b/gas/testsuite/gas/arc/nps400-1.s @@ -0,0 +1,12 @@ + .text + movb r0, r0, r1, 4, 5, 6 + movb r0, r0, r12, 4, 5, 6 + movb r15, r15, r12, 4, 5, 6 + movb.cl r0, r1, 4, 5, 6 + movb.cl r0, r14, 4, 5, 6 + movb.cl r13, r1, 4, 5, 6 + + movh r0, r0, 1234 + movh r3, r3, 0xffff + movh.cl r0, 1234 + movh.cl r3, 0xffff diff --git a/include/ChangeLog b/include/ChangeLog index edb91ea..b99c7c6 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * opcodes/arc.h (insn_class_t): Add BITOP type. + +2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * opcode/arc.h (flag_class_t): Remove all old flag classes, add 3 new classes instead. diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 3310c10..ee2ebfa 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -46,6 +46,7 @@ typedef enum KERNEL, LOGICAL, MEMORY, + BITOP, } insn_class_t; /* Instruction Subclass. */ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 10ebb87..811450d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,20 @@ 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * arc-nps400-tbl.h: New file. + * arc-opc.c: Add top level comment. + (insert_nps_3bit_dst): New function. + (extract_nps_3bit_dst): New function. + (insert_nps_3bit_src2): New function. + (extract_nps_3bit_src2): New function. + (insert_nps_bitop_size): New function. + (extract_nps_bitop_size): New function. + (arc_flag_operands): Add nps400 entries. + (arc_flag_classes): Add nps400 entries. + (arc_operands): Add nps400 entries. + (arc_opcodes): Add nps400 include. + +2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com> + * arc-opc.c (arc_flag_classes): Convert all flag classes to use the new class enum values. diff --git a/opcodes/arc-nps400-tbl.h b/opcodes/arc-nps400-tbl.h new file mode 100644 index 0000000..4b715f9 --- /dev/null +++ b/opcodes/arc-nps400-tbl.h @@ -0,0 +1,11 @@ +/* movl<.cl> */ +{ "movh", 0x48080000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, +{ "movh", 0x48180000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, + +/* movl<.cl> */ +{ "movl", 0x48090000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_R_SRC1, NPS_UIMM16 }, { 0 }}, +{ "movl", 0x48190000, 0xf81f0000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST, NPS_UIMM16 }, { C_NPS_CL }}, + +/* movb<.f><.cl> */ +{ "movb", 0x48010000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC1_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F }}, +{ "movb", 0x48018000, 0xf80f8000, ARC_OPCODE_NPS400 , BITOP, NONE, { NPS_R_DST_3B, NPS_R_SRC2_3B, NPS_BITOP_DST_POS, NPS_BITOP_SRC_POS, NPS_BITOP_SIZE }, { C_NPS_F, C_NPS_CL }}, diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c index f126fa8..82aaf1e 100644 --- a/opcodes/arc-opc.c +++ b/opcodes/arc-opc.c @@ -26,6 +26,12 @@ #include "opintl.h" #include "libiberty.h" +/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom + instructions. Support for this target is available when binutils is + configured and built for the 'arc*-mellanox-*-*' target. As far as + possible all ARC NPS400 features are built into all ARC target builds as + this reduces the chances that regressions might creep in. */ + /* Insert RB register into a 32-bit opcode. */ static unsigned insert_rb (unsigned insn, @@ -637,6 +643,104 @@ extract_g_s (unsigned insn ATTRIBUTE_UNUSED, return value; } +/* ARC NPS400 Support: See comment near head of file. */ +static unsigned +insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + switch (value) + { + case 0: + case 1: + case 2: + case 3: + insn |= value << 24; + break; + case 12: + case 13: + case 14: + case 15: + insn |= (value - 8) << 24; + break; + default: + *errmsg = _("Register must be either r0-r3 or r12-r15."); + break; + } + return insn; +} + +static int +extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 24) & 0x07; + if (value > 3) + return (value + 8); + else + return value; +} + +static unsigned +insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + switch (value) + { + case 0: + case 1: + case 2: + case 3: + insn |= value << 21; + break; + case 12: + case 13: + case 14: + case 15: + insn |= (value - 8) << 21; + break; + default: + *errmsg = _("Register must be either r0-r3 or r12-r15."); + break; + } + return insn; +} + +static int +extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + int value = (insn >> 21) & 0x07; + if (value > 3) + return (value + 8); + else + return value; +} + +static unsigned +insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED, + int value ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + if (value < 1 || value > 32) + { + *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive."); + return insn; + } + + --value; + insn |= ((value & 0x1f) << 10); + return insn; +} + +static int +extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED, + bfd_boolean * invalid ATTRIBUTE_UNUSED) +{ + return ((insn >> 10) & 0x1f) + 1; +} + /* Include the generic extract/insert functions. Order is important as some of the functions present in the .h may be disabled via defines. */ @@ -792,6 +896,13 @@ const struct arc_flag_operand arc_flag_operands[] = /* Fake Flags. */ #define F_NE (F_H17 + 1) { "ne", 0, 0, 0, 1 }, + + /* ARC NPS400 Support: See comment near head of file. */ +#define F_NPS_CL (F_NE + 1) + { "cl", 0, 0, 0, 1 }, + +#define F_NPS_FLAG (F_NPS_CL + 1) + { "f", 1, 1, 20, 1 }, }; const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands); @@ -863,6 +974,13 @@ const struct arc_flag_class arc_flag_classes[] = #define C_NE (C_AS + 1) { F_CLASS_OPTIONAL, { F_NE, F_NULL}}, + + /* ARC NPS400 Support: See comment near head of file. */ +#define C_NPS_CL (C_NE + 1) + { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}}, + +#define C_NPS_F (C_NPS_CL + 1) + { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}}, }; /* The operands table. @@ -1181,6 +1299,34 @@ const struct arc_operand arc_operands[] = /* UIMM6_5_S mask = 0000011111100000. */ #define UIMM6_5_S (W6 + 1) {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s}, + + /* ARC NPS400 Support: See comment near head of file. */ +#define NPS_R_DST_3B (UIMM6_5_S + 1) + { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, + +#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1) + { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst }, + +#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1) + { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 }, + +#define NPS_R_DST (NPS_R_SRC2_3B + 1) + { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, NULL, NULL }, + +#define NPS_R_SRC1 (NPS_R_DST + 1) + { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, NULL, NULL }, + +#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1) + { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, + +#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1) + { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 }, + +#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1) + { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size }, + +#define NPS_UIMM16 (NPS_BITOP_SIZE + 1) + { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL }, }; const unsigned arc_num_operands = ARRAY_SIZE (arc_operands); @@ -1196,6 +1342,7 @@ const unsigned arc_NToperand = FKT_NT; const struct arc_opcode arc_opcodes[] = { #include "arc-tbl.h" +#include "arc-nps400-tbl.h" }; const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes); |