diff options
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-gen.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-opc.h | 9 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 16 |
4 files changed, 20 insertions, 13 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a356fe5..ba93eef 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> + * i386-gen.c (opcode_modifiers): Use Qword instead of QWord. + * i386-opc.h: Likewise. + * i386-opc.tbl: Likewise. + +2008-01-02 H.J. Lu <hongjiu.lu@intel.com> + PR gas/5534 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 52b091a..8ae6bd0 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -279,7 +279,7 @@ static bitfield opcode_modifiers[] = BITFIELD (Byte), BITFIELD (Word), BITFIELD (Dword), - BITFIELD (QWord), + BITFIELD (Qword), BITFIELD (Xmmword), BITFIELD (FWait), BITFIELD (IsString), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 12605dd..9038730 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -175,7 +175,7 @@ typedef union i386_cpu_flags #define Size32 (Size16 + 1) /* needs size prefix if in 64-bit mode */ #define Size64 (Size32 + 1) -/* instruction ignores operand size prefix */ +/* instruction ignores operand size prefix and mnemonic size suffix */ #define IgnoreSize (Size64 + 1) /* default insn size depends on mode */ #define DefaultSize (IgnoreSize + 1) @@ -193,7 +193,8 @@ typedef union i386_cpu_flags #define No_ldSuf (No_qSuf + 1) /* x suffix on instruction illegal */ #define No_xSuf (No_ldSuf + 1) -/* check PTR size on instruction */ +/* check PTR size on instruction in Intel mode. + FIXME: Can it be merged with IgnoreSize? */ #define CheckSize (No_xSuf + 1) /* BYTE PTR on instruction */ #define Byte (CheckSize + 1) @@ -202,9 +203,9 @@ typedef union i386_cpu_flags /* DWORD PTR on instruction */ #define Dword (Word + 1) /* QWORD PTR on instruction */ -#define QWord (Dword + 1) +#define Qword (Dword + 1) /* XMMWORD PTR on instruction */ -#define Xmmword (QWord + 1) +#define Xmmword (Qword + 1) /* instruction needs FWAIT */ #define FWait (Xmmword + 1) /* quick test for string instructions */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 490835f..3c054d7 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -907,14 +907,14 @@ movd, 2, 0x660f6e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32|Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } // In the 64bit mode the short form mov immediate is redefined to have // 64bit displacement value. -movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } -movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } -movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } -movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|CheckSize|QWord|No_ldSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } -movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } -movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } -movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|QWord, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } +movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword|NoRex64, { RegMMX, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX } +movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword|NoRex64, { BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } +movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword|NoRex64, { RegXMM, BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } +movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|CheckSize|wWord|No_ldSuf, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMMX } +movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword, { RegMMX, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } +movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword, { Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM } +movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|CheckSize|Qword, { RegXMM, Reg64|BaseIndex|Disp8|Disp16|Disp32|Disp32S } // We put the 64bit displacement first and we only mark constants // larger than 32bit as Disp64. movq, 2, 0xa0, None, 1, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Disp64, Acc } |