diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 8 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/sse-noavx.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/sse-noavx.s | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-sse-noavx.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-sse-noavx.s | 2 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 4 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 4 |
8 files changed, 25 insertions, 4 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 0d8e43c..af845e2 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,11 @@ +2008-05-21 H.J. Lu <hongjiu.lu@intel.com> + + * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq. + * gas/i386/x86-64-sse-noavx.s: Likewise. + + * gas/i386/sse-noavx.d: Updated. + * gas/i386/x86-64-sse-noavx.d: Likewise. + 2008-05-09 Catherine Moore <clm@codesourcery.com> * gas/mips/mips16-hilo-match.s: New test. diff --git a/gas/testsuite/gas/i386/sse-noavx.d b/gas/testsuite/gas/i386/sse-noavx.d index f37f285..4d5b6e6 100644 --- a/gas/testsuite/gas/i386/sse-noavx.d +++ b/gas/testsuite/gas/i386/sse-noavx.d @@ -15,7 +15,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: dd 08 fisttpll \(%eax\) [ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0 [ ]*[a-f0-9]+: 0f 01 c8 monitor %eax,%ecx,%edx +[ ]*[a-f0-9]+: f2 0f d6 c8 movdq2q %xmm0,%mm1 [ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%eax\) +[ ]*[a-f0-9]+: f3 0f d6 c8 movq2dq %mm0,%xmm1 [ ]*[a-f0-9]+: 0f 01 c9 mwait %eax,%ecx [ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0 diff --git a/gas/testsuite/gas/i386/sse-noavx.s b/gas/testsuite/gas/i386/sse-noavx.s index add51a0..53f5c92 100644 --- a/gas/testsuite/gas/i386/sse-noavx.s +++ b/gas/testsuite/gas/i386/sse-noavx.s @@ -10,7 +10,9 @@ _start: fisttpll (%eax) maskmovq %mm7,%mm0 monitor + movdq2q %xmm0, %mm1 movntq %mm2,(%eax) + movq2dq %mm0, %xmm1 mwait pabsb %mm1,%mm0 pabsd %mm1,%mm0 diff --git a/gas/testsuite/gas/i386/x86-64-sse-noavx.d b/gas/testsuite/gas/i386/x86-64-sse-noavx.d index c597a1d..3c84201 100644 --- a/gas/testsuite/gas/i386/x86-64-sse-noavx.d +++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.d @@ -16,7 +16,9 @@ Disassembly of section .text: [ ]*[a-f0-9]+: dd 08 fisttpll \(%rax\) [ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0 [ ]*[a-f0-9]+: 0f 01 c8 monitor %rax,%rcx,%rdx +[ ]*[a-f0-9]+: f2 0f d6 c8 movdq2q %xmm0,%mm1 [ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%rax\) +[ ]*[a-f0-9]+: f3 0f d6 c8 movq2dq %mm0,%xmm1 [ ]*[a-f0-9]+: 0f 01 c9 mwait %rax,%rcx [ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0 [ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0 diff --git a/gas/testsuite/gas/i386/x86-64-sse-noavx.s b/gas/testsuite/gas/i386/x86-64-sse-noavx.s index 05ce292..309c928 100644 --- a/gas/testsuite/gas/i386/x86-64-sse-noavx.s +++ b/gas/testsuite/gas/i386/x86-64-sse-noavx.s @@ -11,7 +11,9 @@ _start: fisttpll (%rax) maskmovq %mm7,%mm0 monitor + movdq2q %xmm0, %mm1 movntq %mm2,(%rax) + movq2dq %mm0, %xmm1 mwait pabsb %mm1,%mm0 pabsd %mm1,%mm0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6720456..e67b93b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2008-05-21 H.J. Lu <hongjiu.lu@intel.com> + + * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. + * i386-tbl.h: Regenerated. + 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 35c0f90..3b8e234 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1453,8 +1453,8 @@ movdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|N movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM } -movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMMX } -movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, RegXMM } +movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX } +movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM } pmuludq, 2, 0x66f4, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0x660ff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM } pmuludq, 2, 0xff4, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 196cc76..76a3e1a 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -13206,7 +13206,7 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -13218,7 +13218,7 @@ const template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, |