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-rw-r--r--sim/ChangeLog6
-rw-r--r--sim/cris/traps.c12
2 files changed, 17 insertions, 1 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog
index 74f81a7..a7e59e0 100644
--- a/sim/ChangeLog
+++ b/sim/ChangeLog
@@ -1,3 +1,9 @@
+2006-02-23 Hans-Peter Nilsson <hp@axis.com>
+
+ * cris/traps.c (syscall_map): Remove CB_SYS_time / TARGET_SYS_time
+ mapping.
+ (cris_break_13_handler) <case TARGET_SYS_time>: New case.
+
2006-01-23 Jim Blandy <jimb@redhat.com>
Add simulator for Renesas M32C and M16C.
diff --git a/sim/cris/traps.c b/sim/cris/traps.c
index 48fe6c5..2eb0a1b 100644
--- a/sim/cris/traps.c
+++ b/sim/cris/traps.c
@@ -244,7 +244,6 @@ static const CB_TARGET_DEFS_MAP syscall_map[] =
{ CB_SYS_lstat, TARGET_SYS_lstat64 },
{ CB_SYS_stat, TARGET_SYS_stat64 },
{ CB_SYS_pipe, TARGET_SYS_pipe },
- { CB_SYS_time, TARGET_SYS_time },
{ CB_SYS_rename, TARGET_SYS_rename },
{ CB_SYS_truncate, TARGET_SYS_truncate },
{ CB_SYS_ftruncate, TARGET_SYS_ftruncate },
@@ -2044,6 +2043,17 @@ cris_break_13_handler (SIM_CPU *current_cpu, USI callnum, USI arg1,
break;
}
+ case TARGET_SYS_time:
+ {
+ retval = (int) (*cb->time) (cb, 0L);
+
+ /* At time of this writing, CB_SYSCALL_time doesn't do the
+ part of setting *arg1 to the return value. */
+ if (arg1)
+ sim_core_write_unaligned_4 (current_cpu, pc, 0, arg1, retval);
+ break;
+ }
+
case TARGET_SYS_gettimeofday:
if (arg1 != 0)
{