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-rw-r--r--gas/ChangeLog10
-rw-r--r--gas/testsuite/gas/riscv/alias-csr.d23
-rw-r--r--gas/testsuite/gas/riscv/alias-csr.s14
-rw-r--r--gas/testsuite/gas/riscv/no-aliases-csr.d23
-rw-r--r--gas/testsuite/gas/riscv/priv-reg.d2
-rw-r--r--opcodes/ChangeLog8
-rw-r--r--opcodes/riscv-opc.c32
7 files changed, 95 insertions, 17 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 34581e0..4d6f902 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
+ alias instructions.
+ * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
+ -Mno-aliases.
+
+ * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
+ * testsuite/gas/riscv/priv-reg.d: Update.
+
2019-07-24 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
new file mode 100644
index 0000000..af5c591
--- /dev/null
+++ b/gas/testsuite/gas/riscv/alias-csr.d
@@ -0,0 +1,23 @@
+#source: alias-csr.s
+#as: -march=rv64if
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <alias_csr>:
+[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
+[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
+[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
+[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
+[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
+[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
+[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
+[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
+[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
+[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
+[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
+[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
+[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
new file mode 100644
index 0000000..8577de1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/alias-csr.s
@@ -0,0 +1,14 @@
+alias_csr:
+ frcsr t0
+ fscsr t0, t2
+ fscsr t2
+ frrm t0
+ fsrm t0, t1
+ fsrm t1
+ fsrmi t0, 31
+ fsrmi 31
+ frflags t0
+ fsflags t0, t1
+ fsflags t1
+ fsflagsi t0, 31
+ fsflagsi 31
diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
new file mode 100644
index 0000000..2275330
--- /dev/null
+++ b/gas/testsuite/gas/riscv/no-aliases-csr.d
@@ -0,0 +1,23 @@
+#source: alias-csr.s
+#as: -march=rv64if
+#objdump: -dr -Mno-aliases
+
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <alias_csr>:
+[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
+[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
+[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
+[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
+[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
+[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
+[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
+[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
+[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
+[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
+[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
+[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
+[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
index 9ec5d97..d8ec868 100644
--- a/gas/testsuite/gas/riscv/priv-reg.d
+++ b/gas/testsuite/gas/riscv/priv-reg.d
@@ -17,7 +17,7 @@ Disassembly of section .text:
[ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
[ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
[ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
-[ ]+28:[ ]+00302573[ ]+frsr[ ]+a0
+[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
[ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
[ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
[ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ba0be86..652b4bb 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2019-07-30 Mel Chen <mel.chen@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
+ fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
+
+ * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
+ fscsr.
+
2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 113d1a5..b7e8d79 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -496,22 +496,22 @@ const struct riscv_opcode riscv_opcodes[] =
{"remuw", 64, {"M", 0}, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
/* Single-precision floating-point instruction subset */
-{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
-{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
-{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
-{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
-{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
-{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
-{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
-{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
-{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
-{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 },
-{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 },
-{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
-{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
-{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
-{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 },
-{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 },
+{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
+{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
+{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
+{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
+{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS },
+{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
+{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
+{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, INSN_ALIAS },
+{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
+{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, INSN_ALIAS },
+{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
+{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
+{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, INSN_ALIAS },
{"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
generated by cgit v1.1 at 2024-08-09 14:13:54 +0000