diff options
| -rw-r--r-- | binutils/ChangeLog | 5 | ||||
| -rw-r--r-- | binutils/dwarf.c | 2 | ||||
| -rw-r--r-- | gas/ChangeLog | 28 | ||||
| -rw-r--r-- | gas/config/tc-riscv.c | 99 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/csr-dw-regnums.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 66 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/priv-reg.d | 2 | ||||
| -rw-r--r-- | gdb/ChangeLog | 8 | ||||
| -rw-r--r-- | gdb/features/riscv/64bit-csr.xml | 65 | ||||
| -rwxr-xr-x | gdb/features/riscv/rebuild-csr-xml.sh | 10 | ||||
| -rw-r--r-- | gdb/riscv-tdep.c | 6 | ||||
| -rw-r--r-- | gdb/riscv-tdep.h | 2 | ||||
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 488 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/riscv-dis.c | 2 |
19 files changed, 480 insertions, 325 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index bb39cea..5b2f876 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2020-02-20 Nelson Chu <nelson.chu@sifive.com> + + * dwarf.c (regname_internal_riscv): Updated since the DECLARE_CSR + is changed. + 2020-02-19 Jordan Rupprecht <rupprecht@google.com> * objdump.c (show_line): call bfd_demangle when using do_demangle. diff --git a/binutils/dwarf.c b/binutils/dwarf.c index 6ecfab5..2403ac7 100644 --- a/binutils/dwarf.c +++ b/binutils/dwarf.c @@ -7381,7 +7381,7 @@ regname_internal_riscv (unsigned int regno) document. */ switch (regno) { -#define DECLARE_CSR(NAME,VALUE) case VALUE + 4096: name = #NAME; break; +#define DECLARE_CSR(NAME,VALUE,CLASS) case VALUE + 4096: name = #NAME; break; #include "opcode/riscv-opc.h" #undef DECLARE_CSR diff --git a/gas/ChangeLog b/gas/ChangeLog index 01cce9f..904d45a 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,31 @@ +2020-02-20 Nelson Chu <nelson.chu@sifive.com> + + * config/tc-riscv.c (csr_extra_hash): New. + (enum riscv_csr_class): New enum. Used to decide + whether or not this CSR is legal in the current ISA string. + (struct riscv_csr_extra): New structure to hold all extra information + of CSR. + (riscv_init_csr_hashes): New. According to the DECLARE_CSR and + DECLARE_CSR_ALIAS, insert CSR extra information into csr_extra_hash. + Call hash_reg_name to insert CSR address into reg_names_hash. + (reg_csr_lookup_internal, riscv_csr_class_check): New functions. + Decide whether the CSR is valid according to the csr_extra_hash. + (reg_lookup_internal): Call reg_csr_lookup_internal for CSRs. + (init_opcode_hash): Update 'if (hash_error != NULL)' as hash_error is + not a boolean. This is same as riscv_init_csr_hash, so keep the + consistent usage. + (md_begin): Call riscv_init_csr_hashes for each DECLARE_CSR. + * testsuite/gas/riscv/csr-dw-regnums.d: Add -march=rv32if option. + * testsuite/gas/riscv/priv-reg.d: Add f-ext by -march option. + * testsuite/gas/riscv/priv-reg-fail-fext.d: New testcase. The source + file is `priv-reg.s`, and the ISA is rv32i without f-ext, so the + f-ext CSR are not allowed. + * testsuite/gas/riscv/priv-reg-fail-fext.l: Likewise. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.d: New testcase. The + source file is `priv-reg.s`, and the ISA is rv64if, so the + rv32-only CSR are not allowed. + * testsuite/gas/riscv/priv-reg-fail-rv32-only.l: Likewise. + 2020-02-21 Alan Modra <amodra@gmail.com> * config/tc-pdp11.c (md_apply_fix): Handle BFD_RELOC_32. diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 21fff8f..2f95d41 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -455,6 +455,7 @@ enum reg_class }; static struct hash_control *reg_names_hash = NULL; +static struct hash_control *csr_extra_hash = NULL; #define ENCODE_REG_HASH(cls, n) \ ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) @@ -480,6 +481,86 @@ hash_reg_names (enum reg_class class, const char * const names[], unsigned n) hash_reg_name (class, names[i], i); } +/* All RISC-V CSRs belong to one of these classes. */ + +enum riscv_csr_class +{ + CSR_CLASS_NONE, + + CSR_CLASS_I, + CSR_CLASS_I_32, /* rv32 only */ + CSR_CLASS_F, /* f-ext only */ +}; + +/* This structure holds all restricted conditions for a CSR. */ + +struct riscv_csr_extra +{ + /* Class to which this CSR belongs. Used to decide whether or + not this CSR is legal in the current -march context. */ + enum riscv_csr_class csr_class; +}; + +/* Init two hashes, csr_extra_hash and reg_names_hash, for CSR. */ + +static void +riscv_init_csr_hashes (const char *name, + unsigned address, + enum riscv_csr_class class) +{ + struct riscv_csr_extra *entry = XNEW (struct riscv_csr_extra); + entry->csr_class = class; + + const char *hash_error = + hash_insert (csr_extra_hash, name, (void *) entry); + if (hash_error != NULL) + { + fprintf (stderr, _("internal error: can't hash `%s': %s\n"), + name, hash_error); + /* Probably a memory allocation problem? Give up now. */ + as_fatal (_("Broken assembler. No assembly attempted.")); + } + + hash_reg_name (RCLASS_CSR, name, address); +} + +/* Check wether the CSR is valid according to the ISA. */ + +static bfd_boolean +riscv_csr_class_check (enum riscv_csr_class csr_class) +{ + switch (csr_class) + { + case CSR_CLASS_I: return riscv_subset_supports ("i"); + case CSR_CLASS_F: return riscv_subset_supports ("f"); + case CSR_CLASS_I_32: + return (xlen == 32 && riscv_subset_supports ("i")); + + default: + return FALSE; + } +} + +/* If the CSR is defined, then we call `riscv_csr_class_check` to do the + further checking. Return FALSE if the CSR is not defined. Otherwise, + return TRUE. */ + +static bfd_boolean +reg_csr_lookup_internal (const char *s) +{ + struct riscv_csr_extra *r = + (struct riscv_csr_extra *) hash_find (csr_extra_hash, s); + + if (r == NULL) + return FALSE; + + /* We just report the warning when the CSR is invalid. */ + if (!riscv_csr_class_check (r->csr_class)) + as_warn (_("Invalid CSR `%s' for the current ISA"), s); + + return TRUE; +} + static unsigned int reg_lookup_internal (const char *s, enum reg_class class) { @@ -491,6 +572,9 @@ reg_lookup_internal (const char *s, enum reg_class class) if (riscv_opts.rve && class == RCLASS_GPR && DECODE_REG_NUM (r) > 15) return -1; + if (class == RCLASS_CSR && !reg_csr_lookup_internal (s)) + return -1; + return DECODE_REG_NUM (r); } @@ -721,7 +805,7 @@ init_opcode_hash (const struct riscv_opcode *opcodes, const char *hash_error = hash_insert (hash, name, (void *) &opcodes[i]); - if (hash_error) + if (hash_error != NULL) { fprintf (stderr, _("internal error: can't hash `%s': %s\n"), opcodes[i].name, hash_error); @@ -769,18 +853,19 @@ md_begin (void) hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); - /* Add "fp" as an alias for "s0". */ hash_reg_name (RCLASS_GPR, "fp", 8); - opcode_names_hash = hash_new (); - init_opcode_names_hash (); - -#define DECLARE_CSR(name, num) hash_reg_name (RCLASS_CSR, #name, num); -#define DECLARE_CSR_ALIAS(name, num) DECLARE_CSR(name, num); + /* Create and insert CSR hash tables. */ + csr_extra_hash = hash_new (); +#define DECLARE_CSR(name, num, class) riscv_init_csr_hashes (#name, num, class); +#define DECLARE_CSR_ALIAS(name, num, class) DECLARE_CSR(name, num, class); #include "opcode/riscv-opc.h" #undef DECLARE_CSR + opcode_names_hash = hash_new (); + init_opcode_names_hash (); + /* Set the default alignment for the text section. */ record_alignment (text_section, riscv_opts.rvc ? 1 : 2); } diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d index 597747c..a7b415e 100644 --- a/gas/testsuite/gas/riscv/csr-dw-regnums.d +++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d @@ -1,4 +1,4 @@ -#as: +#as: -march=rv32if #objdump: --dwarf=frames diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.d b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d new file mode 100644 index 0000000..78ab758 --- /dev/null +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.d @@ -0,0 +1,3 @@ +#as: -march=rv32i +#source: priv-reg.s +#warning_output: priv-reg-fail-fext.l diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-fext.l b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l new file mode 100644 index 0000000..76818c8 --- /dev/null +++ b/gas/testsuite/gas/riscv/priv-reg-fail-fext.l @@ -0,0 +1,4 @@ +.*Assembler messages: +.*Warning: Invalid CSR `fflags' for the current ISA +.*Warning: Invalid CSR `frm' for the current ISA +.*Warning: Invalid CSR `fcsr' for the current ISA diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d new file mode 100644 index 0000000..5dc840a --- /dev/null +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d @@ -0,0 +1,3 @@ +#as: -march=rv64if +#source: priv-reg.s +#warning_output: priv-reg-fail-rv32-only.l diff --git a/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l new file mode 100644 index 0000000..9123672 --- /dev/null +++ b/gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l @@ -0,0 +1,66 @@ +.*Assembler messages: +.*Warning: Invalid CSR `cycleh' for the current ISA +.*Warning: Invalid CSR `timeh' for the current ISA +.*Warning: Invalid CSR `instreth' for the current ISA +.*Warning: Invalid CSR `hpmcounter3h' for the current ISA +.*Warning: Invalid CSR `hpmcounter4h' for the current ISA +.*Warning: Invalid CSR `hpmcounter5h' for the current ISA +.*Warning: Invalid CSR `hpmcounter6h' for the current ISA +.*Warning: Invalid CSR `hpmcounter7h' for the current ISA +.*Warning: Invalid CSR `hpmcounter8h' for the current ISA +.*Warning: Invalid CSR `hpmcounter9h' for the current ISA +.*Warning: Invalid CSR `hpmcounter10h' for the current ISA +.*Warning: Invalid CSR `hpmcounter11h' for the current ISA +.*Warning: Invalid CSR `hpmcounter12h' for the current ISA +.*Warning: Invalid CSR `hpmcounter13h' for the current ISA +.*Warning: Invalid CSR `hpmcounter14h' for the current ISA +.*Warning: Invalid CSR `hpmcounter15h' for the current ISA +.*Warning: Invalid CSR `hpmcounter16h' for the current ISA +.*Warning: Invalid CSR `hpmcounter17h' for the current ISA +.*Warning: Invalid CSR `hpmcounter18h' for the current ISA +.*Warning: Invalid CSR `hpmcounter19h' for the current ISA +.*Warning: Invalid CSR `hpmcounter20h' for the current ISA +.*Warning: Invalid CSR `hpmcounter21h' for the current ISA +.*Warning: Invalid CSR `hpmcounter22h' for the current ISA +.*Warning: Invalid CSR `hpmcounter23h' for the current ISA +.*Warning: Invalid CSR `hpmcounter24h' for the current ISA +.*Warning: Invalid CSR `hpmcounter25h' for the current ISA +.*Warning: Invalid CSR `hpmcounter26h' for the current ISA +.*Warning: Invalid CSR `hpmcounter27h' for the current ISA +.*Warning: Invalid CSR `hpmcounter28h' for the current ISA +.*Warning: Invalid CSR `hpmcounter29h' for the current ISA +.*Warning: Invalid CSR `hpmcounter30h' for the current ISA +.*Warning: Invalid CSR `hpmcounter31h' for the current ISA +.*Warning: Invalid CSR `mcycleh' for the current ISA +.*Warning: Invalid CSR `minstreth' for the current ISA +.*Warning: Invalid CSR `mhpmcounter3h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter4h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter5h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter6h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter7h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter8h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter9h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter10h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter11h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter12h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter13h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter14h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter15h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter16h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter17h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter18h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter19h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter20h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter21h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter22h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter23h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter24h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter25h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter26h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter27h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter28h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter29h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter30h' for the current ISA +.*Warning: Invalid CSR `mhpmcounter31h' for the current ISA +.*Warning: Invalid CSR `pmpcfg1' for the current ISA +.*Warning: Invalid CSR `pmpcfg3' for the current ISA diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d index d8ec868..8b7a7bf 100644 --- a/gas/testsuite/gas/riscv/priv-reg.d +++ b/gas/testsuite/gas/riscv/priv-reg.d @@ -1,4 +1,4 @@ -#as: -march=rv32i +#as: -march=rv32if #objdump: -dr .*:[ ]+file format .* diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 40bee39..f8a491b 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,11 @@ +2020-02-20 Nelson Chu <nelson.chu@sifive.com> + + * riscv-tdep.c: Updated since the DECLARE_CSR is changed. + * riscv-tdep.h: Likewise. + * features/riscv/rebuild-csr-xml.sh: Generate the 64bit-csr.xml without + rv32-only CSR. + * features/riscv/64bit-csr.xml: Regenerated. + 2020-02-20 Sergio Durigan Junior <sergiodj@redhat.com> Tom Tromey <tom@tromey.com> diff --git a/gdb/features/riscv/64bit-csr.xml b/gdb/features/riscv/64bit-csr.xml index cf15a7f..8ec0ffe 100644 --- a/gdb/features/riscv/64bit-csr.xml +++ b/gdb/features/riscv/64bit-csr.xml @@ -50,38 +50,6 @@ <reg name="hpmcounter29" bitsize="64"/> <reg name="hpmcounter30" bitsize="64"/> <reg name="hpmcounter31" bitsize="64"/> - <reg name="cycleh" bitsize="64"/> - <reg name="timeh" bitsize="64"/> - <reg name="instreth" bitsize="64"/> - <reg name="hpmcounter3h" bitsize="64"/> - <reg name="hpmcounter4h" bitsize="64"/> - <reg name="hpmcounter5h" bitsize="64"/> - <reg name="hpmcounter6h" bitsize="64"/> - <reg name="hpmcounter7h" bitsize="64"/> - <reg name="hpmcounter8h" bitsize="64"/> - <reg name="hpmcounter9h" bitsize="64"/> - <reg name="hpmcounter10h" bitsize="64"/> - <reg name="hpmcounter11h" bitsize="64"/> - <reg name="hpmcounter12h" bitsize="64"/> - <reg name="hpmcounter13h" bitsize="64"/> - <reg name="hpmcounter14h" bitsize="64"/> - <reg name="hpmcounter15h" bitsize="64"/> - <reg name="hpmcounter16h" bitsize="64"/> - <reg name="hpmcounter17h" bitsize="64"/> - <reg name="hpmcounter18h" bitsize="64"/> - <reg name="hpmcounter19h" bitsize="64"/> - <reg name="hpmcounter20h" bitsize="64"/> - <reg name="hpmcounter21h" bitsize="64"/> - <reg name="hpmcounter22h" bitsize="64"/> - <reg name="hpmcounter23h" bitsize="64"/> - <reg name="hpmcounter24h" bitsize="64"/> - <reg name="hpmcounter25h" bitsize="64"/> - <reg name="hpmcounter26h" bitsize="64"/> - <reg name="hpmcounter27h" bitsize="64"/> - <reg name="hpmcounter28h" bitsize="64"/> - <reg name="hpmcounter29h" bitsize="64"/> - <reg name="hpmcounter30h" bitsize="64"/> - <reg name="hpmcounter31h" bitsize="64"/> <reg name="sstatus" bitsize="64"/> <reg name="sedeleg" bitsize="64"/> <reg name="sideleg" bitsize="64"/> @@ -111,9 +79,7 @@ <reg name="mtval" bitsize="64"/> <reg name="mip" bitsize="64"/> <reg name="pmpcfg0" bitsize="64"/> - <reg name="pmpcfg1" bitsize="64"/> <reg name="pmpcfg2" bitsize="64"/> - <reg name="pmpcfg3" bitsize="64"/> <reg name="pmpaddr0" bitsize="64"/> <reg name="pmpaddr1" bitsize="64"/> <reg name="pmpaddr2" bitsize="64"/> @@ -161,37 +127,6 @@ <reg name="mhpmcounter29" bitsize="64"/> <reg name="mhpmcounter30" bitsize="64"/> <reg name="mhpmcounter31" bitsize="64"/> - <reg name="mcycleh" bitsize="64"/> - <reg name="minstreth" bitsize="64"/> - <reg name="mhpmcounter3h" bitsize="64"/> - <reg name="mhpmcounter4h" bitsize="64"/> - <reg name="mhpmcounter5h" bitsize="64"/> - <reg name="mhpmcounter6h" bitsize="64"/> - <reg name="mhpmcounter7h" bitsize="64"/> - <reg name="mhpmcounter8h" bitsize="64"/> - <reg name="mhpmcounter9h" bitsize="64"/> - <reg name="mhpmcounter10h" bitsize="64"/> - <reg name="mhpmcounter11h" bitsize="64"/> - <reg name="mhpmcounter12h" bitsize="64"/> - <reg name="mhpmcounter13h" bitsize="64"/> - <reg name="mhpmcounter14h" bitsize="64"/> - <reg name="mhpmcounter15h" bitsize="64"/> - <reg name="mhpmcounter16h" bitsize="64"/> - <reg name="mhpmcounter17h" bitsize="64"/> - <reg name="mhpmcounter18h" bitsize="64"/> - <reg name="mhpmcounter19h" bitsize="64"/> - <reg name="mhpmcounter20h" bitsize="64"/> - <reg name="mhpmcounter21h" bitsize="64"/> - <reg name="mhpmcounter22h" bitsize="64"/> - <reg name="mhpmcounter23h" bitsize="64"/> - <reg name="mhpmcounter24h" bitsize="64"/> - <reg name="mhpmcounter25h" bitsize="64"/> - <reg name="mhpmcounter26h" bitsize="64"/> - <reg name="mhpmcounter27h" bitsize="64"/> - <reg name="mhpmcounter28h" bitsize="64"/> - <reg name="mhpmcounter29h" bitsize="64"/> - <reg name="mhpmcounter30h" bitsize="64"/> - <reg name="mhpmcounter31h" bitsize="64"/> <reg name="mhpmevent3" bitsize="64"/> <reg name="mhpmevent4" bitsize="64"/> <reg name="mhpmevent5" bitsize="64"/> diff --git a/gdb/features/riscv/rebuild-csr-xml.sh b/gdb/features/riscv/rebuild-csr-xml.sh index e21aaba..1adb180 100755 --- a/gdb/features/riscv/rebuild-csr-xml.sh +++ b/gdb/features/riscv/rebuild-csr-xml.sh @@ -19,10 +19,18 @@ function gen_csr_xml () <feature name="org.gnu.gdb.riscv.csr"> EOF +if [ "$bitsize" = "64" ]; then grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \ - | sed -e "s!DECLARE_CSR(\(.*\), .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!" + | sed /CSR_CLASS_.*_32/d \ + | sed -e "s!DECLARE_CSR(\(.*\), .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!" echo "</feature>" +else + grep "^DECLARE_CSR(" ${RISCV_OPC_FILE} \ + | sed -e "s!DECLARE_CSR(\(.*\), .*, .*! <reg name=\"\1\" bitsize=\"$bitsize\"/>!" + + echo "</feature>" +fi } gen_csr_xml 32 > ${RISCV_FEATURE_DIR}/32bit-csr.xml diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 0515729..97741a3 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -240,7 +240,7 @@ static struct riscv_register_feature riscv_csr_feature = { "org.gnu.gdb.riscv.csr", { -#define DECLARE_CSR(NAME,VALUE) \ +#define DECLARE_CSR(NAME,VALUE,CLASS) \ { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false }, #include "opcode/riscv-opc.h" #undef DECLARE_CSR @@ -534,7 +534,7 @@ riscv_register_name (struct gdbarch *gdbarch, int regnum) if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM) { -#define DECLARE_CSR(NAME,VALUE) \ +#define DECLARE_CSR(NAME,VALUE,CLASS) \ case RISCV_ ## VALUE ## _REGNUM: return # NAME; switch (regnum) @@ -870,7 +870,7 @@ riscv_is_regnum_a_named_csr (int regnum) switch (regnum) { -#define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM: +#define DECLARE_CSR(name, num, class) case RISCV_ ## num ## _REGNUM: #include "opcode/riscv-opc.h" #undef DECLARE_CSR return true; diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index aaed33c..90bae08 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -44,7 +44,7 @@ enum RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */ RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */ -#define DECLARE_CSR(name, num) \ +#define DECLARE_CSR(name, num, class) \ RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num, #include "opcode/riscv-opc.h" #undef DECLARE_CSR diff --git a/include/ChangeLog b/include/ChangeLog index 9c0b5d2..9907c1d 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2020-02-20 Nelson Chu <nelson.chu@sifive.com> + + * opcode/riscv-opc.h: Extend DECLARE_CSR and DECLARE_CSR_ALIAS to + record riscv_csr_class. + 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> Matthew Malcomson <matthew.malcomson@arm.com> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index f09200c..18d0b15 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -1116,257 +1116,257 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2) #endif #ifdef DECLARE_CSR -DECLARE_CSR(ustatus, CSR_USTATUS) -DECLARE_CSR(uie, CSR_UIE) -DECLARE_CSR(utvec, CSR_UTVEC) -DECLARE_CSR(uscratch, CSR_USCRATCH) -DECLARE_CSR(uepc, CSR_UEPC) -DECLARE_CSR(ucause, CSR_UCAUSE) -DECLARE_CSR(utval, CSR_UTVAL) -DECLARE_CSR(uip, CSR_UIP) -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sedeleg, CSR_SEDELEG) -DECLARE_CSR(sideleg, CSR_SIDELEG) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(scounteren, CSR_SCOUNTEREN) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(stval, CSR_STVAL) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(satp, CSR_SATP) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mcounteren, CSR_MCOUNTEREN) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mtval, CSR_MTVAL) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) -DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) -DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) -DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) -DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) -DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) -DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) -DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) -DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) -DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) -DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) -DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) -DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) -DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) -DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) -DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) -DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) -DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) -DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) -DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) +DECLARE_CSR(ustatus, CSR_USTATUS, CSR_CLASS_I) +DECLARE_CSR(uie, CSR_UIE, CSR_CLASS_I) +DECLARE_CSR(utvec, CSR_UTVEC, CSR_CLASS_I) +DECLARE_CSR(uscratch, CSR_USCRATCH, CSR_CLASS_I) +DECLARE_CSR(uepc, CSR_UEPC, CSR_CLASS_I) +DECLARE_CSR(ucause, CSR_UCAUSE, CSR_CLASS_I) +DECLARE_CSR(utval, CSR_UTVAL, CSR_CLASS_I) +DECLARE_CSR(uip, CSR_UIP, CSR_CLASS_I) +DECLARE_CSR(fflags, CSR_FFLAGS, CSR_CLASS_F) +DECLARE_CSR(frm, CSR_FRM, CSR_CLASS_F) +DECLARE_CSR(fcsr, CSR_FCSR, CSR_CLASS_F) +DECLARE_CSR(cycle, CSR_CYCLE, CSR_CLASS_I) +DECLARE_CSR(time, CSR_TIME, CSR_CLASS_I) +DECLARE_CSR(instret, CSR_INSTRET, CSR_CLASS_I) +DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3, CSR_CLASS_I) +DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4, CSR_CLASS_I) +DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5, CSR_CLASS_I) +DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6, CSR_CLASS_I) +DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7, CSR_CLASS_I) +DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8, CSR_CLASS_I) +DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9, CSR_CLASS_I) +DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10, CSR_CLASS_I) +DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11, CSR_CLASS_I) +DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12, CSR_CLASS_I) +DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13, CSR_CLASS_I) +DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14, CSR_CLASS_I) +DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15, CSR_CLASS_I) +DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16, CSR_CLASS_I) +DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17, CSR_CLASS_I) +DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18, CSR_CLASS_I) +DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19, CSR_CLASS_I) +DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20, CSR_CLASS_I) +DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21, CSR_CLASS_I) +DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22, CSR_CLASS_I) +DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23, CSR_CLASS_I) +DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24, CSR_CLASS_I) +DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25, CSR_CLASS_I) +DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26, CSR_CLASS_I) +DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27, CSR_CLASS_I) +DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28, CSR_CLASS_I) +DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29, CSR_CLASS_I) +DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30, CSR_CLASS_I) +DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31, CSR_CLASS_I) +DECLARE_CSR(cycleh, CSR_CYCLEH, CSR_CLASS_I_32) +DECLARE_CSR(timeh, CSR_TIMEH, CSR_CLASS_I_32) +DECLARE_CSR(instreth, CSR_INSTRETH, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H, CSR_CLASS_I_32) +DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H, CSR_CLASS_I_32) +DECLARE_CSR(sstatus, CSR_SSTATUS, CSR_CLASS_I) +DECLARE_CSR(sedeleg, CSR_SEDELEG, CSR_CLASS_I) +DECLARE_CSR(sideleg, CSR_SIDELEG, CSR_CLASS_I) +DECLARE_CSR(sie, CSR_SIE, CSR_CLASS_I) +DECLARE_CSR(stvec, CSR_STVEC, CSR_CLASS_I) +DECLARE_CSR(scounteren, CSR_SCOUNTEREN, CSR_CLASS_I) +DECLARE_CSR(sscratch, CSR_SSCRATCH, CSR_CLASS_I) +DECLARE_CSR(sepc, CSR_SEPC, CSR_CLASS_I) +DECLARE_CSR(scause, CSR_SCAUSE, CSR_CLASS_I) +DECLARE_CSR(stval, CSR_STVAL, CSR_CLASS_I) +DECLARE_CSR(sip, CSR_SIP, CSR_CLASS_I) +DECLARE_CSR(satp, CSR_SATP, CSR_CLASS_I) +DECLARE_CSR(mvendorid, CSR_MVENDORID, CSR_CLASS_I) +DECLARE_CSR(marchid, CSR_MARCHID, CSR_CLASS_I) +DECLARE_CSR(mimpid, CSR_MIMPID, CSR_CLASS_I) +DECLARE_CSR(mhartid, CSR_MHARTID, CSR_CLASS_I) +DECLARE_CSR(mstatus, CSR_MSTATUS, CSR_CLASS_I) +DECLARE_CSR(misa, CSR_MISA, CSR_CLASS_I) +DECLARE_CSR(medeleg, CSR_MEDELEG, CSR_CLASS_I) +DECLARE_CSR(mideleg, CSR_MIDELEG, CSR_CLASS_I) +DECLARE_CSR(mie, CSR_MIE, CSR_CLASS_I) +DECLARE_CSR(mtvec, CSR_MTVEC, CSR_CLASS_I) +DECLARE_CSR(mcounteren, CSR_MCOUNTEREN, CSR_CLASS_I) +DECLARE_CSR(mscratch, CSR_MSCRATCH, CSR_CLASS_I) +DECLARE_CSR(mepc, CSR_MEPC, CSR_CLASS_I) +DECLARE_CSR(mcause, CSR_MCAUSE, CSR_CLASS_I) +DECLARE_CSR(mtval, CSR_MTVAL, CSR_CLASS_I) +DECLARE_CSR(mip, CSR_MIP, CSR_CLASS_I) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0, CSR_CLASS_I) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1, CSR_CLASS_I_32) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2, CSR_CLASS_I) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3, CSR_CLASS_I_32) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0, CSR_CLASS_I) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1, CSR_CLASS_I) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2, CSR_CLASS_I) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3, CSR_CLASS_I) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4, CSR_CLASS_I) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5, CSR_CLASS_I) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6, CSR_CLASS_I) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7, CSR_CLASS_I) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8, CSR_CLASS_I) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9, CSR_CLASS_I) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10, CSR_CLASS_I) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11, CSR_CLASS_I) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12, CSR_CLASS_I) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13, CSR_CLASS_I) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14, CSR_CLASS_I) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15, CSR_CLASS_I) +DECLARE_CSR(mcycle, CSR_MCYCLE, CSR_CLASS_I) +DECLARE_CSR(minstret, CSR_MINSTRET, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30, CSR_CLASS_I) +DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31, CSR_CLASS_I) +DECLARE_CSR(mcycleh, CSR_MCYCLEH, CSR_CLASS_I_32) +DECLARE_CSR(minstreth, CSR_MINSTRETH, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H, CSR_CLASS_I_32) +DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3, CSR_CLASS_I) +DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4, CSR_CLASS_I) +DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5, CSR_CLASS_I) +DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6, CSR_CLASS_I) +DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7, CSR_CLASS_I) +DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8, CSR_CLASS_I) +DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9, CSR_CLASS_I) +DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10, CSR_CLASS_I) +DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11, CSR_CLASS_I) +DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12, CSR_CLASS_I) +DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13, CSR_CLASS_I) +DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14, CSR_CLASS_I) +DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15, CSR_CLASS_I) +DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16, CSR_CLASS_I) +DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17, CSR_CLASS_I) +DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18, CSR_CLASS_I) +DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19, CSR_CLASS_I) +DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20, CSR_CLASS_I) +DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21, CSR_CLASS_I) +DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22, CSR_CLASS_I) +DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23, CSR_CLASS_I) +DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24, CSR_CLASS_I) +DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25, CSR_CLASS_I) +DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26, CSR_CLASS_I) +DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27, CSR_CLASS_I) +DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28, CSR_CLASS_I) +DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29, CSR_CLASS_I) +DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30, CSR_CLASS_I) +DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31, CSR_CLASS_I) +DECLARE_CSR(tselect, CSR_TSELECT, CSR_CLASS_I) +DECLARE_CSR(tdata1, CSR_TDATA1, CSR_CLASS_I) +DECLARE_CSR(tdata2, CSR_TDATA2, CSR_CLASS_I) +DECLARE_CSR(tdata3, CSR_TDATA3, CSR_CLASS_I) +DECLARE_CSR(dcsr, CSR_DCSR, CSR_CLASS_I) +DECLARE_CSR(dpc, CSR_DPC, CSR_CLASS_I) +DECLARE_CSR(dscratch, CSR_DSCRATCH, CSR_CLASS_I) /* These registers are present in priv spec 1.9.1, dropped in 1.10. */ -DECLARE_CSR(hstatus, CSR_HSTATUS) -DECLARE_CSR(hedeleg, CSR_HEDELEG) -DECLARE_CSR(hideleg, CSR_HIDELEG) -DECLARE_CSR(hie, CSR_HIE) -DECLARE_CSR(htvec, CSR_HTVEC) -DECLARE_CSR(hscratch, CSR_HSCRATCH) -DECLARE_CSR(hepc, CSR_HEPC) -DECLARE_CSR(hcause, CSR_HCAUSE) -DECLARE_CSR(hbadaddr, CSR_HBADADDR) -DECLARE_CSR(hip, CSR_HIP) -DECLARE_CSR(mbase, CSR_MBASE) -DECLARE_CSR(mbound, CSR_MBOUND) -DECLARE_CSR(mibase, CSR_MIBASE) -DECLARE_CSR(mibound, CSR_MIBOUND) -DECLARE_CSR(mdbase, CSR_MDBASE) -DECLARE_CSR(mdbound, CSR_MDBOUND) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN) +DECLARE_CSR(hstatus, CSR_HSTATUS, CSR_CLASS_I) +DECLARE_CSR(hedeleg, CSR_HEDELEG, CSR_CLASS_I) +DECLARE_CSR(hideleg, CSR_HIDELEG, CSR_CLASS_I) +DECLARE_CSR(hie, CSR_HIE, CSR_CLASS_I) +DECLARE_CSR(htvec, CSR_HTVEC, CSR_CLASS_I) +DECLARE_CSR(hscratch, CSR_HSCRATCH, CSR_CLASS_I) +DECLARE_CSR(hepc, CSR_HEPC, CSR_CLASS_I) +DECLARE_CSR(hcause, CSR_HCAUSE, CSR_CLASS_I) +DECLARE_CSR(hbadaddr, CSR_HBADADDR, CSR_CLASS_I) +DECLARE_CSR(hip, CSR_HIP, CSR_CLASS_I) +DECLARE_CSR(mbase, CSR_MBASE, CSR_CLASS_I) +DECLARE_CSR(mbound, CSR_MBOUND, CSR_CLASS_I) +DECLARE_CSR(mibase, CSR_MIBASE, CSR_CLASS_I) +DECLARE_CSR(mibound, CSR_MIBOUND, CSR_CLASS_I) +DECLARE_CSR(mdbase, CSR_MDBASE, CSR_CLASS_I) +DECLARE_CSR(mdbound, CSR_MDBOUND, CSR_CLASS_I) +DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN, CSR_CLASS_I) +DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN, CSR_CLASS_I) +DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN, CSR_CLASS_I) #endif #ifdef DECLARE_CSR_ALIAS /* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */ -DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL) +DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL, CSR_CLASS_I) /* Sbadaddr is 0x143 in 1.9.1, but 0x143 is stval in 1.10. */ -DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL) +DECLARE_CSR_ALIAS(sbadaddr, CSR_STVAL, CSR_CLASS_I) /* Sptbr is 0x180 in 1.9.1, but 0x180 is satp in 1.10. */ -DECLARE_CSR_ALIAS(sptbr, CSR_SATP) +DECLARE_CSR_ALIAS(sptbr, CSR_SATP, CSR_CLASS_I) /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */ -DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL) +DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL, CSR_CLASS_I) #endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index e5aa59d..73091b9 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2020-02-20 Nelson Chu <nelson.chu@sifive.com> + + * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is + changed. + 2020-02-19 Nelson Chu <nelson.chu@sifive.com> * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 47f9db0..d7a184c 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -326,7 +326,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) unsigned int csr = EXTRACT_OPERAND (CSR, l); switch (csr) { -#define DECLARE_CSR(name, num) case num: csr_name = #name; break; +#define DECLARE_CSR(name, num, class) case num: csr_name = #name; break; #include "opcode/riscv-opc.h" #undef DECLARE_CSR } |