diff options
162 files changed, 27187 insertions, 5 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 34b0465..367d86c 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,28 @@ +2018-07-30 Andrew Jenner <andrew@codesourcery.com> + + * Makefile.am (ALL_MACHINES, ALL_MACHINES_CFILES): Add C-SKY. + (BFD32_BACKENDS, BFD_BACKENDS_CFILES): Likewise. + * Makefile.in: Regenerated. + * archures.c (enum bfd_architecture): Add bfd_arch_csky and + related bfd_mach defines. + (bfd_csky_arch): Declare. + (bfd_archures_list): Add C-SKY. + * bfd-in.h (elf32_csky_build_stubs): Declare. + (elf32_csky_size_stubs): Declare. + (elf32_csky_next_input_section: Declare. + (elf32_csky_setup_section_lists): Declare. + * bfd-in2.h: Regenerated. + * config.bfd: Add C-SKY. + * configure.ac: Likewise. + * configure: Regenerated. + * cpu-csky.c: New file. + * elf-bfd.h (enum elf_target_id): Add C-SKY. + * elf32-csky.c: New file. + * libbfd.h: Regenerated. + * reloc.c: Add C-SKY relocations. + * targets.c (csky_elf32_be_vec, csky_elf32_le_vec): Declare. + (_bfd_target_vector): Add C-SKY target vector entries. + 2018-07-27 John Darrington <john@darrington.wattle.id.au> * elf32-s12z.c (ELF_TARGET_ID): Don't define. diff --git a/bfd/Makefile.am b/bfd/Makefile.am index 3f3487f..9c299df 100644 --- a/bfd/Makefile.am +++ b/bfd/Makefile.am @@ -100,6 +100,7 @@ ALL_MACHINES = \ cpu-cr16c.lo \ cpu-cris.lo \ cpu-crx.lo \ + cpu-csky.lo \ cpu-d10v.lo \ cpu-d30v.lo \ cpu-dlx.lo \ @@ -185,6 +186,7 @@ ALL_MACHINES_CFILES = \ cpu-cr16c.c \ cpu-cris.c \ cpu-crx.c \ + cpu-csky.c \ cpu-d10v.c \ cpu-d30v.c \ cpu-dlx.c \ @@ -304,6 +306,7 @@ BFD32_BACKENDS = \ elf32-cr16c.lo \ elf32-cris.lo \ elf32-crx.lo \ + elf32-csky.lo \ elf32-d10v.lo \ elf32-d30v.lo \ elf32-dlx.lo \ @@ -441,6 +444,7 @@ BFD32_BACKENDS_CFILES = \ elf32-cr16c.c \ elf32-cris.c \ elf32-crx.c \ + elf32-csky.c \ elf32-d10v.c \ elf32-d30v.c \ elf32-dlx.c \ diff --git a/bfd/Makefile.in b/bfd/Makefile.in index cc27ef0..c1c0292 100644 --- a/bfd/Makefile.in +++ b/bfd/Makefile.in @@ -522,6 +522,7 @@ ALL_MACHINES = \ cpu-cr16c.lo \ cpu-cris.lo \ cpu-crx.lo \ + cpu-csky.lo \ cpu-d10v.lo \ cpu-d30v.lo \ cpu-dlx.lo \ @@ -607,6 +608,7 @@ ALL_MACHINES_CFILES = \ cpu-cr16c.c \ cpu-cris.c \ cpu-crx.c \ + cpu-csky.c \ cpu-d10v.c \ cpu-d30v.c \ cpu-dlx.c \ @@ -727,6 +729,7 @@ BFD32_BACKENDS = \ elf32-cr16c.lo \ elf32-cris.lo \ elf32-crx.lo \ + elf32-csky.lo \ elf32-d10v.lo \ elf32-d30v.lo \ elf32-dlx.lo \ @@ -864,6 +867,7 @@ BFD32_BACKENDS_CFILES = \ elf32-cr16c.c \ elf32-cris.c \ elf32-crx.c \ + elf32-csky.c \ elf32-d10v.c \ elf32-d30v.c \ elf32-dlx.c \ @@ -1323,6 +1327,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cr16c.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-cris.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-crx.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-csky.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d10v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-d30v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cpu-dlx.Plo@am__quote@ @@ -1420,6 +1425,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-cr16c.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-cris.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-crx.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-csky.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d10v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-d30v.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/elf32-dlx.Plo@am__quote@ diff --git a/bfd/archures.c b/bfd/archures.c index 282e983..b0e9230 100644 --- a/bfd/archures.c +++ b/bfd/archures.c @@ -529,6 +529,15 @@ DESCRIPTION . bfd_arch_nfp, {* Netronome Flow Processor *} .#define bfd_mach_nfp3200 0x3200 .#define bfd_mach_nfp6000 0x6000 +. bfd_arch_csky, {* C-SKY. *} +.#define bfd_mach_ck_unknown 0 +.#define bfd_mach_ck510 1 +.#define bfd_mach_ck610 2 +.#define bfd_mach_ck801 3 +.#define bfd_mach_ck802 4 +.#define bfd_mach_ck803 5 +.#define bfd_mach_ck807 6 +.#define bfd_mach_ck810 7 . bfd_arch_last . }; */ @@ -583,6 +592,7 @@ extern const bfd_arch_info_type bfd_cr16_arch; extern const bfd_arch_info_type bfd_cr16c_arch; extern const bfd_arch_info_type bfd_cris_arch; extern const bfd_arch_info_type bfd_crx_arch; +extern const bfd_arch_info_type bfd_csky_arch; extern const bfd_arch_info_type bfd_d10v_arch; extern const bfd_arch_info_type bfd_d30v_arch; extern const bfd_arch_info_type bfd_dlx_arch; @@ -673,6 +683,7 @@ static const bfd_arch_info_type * const bfd_archures_list[] = &bfd_cr16c_arch, &bfd_cris_arch, &bfd_crx_arch, + &bfd_csky_arch, &bfd_d10v_arch, &bfd_d30v_arch, &bfd_dlx_arch, diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h index 1d477c3..f00625d 100644 --- a/bfd/bfd-in.h +++ b/bfd/bfd-in.h @@ -1063,3 +1063,15 @@ extern bfd_boolean v850_elf_set_note /* MIPS ABI flags data access. For the disassembler. */ struct elf_internal_abiflags_v0; extern struct elf_internal_abiflags_v0 *bfd_mips_elf_get_abiflags (bfd *); + +/* C-SKY functions. */ +extern bfd_boolean elf32_csky_build_stubs + (struct bfd_link_info *); +extern bfd_boolean elf32_csky_size_stubs + (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma, + struct bfd_section *(*) (const char*, struct bfd_section*), + void (*) (void)); +extern void elf32_csky_next_input_section + (struct bfd_link_info *, struct bfd_section *); +extern int elf32_csky_setup_section_lists + (bfd *, struct bfd_link_info *); diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h index 414ca54..7105850 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h @@ -1070,6 +1070,18 @@ extern bfd_boolean v850_elf_set_note /* MIPS ABI flags data access. For the disassembler. */ struct elf_internal_abiflags_v0; extern struct elf_internal_abiflags_v0 *bfd_mips_elf_get_abiflags (bfd *); + +/* C-SKY functions. */ +extern bfd_boolean elf32_csky_build_stubs + (struct bfd_link_info *); +extern bfd_boolean elf32_csky_size_stubs + (bfd *, bfd *, struct bfd_link_info *, bfd_signed_vma, + struct bfd_section *(*) (const char*, struct bfd_section*), + void (*) (void)); +extern void elf32_csky_next_input_section + (struct bfd_link_info *, struct bfd_section *); +extern int elf32_csky_setup_section_lists + (bfd *, struct bfd_link_info *); /* Extracted from init.c. */ void bfd_init (void); @@ -2414,6 +2426,15 @@ enum bfd_architecture bfd_arch_nfp, /* Netronome Flow Processor */ #define bfd_mach_nfp3200 0x3200 #define bfd_mach_nfp6000 0x6000 + bfd_arch_csky, /* C-SKY. */ +#define bfd_mach_ck_unknown 0 +#define bfd_mach_ck510 1 +#define bfd_mach_ck610 2 +#define bfd_mach_ck801 3 +#define bfd_mach_ck802 4 +#define bfd_mach_ck803 5 +#define bfd_mach_ck807 6 +#define bfd_mach_ck810 7 bfd_arch_last }; @@ -6580,6 +6601,73 @@ assembler and not (currently) written to any object files. */ BFD_RELOC_WASM32_CODE_POINTER, BFD_RELOC_WASM32_INDEX, BFD_RELOC_WASM32_PLT_SIG, + +/* C-SKY relocations. */ + BFD_RELOC_CKCORE_NONE, + BFD_RELOC_CKCORE_ADDR32, + BFD_RELOC_CKCORE_PCREL_IMM8BY4, + BFD_RELOC_CKCORE_PCREL_IMM11BY2, + BFD_RELOC_CKCORE_PCREL_IMM4BY2, + BFD_RELOC_CKCORE_PCREL32, + BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2, + BFD_RELOC_CKCORE_GNU_VTINHERIT, + BFD_RELOC_CKCORE_GNU_VTENTRY, + BFD_RELOC_CKCORE_RELATIVE, + BFD_RELOC_CKCORE_COPY, + BFD_RELOC_CKCORE_GLOB_DAT, + BFD_RELOC_CKCORE_JUMP_SLOT, + BFD_RELOC_CKCORE_GOTOFF, + BFD_RELOC_CKCORE_GOTPC, + BFD_RELOC_CKCORE_GOT32, + BFD_RELOC_CKCORE_PLT32, + BFD_RELOC_CKCORE_ADDRGOT, + BFD_RELOC_CKCORE_ADDRPLT, + BFD_RELOC_CKCORE_PCREL_IMM26BY2, + BFD_RELOC_CKCORE_PCREL_IMM16BY2, + BFD_RELOC_CKCORE_PCREL_IMM16BY4, + BFD_RELOC_CKCORE_PCREL_IMM10BY2, + BFD_RELOC_CKCORE_PCREL_IMM10BY4, + BFD_RELOC_CKCORE_ADDR_HI16, + BFD_RELOC_CKCORE_ADDR_LO16, + BFD_RELOC_CKCORE_GOTPC_HI16, + BFD_RELOC_CKCORE_GOTPC_LO16, + BFD_RELOC_CKCORE_GOTOFF_HI16, + BFD_RELOC_CKCORE_GOTOFF_LO16, + BFD_RELOC_CKCORE_GOT12, + BFD_RELOC_CKCORE_GOT_HI16, + BFD_RELOC_CKCORE_GOT_LO16, + BFD_RELOC_CKCORE_PLT12, + BFD_RELOC_CKCORE_PLT_HI16, + BFD_RELOC_CKCORE_PLT_LO16, + BFD_RELOC_CKCORE_ADDRGOT_HI16, + BFD_RELOC_CKCORE_ADDRGOT_LO16, + BFD_RELOC_CKCORE_ADDRPLT_HI16, + BFD_RELOC_CKCORE_ADDRPLT_LO16, + BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2, + BFD_RELOC_CKCORE_TOFFSET_LO16, + BFD_RELOC_CKCORE_DOFFSET_LO16, + BFD_RELOC_CKCORE_PCREL_IMM18BY2, + BFD_RELOC_CKCORE_DOFFSET_IMM18, + BFD_RELOC_CKCORE_DOFFSET_IMM18BY2, + BFD_RELOC_CKCORE_DOFFSET_IMM18BY4, + BFD_RELOC_CKCORE_GOTOFF_IMM18, + BFD_RELOC_CKCORE_GOT_IMM18BY4, + BFD_RELOC_CKCORE_PLT_IMM18BY4, + BFD_RELOC_CKCORE_PCREL_IMM7BY4, + BFD_RELOC_CKCORE_TLS_LE32, + BFD_RELOC_CKCORE_TLS_IE32, + BFD_RELOC_CKCORE_TLS_GD32, + BFD_RELOC_CKCORE_TLS_LDM32, + BFD_RELOC_CKCORE_TLS_LDO32, + BFD_RELOC_CKCORE_TLS_DTPMOD32, + BFD_RELOC_CKCORE_TLS_DTPOFF32, + BFD_RELOC_CKCORE_TLS_TPOFF32, + BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4, + BFD_RELOC_CKCORE_NOJSRI, + BFD_RELOC_CKCORE_CALLGRAPH, + BFD_RELOC_CKCORE_IRELATIVE, + BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4, + BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4, BFD_RELOC_UNUSED }; typedef enum bfd_reloc_code_real bfd_reloc_code_real_type; diff --git a/bfd/config.bfd b/bfd/config.bfd index 6391f35..0e397f5 100644 --- a/bfd/config.bfd +++ b/bfd/config.bfd @@ -170,6 +170,7 @@ c54x*) targ_archs=bfd_tic54x_arch ;; cr16*) targ_archs=bfd_cr16_arch ;; crisv32) targ_archs=bfd_cris_arch ;; crx*) targ_archs=bfd_crx_arch ;; +csky*) targ_archs=bfd_csky_arch ;; dlx*) targ_archs=bfd_dlx_arch ;; fido*) targ_archs=bfd_m68k_arch ;; hppa*) targ_archs=bfd_hppa_arch ;; @@ -461,6 +462,11 @@ case "${targ}" in targ_underscore=yes ;; + csky-*-elf* | csky-*-linux* ) + targ_defvec=csky_elf32_be_vec + targ_selvecs="csky_elf32_be_vec csky_elf32_le_vec" + ;; + d10v-*-*) targ_defvec=d10v_elf32_vec ;; diff --git a/bfd/configure b/bfd/configure index 0cfe568..2ba044d 100755 --- a/bfd/configure +++ b/bfd/configure @@ -14697,6 +14697,8 @@ do cris_elf32_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; cris_elf32_us_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; crx_elf32_vec) tb="$tb elf32-crx.lo elf32.lo $elf" ;; + csky_elf32_be_vec) tb="$tb elf32-csky.lo elf32.lo $elf" ;; + csky_elf32_le_vec) tb="$tb elf32-csky.lo elf32.lo $elf" ;; d10v_elf32_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;; d30v_elf32_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; dlx_elf32_be_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; diff --git a/bfd/configure.ac b/bfd/configure.ac index c6193cd..fc4331c 100644 --- a/bfd/configure.ac +++ b/bfd/configure.ac @@ -465,6 +465,8 @@ do cris_elf32_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; cris_elf32_us_vec) tb="$tb elf32-cris.lo elf32.lo $elf" ;; crx_elf32_vec) tb="$tb elf32-crx.lo elf32.lo $elf" ;; + csky_elf32_be_vec) tb="$tb elf32-csky.lo elf32.lo $elf" ;; + csky_elf32_le_vec) tb="$tb elf32-csky.lo elf32.lo $elf" ;; d10v_elf32_vec) tb="$tb elf32-d10v.lo elf32.lo $elf" ;; d30v_elf32_vec) tb="$tb elf32-d30v.lo elf32.lo $elf" ;; dlx_elf32_be_vec) tb="$tb elf32-dlx.lo elf32.lo $elf" ;; diff --git a/bfd/cpu-csky.c b/bfd/cpu-csky.c new file mode 100644 index 0000000..a8f251d --- /dev/null +++ b/bfd/cpu-csky.c @@ -0,0 +1,59 @@ +/* BFD support for C-SKY processors. + Copyright (C) 1994-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "libbfd.h" + +#define N(NUMBER, PRINT, ISDEFAULT, NEXT) \ +{ \ + 32, /* 32 bits in a word */ \ + 32, /* 32 bits in an address */ \ + 8, /* 8 bits in a byte */ \ + bfd_arch_csky, /* Architecture */ \ + NUMBER, /* Machine number */ \ + "csky", /* Architecture name */ \ + PRINT, /* Printable name */ \ + 3, /* Section align power */ \ + ISDEFAULT, /* Is this the default architecture ? */ \ + bfd_default_compatible, /* Architecture comparison function */ \ + bfd_default_scan, /* String to architecture conversion */ \ + bfd_arch_default_fill, \ + NEXT /* Next in list */ \ +} + +static const bfd_arch_info_type arch_info_struct[] = +{ + /* ABI v1 processors. */ + N (bfd_mach_ck510, "csky:ck510", FALSE, & arch_info_struct[1]), + N (bfd_mach_ck610, "csky:ck610", FALSE, & arch_info_struct[2]), + + /* ABI v2 processors. */ + N (bfd_mach_ck801, "csky:ck801", FALSE, & arch_info_struct[3]), + N (bfd_mach_ck802, "csky:ck802", FALSE, & arch_info_struct[4]), + N (bfd_mach_ck803, "csky:ck803", FALSE, & arch_info_struct[5]), + N (bfd_mach_ck807, "csky:ck807", FALSE, & arch_info_struct[6]), + N (bfd_mach_ck810, "csky:ck810", FALSE, & arch_info_struct[7]), + N (bfd_mach_ck_unknown, "csky:any", FALSE, NULL) +}; + +const bfd_arch_info_type bfd_csky_arch = + N (0, "csky", TRUE, & arch_info_struct[0]); diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h index 3ff39a9..ba1b495 100644 --- a/bfd/elf-bfd.h +++ b/bfd/elf-bfd.h @@ -489,6 +489,7 @@ enum elf_target_id AVR_ELF_DATA, BFIN_ELF_DATA, CRIS_ELF_DATA, + CSKY_ELF_DATA, FRV_ELF_DATA, HPPA32_ELF_DATA, HPPA64_ELF_DATA, diff --git a/bfd/elf32-csky.c b/bfd/elf32-csky.c new file mode 100644 index 0000000..d406b5a --- /dev/null +++ b/bfd/elf32-csky.c @@ -0,0 +1,5197 @@ +/* 32-bit ELF support for C-SKY. + Copyright (C) 1998-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "bfd.h" +#include "bfdlink.h" +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/csky.h" +#include "opcode/csky.h" +#include <assert.h> +#include "libiberty.h" + +/* Data structures used for merging different arch variants. + V1 (510/610) and V2 (8xx) processors are incompatible, but + we can merge wthin each family. */ + +enum merge_class +{ + CSKY_V1, + CSKY_V2 +}; + +typedef struct csky_arch_for_merge +{ + const char *name; + const unsigned long arch_eflag; + /* The files can merge only if they are in same class. */ + enum merge_class class; + /* When input files have different levels, + the target sets arch_eflag to the largest level file's arch_eflag. */ + unsigned int class_level; + /* Control whether to print warning when merging with different arch. */ + unsigned int do_warning; +} csky_arch_for_merge; + +static struct csky_arch_for_merge csky_archs[] = +{ + /* 510 and 610 merge to 610 without warning. */ + { "510", CSKY_ARCH_510, CSKY_V1, 0, 0}, + { "610", CSKY_ARCH_610, CSKY_V1, 1, 0}, + /* 801, 802, 803, 807, 810 merge to largest one. */ + { "801", CSKY_ARCH_801, CSKY_V2, 0, 1}, + { "802", CSKY_ARCH_802, CSKY_V2, 1, 1}, + { "803", CSKY_ARCH_803, CSKY_V2, 2, 1}, + { "807", CSKY_ARCH_807, CSKY_V2, 3, 1}, + { "810", CSKY_ARCH_810, CSKY_V2, 4, 1}, + { NULL, 0, 0, 0, 0} +}; + +/* Return the ARCH bits out of ABFD. */ +#define bfd_csky_arch(abfd) \ + (elf_elfheader (abfd)->e_flags & CSKY_ARCH_MASK) + +/* Return the ABI bits out of ABFD. */ +#define bfd_csky_abi(abfd) \ + (elf_elfheader (abfd)->e_flags & CSKY_ABI_MASK) + + +/* The index of a howto-item is implicitly equal to + the corresponding Relocation Type Encoding. */ +static reloc_howto_type csky_elf_howto_table[] = +{ + /* 0 */ + HOWTO (R_CKCORE_NONE, /* type */ + 0, /* rightshift */ + 0, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_NONE", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 1. */ + HOWTO (R_CKCORE_ADDR32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_ADDR32", /* name */ + FALSE, /* partial_inplace */ + 0, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 2: Only for csky v1. */ + HOWTO (R_CKCORE_PCREL_IMM8BY4, /* type */ + 2, /* rightshift */ + 1, /* size */ + 8, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL_IMM8BY4", /* name */ + FALSE, /* partial_inplace */ + 0xff, /* src_mask */ + 0xff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 3: Only for csky v1. */ + HOWTO (R_CKCORE_PCREL_IMM11BY2, /* type */ + 1, /* rightshift */ + 1, /* size */ + 11, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_IMM11BY2", /* name */ + FALSE, /* partial_inplace */ + 0x7ff, /* src_mask */ + 0x7ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 4: DELETED. */ + HOWTO (R_CKCORE_PCREL_IMM4BY2,0,0,0,0,0,0,0,"R_CKCORE_PCREL_IMM4BY2",0,0,0,0), + + /* 5. */ + HOWTO (R_CKCORE_PCREL32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL32", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 6: Only for csky v1. */ + HOWTO (R_CKCORE_PCREL_JSR_IMM11BY2, /* type */ + 1, /* rightshift */ + 1, /* size */ + 11, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_JSR_IMM11BY2", /* name */ + FALSE, /* partial_inplace */ + 0x7ff, /* src_mask */ + 0x7ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 7: GNU extension to record C++ vtable member usage. */ + HOWTO (R_CKCORE_GNU_VTENTRY, /* type */ + 0, /* rightshift */ + 2, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + _bfd_elf_rel_vtable_reloc_fn, /* special_function */ + "R_CKCORE_GNU_VTENTRY", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 8: GNU extension to record C++ vtable hierarchy. */ + HOWTO (R_CKCORE_GNU_VTINHERIT, /* type */ + 0, /* rightshift */ + 2, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_GNU_VTINHERIT", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 9. */ + HOWTO (R_CKCORE_RELATIVE, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_RELATIVE", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 10: None. */ + /* FIXME: It is a bug that copy relocations are not implemented. */ + HOWTO (R_CKCORE_COPY, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_COPY", /* name */ + TRUE, /* partial_inplace */ + 0xffffffff, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 11: None. */ + HOWTO (R_CKCORE_GLOB_DAT,0,0,0,0,0,0,0,"R_CKCORE_GLOB_DAT",0,0,0,0), + + /* 12: None. */ + HOWTO (R_CKCORE_JUMP_SLOT,0,0,0,0,0,0,0,"R_CKCORE_JUMP_SLOT",0,0,0,0), + + /* 13. */ + HOWTO (R_CKCORE_GOTOFF, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTOFF", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffffl, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 14. */ + HOWTO (R_CKCORE_GOTPC, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTPC", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 15. */ + HOWTO (R_CKCORE_GOT32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOT32", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 16. */ + HOWTO (R_CKCORE_PLT32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PLT32", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 17: None. */ + HOWTO (R_CKCORE_ADDRGOT,0,0,0,0,0,0,0,"R_CKCORE_ADDRGOT",0,0,0,0), + + /* 18: None. */ + HOWTO (R_CKCORE_ADDRPLT,0,0,0,0,0,0,0,"R_CKCORE_ADDRPLT",0,0,0,0), + + /* 19: Only for csky v2. */ + HOWTO (R_CKCORE_PCREL_IMM26BY2, /* type */ + 1, /* rightshift */ + 2, /* size */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_IMM26BY2", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 20: Only for csky v2. */ + HOWTO (R_CKCORE_PCREL_IMM16BY2, /* type */ + 1, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL_IMM16BY2", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 21: Only for csky v2. */ + HOWTO (R_CKCORE_PCREL_IMM16BY4, /* type */ + 2, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL_IMM16BY4", /* name */ + FALSE, /* partial_inplace */ + 0xffff0000, /* src_mask */ + 0xffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 22: Only for csky v2. */ + HOWTO (R_CKCORE_PCREL_IMM10BY2, /* type */ + 1, /* rightshift */ + 1, /* size */ + 10, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_IMM10BY2", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 23: Only for csky v2. */ + HOWTO (R_CKCORE_PCREL_IMM10BY4, /* type */ + 2, /* rightshift */ + 2, /* size */ + 10, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL_IMM10BY4", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 24: Only for csky v2. */ + HOWTO (R_CKCORE_ADDR_HI16, /* type */ + 16, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_ADDR_HI16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 25. */ + HOWTO (R_CKCORE_ADDR_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_ADDR_LO16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 26. */ + HOWTO (R_CKCORE_GOTPC_HI16, /* type */ + 16, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTPC_HI16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 27. */ + HOWTO (R_CKCORE_GOTPC_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTPC_LO16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 28. */ + HOWTO (R_CKCORE_GOTOFF_HI16, /* type */ + 16, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTOFF_HI16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 29. */ + HOWTO (R_CKCORE_GOTOFF_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTOFF_LO16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 30. */ + HOWTO (R_CKCORE_GOT12, /* type */ + 2, /* rightshift */ + 2, /* size */ + 12, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOT12", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xfff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 31. */ + HOWTO (R_CKCORE_GOT_HI16, /* type */ + 16, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOT_HI16", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 32. */ + HOWTO (R_CKCORE_GOT_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOT_LO16", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 33. */ + HOWTO (R_CKCORE_PLT12, /* type */ + 2, /* rightshift */ + 2, /* size */ + 12, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PLT12", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xfff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 34. */ + HOWTO (R_CKCORE_PLT_HI16, /* type */ + 16, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PLT_HI16", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 35. */ + HOWTO (R_CKCORE_PLT_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PLT_LO16", /* name */ + TRUE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 36: None. */ + HOWTO (R_CKCORE_ADDRGOT_HI16,0,0,0,0,0,0,0,"R_CKCORE_",0,0,0,0), + + /* 37: None. */ + HOWTO (R_CKCORE_ADDRGOT_LO16,0,0,0,0,0,0,0,"R_CKCORE_",0,0,0,0), + + /* 38: None. */ + HOWTO (R_CKCORE_ADDRPLT_HI16,0,0,0,0,0,0,0,"R_CKCORE_",0,0,0,0), + + /* 39: None. */ + HOWTO (R_CKCORE_ADDRPLT_LO16,0,0,0,0,0,0,0,"R_CKCORE_",0,0,0,0), + + /* 40. */ + HOWTO (R_CKCORE_PCREL_JSR_IMM26BY2, /* type */ + 1, /* rightshift */ + 2, /* size */ + 26, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_JSR_IMM26BY2", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 41. */ + HOWTO (R_CKCORE_TOFFSET_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_TOFFSET_LO16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 42. */ + HOWTO (R_CKCORE_DOFFSET_LO16, /* type */ + 0, /* rightshift */ + 2, /* size */ + 16, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_DOFFSET_LO16", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 43. */ + HOWTO (R_CKCORE_PCREL_IMM18BY2, /* type */ + 1, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL_IMM18BY2", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 44. */ + HOWTO (R_CKCORE_DOFFSET_IMM18, /* type */ + 0, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_DOFFSET_IMM18", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 45. */ + HOWTO (R_CKCORE_DOFFSET_IMM18BY2, /* type */ + 1, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_DOFFSET_IMM18BY2", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 46. */ + HOWTO (R_CKCORE_DOFFSET_IMM18BY4, /* type */ + 2, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_unsigned, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_DOFFSET_IMM18BY4", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x3ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 47. */ + HOWTO (R_CKCORE_GOTOFF_IMM18, /* type */ + 0, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOTOFF_IMM18", /* name */ + TRUE, /* partial_inplace */ + 0xfffc, /* src_mask */ + 0x3ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 48. */ + HOWTO (R_CKCORE_GOT_IMM18BY4, /* type */ + 2, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_GOT_IMM18BY4", /* name */ + TRUE, /* partial_inplace */ + 0xfffc, /* src_mask */ + 0x3ffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 49. */ + HOWTO (R_CKCORE_PLT_IMM18BY4, /* type */ + 2, /* rightshift */ + 2, /* size */ + 18, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PLT_IMM18BY4", /* name */ + TRUE, /* partial_inplace */ + 0xfffc, /* src_mask */ + 0x3ffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 50: for lrw16. */ + HOWTO (R_CKCORE_PCREL_IMM7BY4, /* type */ + 2, /* rightshift */ + 1, /* size */ + 7, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_IMM7BY4", /* name */ + FALSE, /* partial_inplace */ + 0xec1f, /* src_mask */ + 0x31f, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 51: for static nptl. */ + HOWTO (R_CKCORE_TLS_LE32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_TLS_LE32", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 52: for static nptl. */ + HOWTO (R_CKCORE_TLS_IE32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_TLS_IE32", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 53: for pic nptl. */ + HOWTO (R_CKCORE_TLS_GD32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_TLS_GD32", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 54: for pic nptl. */ + HOWTO (R_CKCORE_TLS_LDM32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_TLS_LDM32", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 55: for pic nptl. */ + HOWTO (R_CKCORE_TLS_LDO32, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_TLS_LDO32", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xffffffff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 56: for linker. */ + HOWTO (R_CKCORE_TLS_DTPMOD32,0,0,0,0,0,0,0,"R_CKCORE_TLS_DTPMOD32",0,0,0,0), + + /* 57: for linker. */ + HOWTO (R_CKCORE_TLS_DTPOFF32,0,0,0,0,0,0,0,"R_CKCORE_TLS_DTPOFF32",0,0,0,0), + + /* 58: for linker. */ + HOWTO (R_CKCORE_TLS_TPOFF32,0,0,0,0,0,0,0,"R_CKCORE_TLS_TPOFF32",0,0,0,0), + + /* 59: for ck807f. */ + HOWTO (R_CKCORE_PCREL_FLRW_IMM8BY4, /* type */ + 2, /* rightshift */ + 2, /* size */ + 8, /* bitsize */ + TRUE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_bitfield, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_PCREL_FLRW_IMM8BY4", /* name */ + FALSE, /* partial_inplace */ + 0xfe1fff0f, /* src_mask */ + 0x1e000f0, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 60: for 810 not to generate jsri. */ + HOWTO (R_CKCORE_NOJSRI, /* type */ + 0, /* rightshift */ + 2, /* size */ + 32, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_NOJSRI", /* name */ + FALSE, /* partial_inplace */ + 0xffff, /* src_mask */ + 0xffff, /* dst_mask */ + FALSE), /* pcrel_offset */ + + /* 61: for callgraph. */ + HOWTO (R_CKCORE_CALLGRAPH, /* type */ + 0, /* rightshift */ + 0, /* size */ + 0, /* bitsize */ + FALSE, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_dont, /* complain_on_overflow */ + NULL, /* special_function */ + "R_CKCORE_CALLGRAPH", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0x0, /* dst_mask */ + TRUE), /* pcrel_offset */ + + /* 62: IRELATIVE*/ + HOWTO (R_CKCORE_IRELATIVE,0,0,0,0,0,0,0,"R_CKCORE_IRELATIVE",0,0,0,0), + + /* 63: for bloop instruction */ + HOWTO (R_CKCORE_PCREL_BLOOP_IMM4BY4, /* type */ + 1, /* rightshift */ + 2, /* size */ + 4, /* bitsize */ + 1, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_BLOOP_IMM4BY4", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xf, /* dst_mask */ + TRUE), /* pcrel_offset */ + /* 64: for bloop instruction */ + HOWTO (R_CKCORE_PCREL_BLOOP_IMM12BY4, /* type */ + 1, /* rightshift */ + 2, /* size */ + 12, /* bitsize */ + 1, /* pc_relative */ + 0, /* bitpos */ + complain_overflow_signed, /* complain_on_overflow */ + bfd_elf_generic_reloc, /* special_function */ + "R_CKCORE_PCREL_BLOOP_IMM12BY4", /* name */ + FALSE, /* partial_inplace */ + 0x0, /* src_mask */ + 0xfff, /* dst_mask */ + TRUE), /* pcrel_offset */ + + +}; + + +/* Whether GOT overflow checking is needed. */ +static int check_got_overflow = 0; + +/* Whether the target 32 bits is forced so that the high + 16 bits is at the low address. */ +static int need_reverse_bits; + +/* Used for relaxation. See csky_relocate_contents. */ +static bfd_vma read_content_substitute; + +/* NOTICE! + The way the following two look-up functions work demands + that BFD_RELOC_CKCORE_xxx are defined contiguously. */ + +static reloc_howto_type * +csky_elf_reloc_type_lookup (bfd * abfd ATTRIBUTE_UNUSED, + bfd_reloc_code_real_type code) +{ + int csky_code = code - BFD_RELOC_CKCORE_NONE; + + if (csky_code < 0 || csky_code >= R_CKCORE_MAX) + { + switch (code) + { + case BFD_RELOC_NONE: + csky_code = R_CKCORE_NONE; + break; + case BFD_RELOC_32: + csky_code = R_CKCORE_ADDR32; + break; + case BFD_RELOC_32_PCREL: + csky_code = R_CKCORE_PCREL32; + break; + case BFD_RELOC_VTABLE_INHERIT: + csky_code = R_CKCORE_GNU_VTINHERIT; + break; + case BFD_RELOC_VTABLE_ENTRY: + csky_code = R_CKCORE_GNU_VTENTRY; + break; + case BFD_RELOC_RVA: + csky_code = R_CKCORE_RELATIVE; + break; + default: + return (reloc_howto_type *)NULL; + } + } + /* Note: when adding csky bfd reloc types in bfd-in2.h + and csky elf reloc types in elf/csky.h, + the order of the two reloc type tables should be consistent. */ + return &csky_elf_howto_table[csky_code]; +} + +static reloc_howto_type * +csky_elf_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, + const char *r_name) +{ + unsigned int i; + for (i = 0; i < R_CKCORE_MAX; i++) + if (strcasecmp (csky_elf_howto_table[i].name, r_name) == 0) + return &csky_elf_howto_table[i]; + return NULL; +} + +static reloc_howto_type * +elf32_csky_howto_from_type (unsigned int r_type) +{ + if (r_type < R_CKCORE_MAX) + return &csky_elf_howto_table[r_type]; + else + return NULL; +} + +static bfd_boolean +csky_elf_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED, + arelent *cache_ptr, + Elf_Internal_Rela *dst) +{ + unsigned int r_type; + + r_type = ELF32_R_TYPE (dst->r_info); + cache_ptr->howto = elf32_csky_howto_from_type (r_type); + if (cache_ptr->howto == NULL) + { + /* xgettext:c-format */ + _bfd_error_handler (_("%pB: unsupported relocation type %#x"), + abfd, r_type); + bfd_set_error (bfd_error_bad_value); + return FALSE; + } + return TRUE; +} + +/* The Global Offset Table max size. */ +#define GOT_MAX_SIZE 0xFFFF8 + +/* The name of the dynamic interpreter. This is put in the .interp + section. */ +#define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1" + +/* The size in bytes of an entry in the procedure linkage table. */ +#define PLT_ENTRY_SIZE 12 +#define PLT_ENTRY_SIZE_P 16 + +/* The first entry in a procedure linkage table looks like + this. It is set up so that any shared library function that is + called before the relocation has been set up calls the dynamic + linker first. */ +static const bfd_vma csky_elf_plt_entry_v2[PLT_ENTRY_SIZE / 4] = +{ + 0xd99c2002, /* ldw r12, (gb, 8) */ + 0xea0d0000, /* movi r13,offset */ + 0xe8cc0000 /* jmp r12 */ +}; + +static const bfd_vma csky_elf_plt_entry_v1[PLT_ENTRY_SIZE / 2 ] = +{ + 0x25f0, /* subi r0, 32 */ + 0x9200, /* stw r2, (r0, 0) */ + 0x9310, /* stw r3, (r0, 4) */ + 0x822e, /* ldw r2, (gb, 8) */ + 0x7301, /* lrw r3, #offset */ + 0x00c2, /* jmp r2 */ +}; + +/* Branch stub support. */ + +enum stub_insn_type +{ + INSN16, + INSN32, + DATA_TYPE +}; + +bfd_boolean use_branch_stub = TRUE; +typedef struct +{ + bfd_vma data; + enum stub_insn_type type; + unsigned int r_type; + int reloc_addend; +} insn_sequence; + +static const insn_sequence elf32_csky_stub_long_branch[] = +{ + {0xea8d0002, INSN32, R_CKCORE_NONE, 0x0}, /* lrw t1,[pc+8] */ + {0x7834, INSN16, R_CKCORE_NONE, 0x0}, /* jmp t1 */ + {0x6c03, INSN16, R_CKCORE_NONE, 0x0}, /* nop */ + {0x0, DATA_TYPE, R_CKCORE_ADDR32, 0x0} /* .long addr */ +}; + +static const insn_sequence elf32_csky_stub_long_branch_jmpi[] = +{ + {0xeac00001, INSN32, R_CKCORE_NONE, 0x0}, /* jmpi [pc+4] */ + {0x0, DATA_TYPE, R_CKCORE_ADDR32, 0x0} /* .long addr */ +}; + +/* The bsr instruction offset limit. */ +#define BSR_MAX_FWD_BRANCH_OFFSET (((1 << 25) - 1) << 1) +#define BSR_MAX_BWD_BRANCH_OFFSET (-(1 << 26)) + +#define STUB_SUFFIX ".stub" +#define STUB_ENTRY_NAME "__%s_veneer" + +/* One entry per long/short branch stub defined above. */ +#define DEF_STUBS \ + DEF_STUB(long_branch) \ + DEF_STUB(long_branch_jmpi) + +#define DEF_STUB(x) csky_stub_##x, +enum elf32_csky_stub_type +{ + csky_stub_none, + DEF_STUBS +}; +#undef DEF_STUB + +typedef struct +{ + const insn_sequence* template_sequence; + int template_size; +} stub_def; + +#define DEF_STUB(x) {elf32_csky_stub_##x, ARRAY_SIZE(elf32_csky_stub_##x)}, +static const stub_def stub_definitions[] = { + {NULL, 0}, + DEF_STUBS +}; + +/* The size of the thread control block. */ +#define TCB_SIZE 8 + +struct csky_elf_obj_tdata +{ + struct elf_obj_tdata root; + + /* tls_type for each local got entry. */ + char *local_got_tls_type; +}; + +#define csky_elf_local_got_tls_type(bfd) \ + (csky_elf_tdata (bfd)->local_got_tls_type) + +#define csky_elf_tdata(bfd) \ + ((struct csky_elf_obj_tdata *) (bfd)->tdata.any) + +struct elf32_csky_stub_hash_entry +{ + /* Base hash table entry structure. */ + struct bfd_hash_entry root; + + /* The stub section. */ + asection *stub_sec; + + /* Offset within stub_sec of the beginning of this stub. */ + bfd_vma stub_offset; + + /* Given the symbol's value and its section we can determine its final + value when building the stubs (so the stub knows where to jump). */ + bfd_vma target_value; + asection *target_section; + + /* Offset to apply to relocation referencing target_value. */ + bfd_vma target_addend; + + /* The stub type. */ + enum elf32_csky_stub_type stub_type; + /* Its encoding size in bytes. */ + int stub_size; + /* Its template. */ + const insn_sequence *stub_template; + /* The size of the template (number of entries). */ + int stub_template_size; + + /* The symbol table entry, if any, that this was derived from. */ + struct csky_elf_link_hash_entry *h; + + /* Destination symbol type. */ + unsigned char st_type; + + /* Where this stub is being called from, or, in the case of combined + stub sections, the first input section in the group. */ + asection *id_sec; + + /* The name for the local symbol at the start of this stub. The + stub name in the hash table has to be unique; this does not, so + it can be friendlier. */ + char *output_name; +}; + +#define csky_stub_hash_lookup(table, string, create, copy) \ + ((struct elf32_csky_stub_hash_entry *) \ + bfd_hash_lookup ((table), (string), (create), (copy))) + +/* C-SKY ELF linker hash entry. */ +struct csky_elf_link_hash_entry +{ + struct elf_link_hash_entry elf; + int plt_refcount; + /* For sub jsri2bsr relocs count. */ + int jsri2bsr_refcount; + /* Track dynamic relocs copied for this symbol. */ + struct elf_dyn_relocs *dyn_relocs; + +#define GOT_UNKNOWN 0 +#define GOT_NORMAL 1 +#define GOT_TLS_GD 2 +#define GOT_TLS_IE 4 + + unsigned char tls_type; + + /* A pointer to the most recently used stub hash entry against this + symbol. */ + struct elf32_csky_stub_hash_entry *stub_cache; +}; + +/* Traverse an C-SKY ELF linker hash table. */ +#define csky_elf_link_hash_traverse(table, func, info) \ + (elf_link_hash_traverse \ + (&(table)->root, \ + (bfd_boolean (*) PARAMS ((struct elf_link_hash_entry *, PTR))) (func), \ + (info))) + +/* Get the C-SKY ELF linker hash table from a link_info structure. */ +#define csky_elf_hash_table(info) \ + ((elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \ + == CSKY_ELF_DATA) \ + ? ((struct csky_elf_link_hash_table *) ((info)->hash)) \ + : NULL) + +#define csky_elf_hash_entry(ent) ((struct csky_elf_link_hash_entry*)(ent)) + +/* Array to keep track of which stub sections have been created, and + information on stub grouping. */ +struct map_stub +{ + /* This is the section to which stubs in the group will be + attached. */ + asection *link_sec; + /* The stub section. */ + asection *stub_sec; +}; + +/* C-SKY ELF linker hash table. */ +struct csky_elf_link_hash_table +{ + struct elf_link_hash_table elf; + + /* Small local sym cache. */ + struct sym_cache sym_cache; + + /* Data for R_CKCORE_TLS_LDM32 relocations. */ + union + { + bfd_signed_vma refcount; + bfd_vma offset; + } tls_ldm_got; + + /* The stub hash table. */ + struct bfd_hash_table stub_hash_table; + + /* Linker stub bfd. */ + bfd *stub_bfd; + + /* Linker call-backs. */ + asection * (*add_stub_section) (const char *, asection *); + void (*layout_sections_again) (void); + + /* Array to keep track of which stub sections have been created, and + * information on stub grouping. */ + struct map_stub *stub_group; + + /* Number of elements in stub_group. */ + unsigned int top_id; + + /* Assorted information used by elf32_csky_size_stubs. */ + unsigned int bfd_count; + unsigned int top_index; + asection **input_list; +}; + +/* We can't change vectors in the bfd target which will apply to + data sections, however we only do this to the text sections. */ + +static bfd_vma +csky_get_insn_32 (bfd *input_bfd, + bfd_byte *location) +{ + if (bfd_big_endian (input_bfd)) + return bfd_get_32 (input_bfd, location); + else + return (bfd_get_16 (input_bfd, location) << 16 + | bfd_get_16 (input_bfd, location + 2)); +} + +static void +csky_put_insn_32 (bfd *input_bfd, + bfd_vma x, + bfd_byte *location) +{ + if (bfd_big_endian (input_bfd)) + bfd_put_32 (input_bfd, x, location); + else + { + bfd_put_16 (input_bfd, x >> 16, location); + bfd_put_16 (input_bfd, x & 0xffff, location + 2); + } +} + +/* Find or create a stub section. Returns a pointer to the stub section, and + the section to which the stub section will be attached (in *LINK_SEC_P). + LINK_SEC_P may be NULL. */ + +static asection * +elf32_csky_create_or_find_stub_sec (asection **link_sec_p, asection *section, + struct csky_elf_link_hash_table *htab) +{ + asection *link_sec; + asection *stub_sec; + + link_sec = htab->stub_group[section->id].link_sec; + stub_sec = htab->stub_group[section->id].stub_sec; + if (stub_sec == NULL) + { + stub_sec = htab->stub_group[link_sec->id].stub_sec; + if (stub_sec == NULL) + { + size_t namelen; + bfd_size_type len; + char *s_name; + + namelen = strlen (link_sec->name); + len = namelen + sizeof (STUB_SUFFIX); + s_name = bfd_alloc (htab->stub_bfd, len); + if (s_name == NULL) + return NULL; + + memcpy (s_name, link_sec->name, namelen); + memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX)); + stub_sec = (*htab->add_stub_section) (s_name, link_sec); + if (stub_sec == NULL) + return NULL; + htab->stub_group[link_sec->id].stub_sec = stub_sec; + } + htab->stub_group[section->id].stub_sec = stub_sec; + } + + if (link_sec_p) + *link_sec_p = link_sec; + + return stub_sec; +} + +/* Build a name for an entry in the stub hash table. */ + +static char * +elf32_csky_stub_name (const asection *input_section, + const asection *sym_sec, + const struct csky_elf_link_hash_entry *hash, + const Elf_Internal_Rela *rel) +{ + char *stub_name; + bfd_size_type len; + + if (hash) + { + len = 8 + 1 + strlen (hash->elf.root.root.string) + 1 + 8 + 1; + stub_name = bfd_malloc (len); + if (stub_name != NULL) + sprintf (stub_name, "%08x_%s+%x", + input_section->id & 0xffffffff, + hash->elf.root.root.string, + (int) rel->r_addend & 0xffffffff); + } + else + { + len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1; + stub_name = bfd_malloc (len); + if (stub_name != NULL) + sprintf (stub_name, "%08x_%x:%x+%x", + input_section->id & 0xffffffff, + sym_sec->id & 0xffffffff, + (int) ELF32_R_SYM (rel->r_info) & 0xffffffff, + (int) rel->r_addend & 0xffffffff); + } + + return stub_name; +} + +/* Determine the type of stub needed, if any, for a call. */ + +static enum elf32_csky_stub_type +csky_type_of_stub (struct bfd_link_info *info, + asection *input_sec, + const Elf_Internal_Rela *rel, + unsigned char st_type, + struct csky_elf_link_hash_entry *hash, + bfd_vma destination, + asection *sym_sec ATTRIBUTE_UNUSED, + bfd *input_bfd ATTRIBUTE_UNUSED, + const char *name ATTRIBUTE_UNUSED) +{ + bfd_vma location; + bfd_signed_vma branch_offset; + unsigned int r_type; + enum elf32_csky_stub_type stub_type = csky_stub_none; + struct elf_link_hash_entry * h = &hash->elf; + + /* We don't know the actual type of destination in case it is of + type STT_SECTION: give up. */ + if (st_type == STT_SECTION) + return stub_type; + + location = (input_sec->output_offset + + input_sec->output_section->vma + + rel->r_offset); + + branch_offset = (bfd_signed_vma)(destination - location); + r_type = ELF32_R_TYPE (rel->r_info); + if (r_type == R_CKCORE_PCREL_IMM26BY2 + && ((h != NULL + && ((h->def_dynamic && !h->def_regular) + || (bfd_link_pic (info) + && h->root.type == bfd_link_hash_defweak))) + || branch_offset > BSR_MAX_FWD_BRANCH_OFFSET + || branch_offset < BSR_MAX_BWD_BRANCH_OFFSET)) + { + if (bfd_csky_arch (info->output_bfd) == CSKY_ARCH_810 + || bfd_csky_arch (info->output_bfd) == CSKY_ARCH_807) + stub_type = csky_stub_long_branch_jmpi; + else + stub_type = csky_stub_long_branch; + } + + return stub_type; +} + +/* Create an entry in an C-SKY ELF linker hash table. */ + +static struct bfd_hash_entry * +csky_elf_link_hash_newfunc (struct bfd_hash_entry * entry, + struct bfd_hash_table * table, + const char * string) +{ + struct csky_elf_link_hash_entry * ret = + (struct csky_elf_link_hash_entry *) entry; + + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (ret == NULL) + { + ret = (struct csky_elf_link_hash_entry *) + bfd_hash_allocate (table, + sizeof (struct csky_elf_link_hash_entry)); + if (ret == NULL) + return (struct bfd_hash_entry *) ret; + } + + /* Call the allocation method of the superclass. */ + ret = ((struct csky_elf_link_hash_entry *) + _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *)ret, + table, string)); + if (ret != NULL) + { + struct csky_elf_link_hash_entry *eh; + + eh = (struct csky_elf_link_hash_entry *) ret; + eh->dyn_relocs = NULL; + eh->plt_refcount = 0; + eh->jsri2bsr_refcount = 0; + eh->tls_type = GOT_NORMAL; + ret->stub_cache = NULL; + } + + return (struct bfd_hash_entry *) ret; +} + +/* Initialize an entry in the stub hash table. */ + +static struct bfd_hash_entry * +stub_hash_newfunc (struct bfd_hash_entry *entry, + struct bfd_hash_table *table, + const char *string) +{ + /* Allocate the structure if it has not already been allocated by a + subclass. */ + if (entry == NULL) + { + entry = ((struct bfd_hash_entry *) + bfd_hash_allocate (table, + sizeof (struct elf32_csky_stub_hash_entry))); + if (entry == NULL) + return entry; + } + + /* Call the allocation method of the superclass. */ + entry = bfd_hash_newfunc (entry, table, string); + if (entry != NULL) + { + struct elf32_csky_stub_hash_entry *eh; + + /* Initialize the local fields. */ + eh = (struct elf32_csky_stub_hash_entry *) entry; + eh->stub_sec = NULL; + eh->stub_offset = 0; + eh->target_value = 0; + eh->target_section = NULL; + eh->target_addend = 0; + eh->stub_type = csky_stub_none; + eh->stub_size = 0; + eh->stub_template = NULL; + eh->stub_template_size = -1; + eh->h = NULL; + eh->id_sec = NULL; + eh->output_name = NULL; + } + + return entry; +} + +/* Free the derived linker hash table. */ + +static void +csky_elf_link_hash_table_free (bfd *obfd) +{ + struct csky_elf_link_hash_table *ret + = (struct csky_elf_link_hash_table *) obfd->link.hash; + + bfd_hash_table_free (&ret->stub_hash_table); + _bfd_elf_link_hash_table_free (obfd); +} + +/* Create an CSKY elf linker hash table. */ + +static struct bfd_link_hash_table * +csky_elf_link_hash_table_create (bfd *abfd) +{ + struct csky_elf_link_hash_table *ret; + bfd_size_type amt = sizeof (struct csky_elf_link_hash_table); + + ret = (struct csky_elf_link_hash_table*) bfd_zmalloc (amt); + if (ret == NULL) + return NULL; + + if (!_bfd_elf_link_hash_table_init (&ret->elf, abfd, + csky_elf_link_hash_newfunc, + sizeof (struct csky_elf_link_hash_entry), + CSKY_ELF_DATA)) + { + free (ret); + return NULL; + } + + if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc, + sizeof (struct elf32_csky_stub_hash_entry))) + { + free (ret); + return NULL; + } + ret->elf.root.hash_table_free = csky_elf_link_hash_table_free; + return &ret->elf.root; +} + +static bfd_boolean +csky_elf_mkobject (bfd *abfd) +{ + return bfd_elf_allocate_object (abfd, sizeof (struct csky_elf_obj_tdata), + CSKY_ELF_DATA); +} + +/* Adjust a symbol defined by a dynamic object and referenced by a + regular object. The current definition is in some section of the + dynamic object, but we're not including those sections. We have to + change the definition to something the rest of the link can + understand. */ + +static bfd_boolean +csky_elf_adjust_dynamic_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *h) +{ + struct csky_elf_link_hash_entry *eh; + struct csky_elf_link_hash_table *htab; + asection *srel; + asection *s; + eh = (struct csky_elf_link_hash_entry *)h; + if (eh == NULL) + return FALSE; + + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + + /* Clear jsri2bsr_refcount, if creating shared library files. */ + if (bfd_link_pic (info) && eh->jsri2bsr_refcount > 0) + eh->jsri2bsr_refcount = 0; + + /* If there is a function, put it in the procedure linkage table. We + will fill in the contents of the procedure linkage table later. */ + if (h->needs_plt) + { + /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the + symbol binds locally. */ + if (h->plt.refcount <= 0 + || (h->type != STT_GNU_IFUNC + && (SYMBOL_CALLS_LOCAL (info, h) + || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT + && h->root.type == bfd_link_hash_undefweak)))) + + { + /* This case can occur if we saw a PLT32 reloc in an input + file, but the symbol was never referred to by a dynamic + object, or if all references were garbage collected. In + such a case, we don't actually need to build a procedure + linkage table, and we can just do a PC32 reloc instead. */ + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + if (h->got.refcount == 0) + h->got.refcount += 1; + } + else if (h->got.refcount != 0) + { + h->got.refcount -= eh->plt_refcount; + eh->plt_refcount = 0; + } + return TRUE; + } + else + /* It's possible that we incorrectly decided a .plt reloc was + needed for an R_CKCORE_PC32 or similar reloc to a non-function + sym in check_relocs. We can't decide accurately between function + and non-function syms in check_relocs; objects loaded later in + the link may change h->type. So fix it now. */ + h->plt.offset = (bfd_vma) -1; + + /* If this is a weak symbol, and there is a real definition, the + processor independent code will have arranged for us to see the + real definition first, and we can just use the same value. */ + if (h->is_weakalias) + { + struct elf_link_hash_entry *def = weakdef (h); + BFD_ASSERT (def->root.type == bfd_link_hash_defined); + h->root.u.def.section = def->root.u.def.section; + h->root.u.def.value = def->root.u.def.value; + return TRUE; + } + + /* If there are no non-GOT references, we do not need a copy + relocation. */ + if (!h->non_got_ref) + return TRUE; + + /* This is a reference to a symbol defined by a dynamic object which + is not a function. */ + + /* If we are creating a shared library, we must presume that the + only references to the symbol are via the global offset table. + For such cases we need not do anything here; the relocations will + be handled correctly by relocate_section. */ + if (bfd_link_pic (info) || htab->elf.is_relocatable_executable) + return TRUE; + + /* We must allocate the symbol in our .dynbss section, which will + become part of the .bss section of the executable. There will be + an entry for this symbol in the .dynsym section. The dynamic + object will contain position independent code, so all references + from the dynamic object to this symbol will go through the global + offset table. The dynamic linker will use the .dynsym entry to + determine the address it must put in the global offset table, so + both the dynamic object and the regular object will refer to the + same memory location for the variable. */ + /* We must generate a R_CKCORE_COPY reloc to tell the dynamic linker to + copy the initial value out of the dynamic object and into the + runtime process image. We need to remember the offset into the + .rela.bss section we are going to use. */ + if ((h->root.u.def.section->flags & SEC_READONLY) != 0) + { + s = htab->elf.sdynrelro; + srel = htab->elf.sreldynrelro; + } + else + { + s = htab->elf.sdynbss; + srel = htab->elf.srelbss; + } + if (info->nocopyreloc == 0 + && (h->root.u.def.section->flags & SEC_ALLOC) != 0 + && h->size != 0 + && srel != NULL + && s != NULL) + { + srel->size += sizeof (Elf32_External_Rela); + h->needs_copy = 1; + return _bfd_elf_adjust_dynamic_copy (info, h, s); + } + + h->non_got_ref = 0; + return TRUE; +} + +/* Allocate space in .plt, .got and associated reloc sections for + dynamic relocs. */ + +static bfd_boolean +csky_allocate_dynrelocs (struct elf_link_hash_entry *h, PTR inf) +{ + struct bfd_link_info *info; + struct csky_elf_link_hash_table *htab; + struct csky_elf_link_hash_entry *eh; + struct elf_dyn_relocs *p; + + /* For indirect case, such as _ZdlPv to _ZdlPv@@GLIBCXX_3.4. */ + if (h->root.type == bfd_link_hash_indirect) + return TRUE; + + if (h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + + + info = (struct bfd_link_info *) inf; + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + /*TODO: how to deal with weak symbol relocs. */ + if ((htab->elf.dynamic_sections_created || h->type == STT_GNU_IFUNC) + && h->plt.refcount > 0) + { + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 && !h->forced_local + && h->root.type == bfd_link_hash_undefweak + && ! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + if (bfd_link_pic (info) || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h)) + { + asection *splt = htab->elf.splt; + + /* If this is the first .plt entry, make room for the special + first entry. */ + if (splt->size == 0) + { + if (bfd_csky_abi (info->output_bfd) == CSKY_ABI_V1) + splt->size += PLT_ENTRY_SIZE_P; + else + splt->size += PLT_ENTRY_SIZE; + } + h->plt.offset = splt->size; + + /* If this symbol is not defined in a regular file, and we are + not generating a shared library, then set the symbol to this + location in the .plt. This is required to make function + pointers compare as equal between the normal executable and + the shared library. */ + if (!bfd_link_pic (info) && !h->def_regular) + { + h->root.u.def.section = splt; + h->root.u.def.value = h->plt.offset; + } + + /* Make room for this entry. */ + if (bfd_csky_abi (info->output_bfd) == CSKY_ABI_V1) + splt->size += PLT_ENTRY_SIZE_P; + else + splt->size += PLT_ENTRY_SIZE; + /* We also need to make an entry in the .rela.plt section. */ + htab->elf.srelplt->size += sizeof (Elf32_External_Rela); + + /* We also need to make an entry in the .got.plt section, which + will be placed in the .got section by the linker script. */ + htab->elf.sgotplt->size += 4; + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + } + else + { + h->plt.offset = (bfd_vma) -1; + h->needs_plt = 0; + } + + if (h->got.refcount > 0) + { + asection *sgot; + bfd_boolean dyn; + int indx; + + int tls_type = csky_elf_hash_entry (h)->tls_type; + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 && !h->forced_local + && h->root.type == bfd_link_hash_undefweak + && ! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + + sgot = htab->elf.sgot; + h->got.offset = sgot->size; + BFD_ASSERT (tls_type != GOT_UNKNOWN); + if (tls_type == GOT_NORMAL) + /* Non-TLS symbols need one GOT slot. */ + sgot->size += 4; + else + { + if (tls_type & GOT_TLS_GD) + /* R_CKCORE_TLS_GD32 needs 2 consecutive GOT slots. */ + sgot->size += 8; + if (tls_type & GOT_TLS_IE) + /* R_CKCORE_TLS_IE32 needs one GOT slot. */ + sgot->size += 4; + } + dyn = htab->elf.dynamic_sections_created; + indx = 0; + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, bfd_link_pic (info), h) + && (! bfd_link_pic (info) || !SYMBOL_REFERENCES_LOCAL (info, h))) + indx = h->dynindx; + + if (tls_type != GOT_NORMAL + && (bfd_link_pic (info) || indx != 0) + && ((ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + || h->root.type != bfd_link_hash_undefweak)) + { + if (tls_type & GOT_TLS_IE) + htab->elf.srelgot->size += sizeof (Elf32_External_Rela); + if (tls_type & GOT_TLS_GD) + htab->elf.srelgot->size += sizeof (Elf32_External_Rela); + if ((tls_type & GOT_TLS_GD) && indx != 0) + htab->elf.srelgot->size += sizeof (Elf32_External_Rela); + } + else if (((ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + || h->root.type != bfd_link_hash_undefweak) + && (bfd_link_pic (info) + || WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, 0, h) + || h->plt.offset == (bfd_vma) -1)) + htab->elf.srelgot->size += sizeof (Elf32_External_Rela); + } + else + h->got.offset = (bfd_vma) -1; + + eh = (struct csky_elf_link_hash_entry *) h; + if (eh->dyn_relocs == NULL) + return TRUE; + + /* In the shared -Bsymbolic case, discard space allocated for + dynamic pc-relative relocs against symbols which turn out to be + defined in regular objects. For the normal shared case, discard + space for pc-relative relocs that have become local due to symbol + visibility changes. */ + + if (bfd_link_pic (info)) + { + if (SYMBOL_CALLS_LOCAL (info, h)) + { + struct elf_dyn_relocs **pp; + + for (pp = &eh->dyn_relocs; (p = *pp) != NULL; ) + { + p->count -= p->pc_count; + p->pc_count = 0; + if (p->count == 0) + *pp = p->next; + else + pp = &p->next; + } + } + + if (eh->jsri2bsr_refcount + && h->root.type == bfd_link_hash_defined + && eh->dyn_relocs != NULL) + eh->dyn_relocs->count -= eh->jsri2bsr_refcount; + + /* Also discard relocs on undefined weak syms with non-default + visibility. */ + if (eh->dyn_relocs != NULL + && h->root.type == bfd_link_hash_undefweak) + { + if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT + || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + eh->dyn_relocs = NULL; + + /* Make sure undefined weak symbols are output as a dynamic + symbol in PIEs. */ + else if (h->dynindx == -1 + && !h->forced_local + && !bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + } + else + { + /* For the non-shared case, discard space for relocs against + symbols which turn out to need copy relocs or are not + dynamic. */ + + if (!h->non_got_ref + && ((h->def_dynamic && !h->def_regular) + || (htab->elf.dynamic_sections_created + && (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_undefined)))) + { + /* Make sure this symbol is output as a dynamic symbol. + Undefined weak syms won't yet be marked as dynamic. */ + if (h->dynindx == -1 && !h->forced_local + && h->root.type == bfd_link_hash_undefweak) + { + if (! bfd_elf_link_record_dynamic_symbol (info, h)) + return FALSE; + } + + /* If that succeeded, we know we'll be keeping all the + relocs. */ + if (h->dynindx != -1) + goto keep; + } + + eh->dyn_relocs = NULL; + + keep: ; + } + + /* Finally, allocate space. */ + for (p = eh->dyn_relocs; p != NULL; p = p->next) + { + asection *srelgot = htab->elf.srelgot; + srelgot->size += p->count * sizeof (Elf32_External_Rela); + } + + return TRUE; +} + +static asection * +readonly_dynrelocs (struct elf_link_hash_entry *h) +{ + struct elf_dyn_relocs *p; + + for (p = csky_elf_hash_entry (h)->dyn_relocs; p != NULL; p = p->next) + { + asection *s = p->sec->output_section; + + if (s != NULL && (s->flags & SEC_READONLY) != 0) + return p->sec; + } + return NULL; +} + +/* Set DF_TEXTREL if we find any dynamic relocs that apply to + read-only sections. */ + +static bfd_boolean +maybe_set_textrel (struct elf_link_hash_entry *h, void *info_p) +{ + asection *sec; + + if (h->root.type == bfd_link_hash_indirect) + return TRUE; + + sec = readonly_dynrelocs (h); + if (sec != NULL) + { + struct bfd_link_info *info = (struct bfd_link_info *) info_p; + + info->flags |= DF_TEXTREL; + info->callbacks->minfo + (_("%pB: dynamic relocation against `%pT' in read-only section `%pA'\n"), + sec->owner, h->root.root.string, sec); + + /* Not an error, just cut short the traversal. */ + return FALSE; + } + return TRUE; +} + +/* Set the sizes of the dynamic sections. */ + +static bfd_boolean +csky_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED, + struct bfd_link_info *info) +{ + struct csky_elf_link_hash_table *htab; + bfd *dynobj; + asection *s; + bfd_boolean relocs; + bfd *ibfd; + + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + dynobj = htab->elf.dynobj; + if (dynobj == NULL) + return FALSE; + + if (htab->elf.dynamic_sections_created) + { + /* Set the contents of the .interp section to the interpreter. */ + if (!bfd_link_pic (info) && !info->nointerp) + { + s = bfd_get_section_by_name (dynobj, ".interp"); + BFD_ASSERT (s != NULL); + s->size = sizeof ELF_DYNAMIC_INTERPRETER; + s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER; + } + } + + /* Set up .got offsets for local syms, and space for local dynamic + relocs. */ + for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next) + { + bfd_signed_vma *local_got_refcounts; + bfd_signed_vma *end_local_got; + bfd_size_type locsymcount; + Elf_Internal_Shdr *symtab_hdr; + asection *srelgot, *sgot; + char *local_tls_type; + + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) + continue; + + sgot = htab->elf.sgot; + srelgot = htab->elf.srelgot; + + for (s = ibfd->sections; s != NULL; s = s->next) + { + struct elf_dyn_relocs *p; + + for (p = *((struct elf_dyn_relocs **) + &elf_section_data (s)->local_dynrel); + p != NULL; + p = p->next) + { + if (!bfd_is_abs_section (p->sec) + && bfd_is_abs_section (p->sec->output_section)) + /* Input section has been discarded, either because + it is a copy of a linkonce section or due to + linker script /DISCARD/, so we'll be discarding + the relocs too. */ + ; + else if (p->count != 0) + { + srelgot->size += p->count * sizeof (Elf32_External_Rela); + if ((p->sec->output_section->flags & SEC_READONLY) != 0) + info->flags |= DF_TEXTREL; + } + } + } + + local_got_refcounts = elf_local_got_refcounts (ibfd); + if (!local_got_refcounts) + continue; + + symtab_hdr = &elf_tdata (ibfd)->symtab_hdr; + locsymcount = symtab_hdr->sh_info; + end_local_got = local_got_refcounts + locsymcount; + local_tls_type = csky_elf_local_got_tls_type (ibfd); + + for (; local_got_refcounts < end_local_got; + ++local_got_refcounts, ++local_tls_type) + { + if (*local_got_refcounts > 0) + { + /* GOT_TLS_GD and GOT_TLS_IE type for TLS, GOT_NORMAL type + for GOT. If output file is shared library, we should output + GOT_TLS_GD type relocation in .rel.got. */ + *local_got_refcounts = sgot->size; + if (*local_tls_type & GOT_TLS_GD) + /* TLS_GD relocs need an 8-byte structure in the GOT. */ + sgot->size += 8; + if (*local_tls_type & GOT_TLS_IE) + sgot->size += 4; + if (*local_tls_type == GOT_NORMAL) + sgot->size += 4; + if (bfd_link_pic (info) || *local_tls_type == GOT_TLS_GD) + srelgot->size += sizeof (Elf32_External_Rela); + } + else + *local_got_refcounts = (bfd_vma) -1; + } + } + + if (htab->tls_ldm_got.refcount > 0) + { + /* Allocate two GOT entries and one dynamic relocation (if necessary) + for R_CSKY_TLS_LDM32 relocations. */ + htab->tls_ldm_got.offset = htab->elf.sgot->size; + htab->elf.sgot->size += 8; + if (bfd_link_pic (info)) + htab->elf.srelgot->size += sizeof (Elf32_External_Rela); + } + else + htab->tls_ldm_got.offset = -1; + + /* Allocate global sym .plt and .got entries, and space for global + sym dynamic relocs. */ + elf_link_hash_traverse (&htab->elf, csky_allocate_dynrelocs, (PTR) info); + + /* Check for GOT overflow. */ + if (check_got_overflow == 1 + && htab->elf.sgot->size + htab->elf.sgotplt->size > GOT_MAX_SIZE) + { + _bfd_error_handler (_("GOT table size out of range")); /* */ + return FALSE; + } + + /* We now have determined the sizes of the various dynamic sections. + Allocate memory for them. */ + relocs = FALSE; + for (s = dynobj->sections; s != NULL; s = s->next) + { + bfd_boolean strip_section = TRUE; + + if ((s->flags & SEC_LINKER_CREATED) == 0) + continue; + + if (s == htab->elf.splt + || s == htab->elf.sgot + || s == htab->elf.sgotplt + || s == htab->elf.sdynrelro + || s == htab->elf.sreldynrelro) + { + /* Strip this section if we don't need it; + see the comment below. */ + /* We'd like to strip these sections if they aren't needed, but if + we've exported dynamic symbols from them we must leave them. + It's too late to tell BFD to get rid of the symbols. */ + + if (htab->elf.hplt != NULL) + strip_section = FALSE; + } + else if (CONST_STRNEQ (bfd_get_section_name (dynobj, s), ".rel") ) + { + if (s->size != 0 ) + relocs = TRUE; + + /* We use the reloc_count field as a counter if we need + to copy relocs into the output file. */ + s->reloc_count = 0; + } + else + /* It's not one of our sections, so don't allocate space. */ + continue; + + /* Strip this section if we don't need it; see the + comment below. */ + if (s->size == 0) + { + /* If we don't need this section, strip it from the + output file. This is mostly to handle .rel.bss and + .rel.plt. We must create both sections in + create_dynamic_sections, because they must be created + before the linker maps input sections to output + sections. The linker does that before + adjust_dynamic_symbol is called, and it is that + function which decides whether anything needs to go + into these sections. */ + if (strip_section) + s->flags |= SEC_EXCLUDE; + continue; + } + + if ((s->flags & SEC_HAS_CONTENTS) == 0) + continue; + + /* Allocate memory for the section contents. We use bfd_zalloc + here in case unused entries are not reclaimed before the + section's contents are written out. This should not happen, + but this way if it does, we get a R_CKCORE_NONE reloc instead + of garbage. */ + s->contents = (bfd_byte *) bfd_zalloc (dynobj, s->size); + if (s->contents == NULL) + return FALSE; + } + + if (htab->elf.dynamic_sections_created) + { + /* Add some entries to the .dynamic section. We fill in the + values later, in csky_elf_finish_dynamic_sections, but we + must add the entries now so that we get the correct size for + the .dynamic section. The DT_DEBUG entry is filled in by the + dynamic linker and used by the debugger. */ +#define add_dynamic_entry(TAG, VAL) \ + _bfd_elf_add_dynamic_entry (info, TAG, VAL) + + if (bfd_link_executable (info) && !add_dynamic_entry (DT_DEBUG, 0)) + return FALSE; + + if (htab->elf.sgot->size != 0 || htab->elf.splt->size) + { + if (!add_dynamic_entry (DT_PLTGOT, 0) + || !add_dynamic_entry (DT_PLTRELSZ, 0) + || !add_dynamic_entry (DT_PLTREL, DT_RELA) + || !add_dynamic_entry (DT_JMPREL, 0)) + return FALSE; + } + + if (relocs) + { + if (!add_dynamic_entry (DT_RELA, 0) + || !add_dynamic_entry (DT_RELASZ, 0) + || !add_dynamic_entry (DT_RELAENT, + sizeof (Elf32_External_Rela))) + return FALSE; + + /* If any dynamic relocs apply to a read-only section, + then we need a DT_TEXTREL entry. */ + if ((info->flags & DF_TEXTREL) == 0) + elf_link_hash_traverse (&htab->elf, maybe_set_textrel, info); + + if ((info->flags & DF_TEXTREL) != 0 + && !add_dynamic_entry (DT_TEXTREL, 0)) + return FALSE; + } + } +#undef add_dynamic_entry + + return TRUE; +} + +/* Finish up dynamic symbol handling. We set the contents of various + dynamic sections here. */ + +static bfd_boolean +csky_elf_finish_dynamic_symbol (bfd *output_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + struct csky_elf_link_hash_table *htab; + + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + + /* Sanity check to make sure no unexpected symbol reaches here. + This matches the test in csky_elf_relocate_section handling + of GOT/PLT entries. */ + BFD_ASSERT (! (h->dynindx == -1 + && !h->forced_local + && h->root.type != bfd_link_hash_undefweak + && bfd_link_pic (info))); + + if (h->plt.offset != (bfd_vma) -1) + { + bfd_vma plt_index; + bfd_vma got_offset; + Elf_Internal_Rela rel; + bfd_byte *loc; + asection *plt, *relplt, *gotplt; + + plt = htab->elf.splt; + relplt = htab->elf.srelplt; + gotplt = htab->elf.sgotplt; + + /* This symbol has an entry in the procedure linkage table. Set + it up. */ + BFD_ASSERT (h->dynindx != -1 + || ((h->forced_local || bfd_link_executable (info)) + && h->def_regular)); + BFD_ASSERT (plt != NULL && gotplt != NULL && relplt != NULL); + if (bfd_csky_abi (output_bfd) == CSKY_ABI_V2) + plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1; + else + plt_index = h->plt.offset / PLT_ENTRY_SIZE_P - 1; + got_offset = (plt_index + 3) * 4; + + /* Fill in the entry in the procedure linkage table. */ + if (bfd_csky_abi (output_bfd) == CSKY_ABI_V2) + { + csky_put_insn_32 (output_bfd, csky_elf_plt_entry_v2[0], + plt->contents + h->plt.offset); + csky_put_insn_32 (output_bfd, + (csky_elf_plt_entry_v2[1] | plt_index), + plt->contents + h->plt.offset + 4); + csky_put_insn_32 (output_bfd, csky_elf_plt_entry_v2[2], + plt->contents + h->plt.offset + 8); + } + else + { + int i; + for (i = 0; i < 6; i++) + bfd_put_16 (output_bfd, csky_elf_plt_entry_v1[i], + plt->contents + h->plt.offset + i * 2); + bfd_put_32 (output_bfd, plt_index, + plt->contents + h->plt.offset + i * 2); + } + + /* Fill in the entry in the .rel.plt section. */ + rel.r_offset = (htab->elf.sgotplt->output_section->vma + + htab->elf.sgotplt->output_offset + + got_offset); + rel.r_info = ELF32_R_INFO (h->dynindx, R_CKCORE_JUMP_SLOT); + rel.r_addend = (plt->output_section->vma + + plt->output_offset + + h->plt.offset); + loc = (htab->elf.srelplt->contents + + plt_index * sizeof (Elf32_External_Rela)); + + if (loc != NULL) + bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + if (! h->def_regular) + { + /* Mark the symbol as undefined, rather than as defined in + the .plt section. Leave the value alone. */ + sym->st_shndx = SHN_UNDEF; + /* If the symbol is weak, we do need to clear the value. + Otherwise, the PLT entry would provide a definition for + the symbol even if the symbol wasn't defined anywhere, + and so the symbol would never be NULL. Leave the value if + there were any relocations where pointer equality matters + (this is a clue for the dynamic linker, to make function + pointer comparisons work between an application and shared + library). */ + if (!h->ref_regular_nonweak || !h->pointer_equality_needed) + sym->st_value = 0; + } + } + + /* Fill in the entry in the .got section. */ + if (h->got.offset != (bfd_vma) -1 + && ((csky_elf_hash_entry (h)->tls_type & GOT_TLS_GD) == 0) + && ((csky_elf_hash_entry (h)->tls_type & GOT_TLS_IE) == 0)) + { + Elf_Internal_Rela rel; + bfd_byte *loc; + + /* This symbol has an entry in the global offset table. + Set it up. */ + BFD_ASSERT (htab->elf.sgot != NULL && htab->elf.srelgot != NULL); + + rel.r_offset = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + + (h->got.offset & ~(bfd_vma) 1)); + + /* If this is a static link, or it is a -Bsymbolic link and the + symbol is defined locally or was forced to be local because + of a version file, we just want to emit a RELATIVE reloc. + The entry in the global offset table will already have been + initialized in the relocate_section function. */ + if (bfd_link_pic (info) && SYMBOL_REFERENCES_LOCAL (info, h)) + { + BFD_ASSERT ((h->got.offset & 1) != 0); + rel.r_info = ELF32_R_INFO (0, R_CKCORE_RELATIVE); + rel.r_addend = (h->root.u.def.value + + h->root.u.def.section->output_offset + + h->root.u.def.section->output_section->vma); + } + else + { + BFD_ASSERT ((h->got.offset & 1) == 0); + bfd_put_32 (output_bfd, (bfd_vma) 0, + htab->elf.sgot->contents + h->got.offset); + rel.r_info = ELF32_R_INFO (h->dynindx, R_CKCORE_GLOB_DAT); + rel.r_addend = 0; + } + + loc = htab->elf.srelgot->contents; + loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf32_External_Rela); + + if (loc != NULL) + bfd_elf32_swap_reloca_out (output_bfd, &rel, loc); + } + + if (h->needs_copy) + { + asection *s; + Elf_Internal_Rela rela; + bfd_byte *loc; + + /* This symbol needs a copy reloc. Set it up. */ + BFD_ASSERT (h->dynindx != -1 + && (h->root.type == bfd_link_hash_defined + || h->root.type == bfd_link_hash_defweak)); + + rela.r_offset = (h->root.u.def.value + + h->root.u.def.section->output_section->vma + + h->root.u.def.section->output_offset); + rela.r_info = ELF32_R_INFO (h->dynindx, R_CKCORE_COPY); + rela.r_addend = 0; + if (h->root.u.def.section == htab->elf.sdynrelro) + s = htab->elf.sreldynrelro; + else + s = htab->elf.srelbss; + BFD_ASSERT (s != NULL); + loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela); + bfd_elf32_swap_reloca_out (output_bfd, &rela, loc); + } + + /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. */ + if (strcmp (h->root.root.string, "_DYNAMIC") == 0 + || strcmp (h->root.root.string, "_GLOBAL_OFFSET_TABLE_") == 0) + sym->st_shndx = SHN_ABS; + + return TRUE; +} + +/* Finish up the dynamic sections. */ + +static bfd_boolean +csky_elf_finish_dynamic_sections (bfd *output_bfd, + struct bfd_link_info *info) +{ + struct csky_elf_link_hash_table *htab; + bfd *dynobj; + asection *sdyn; + asection *got_sec; + + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + + dynobj = htab->elf.dynobj; + sdyn = bfd_get_section_by_name (dynobj, ".dynamic"); + + if (htab->elf.dynamic_sections_created) + { + Elf32_External_Dyn *dyncon, *dynconend; + + BFD_ASSERT (sdyn != NULL && htab->elf.sgot != NULL); + + dyncon = (Elf32_External_Dyn *) sdyn->contents; + dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size); + for (; dyncon < dynconend; dyncon++) + { + Elf_Internal_Dyn dyn; + bfd_boolean size = FALSE; + const char *name = NULL; + + bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn); + switch (dyn.d_tag) + { + default: + continue; + case DT_RELA: + name = ".rela.dyn"; + size = FALSE; + break; + case DT_RELASZ: + name = ".rela.dyn"; + size = TRUE; + break; + case DT_PLTRELSZ: + name = ".rela.plt"; + size = TRUE; + break; + case DT_PLTGOT: + dyn.d_un.d_ptr = htab->elf.sgot->output_section->vma; + break; + case DT_JMPREL: + dyn.d_un.d_ptr = htab->elf.srelplt->output_section->vma + + htab->elf.srelplt->output_offset; + break; + } + + if (name != NULL) + { + asection *s = bfd_get_section_by_name (output_bfd, name); + + if (s == NULL) + dyn.d_un.d_val = 0; + else if (!size) + dyn.d_un.d_ptr = s->vma; + else + dyn.d_un.d_val = s->size; + } + bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon); + } + } + + /* Fill in the first three entries in the global offset table. */ + if (htab->elf.sgotplt) + got_sec = htab->elf.sgotplt; + else + got_sec = htab->elf.sgot; + if (got_sec != NULL) + { + if (got_sec->size > 0) + { + bfd_put_32 (output_bfd, + (sdyn == NULL ? (bfd_vma) 0 + : sdyn->output_section->vma + sdyn->output_offset), + got_sec->contents); + bfd_put_32 (output_bfd, (bfd_vma) 0, got_sec->contents + 4); + bfd_put_32 (output_bfd, (bfd_vma) 0, got_sec->contents + 8); + } + elf_section_data (got_sec->output_section)->this_hdr.sh_entsize = 4; + } + return TRUE; +} + +/* Copy the extra info we tack onto an elf_link_hash_entry. */ + +static void +csky_elf_copy_indirect_symbol (struct bfd_link_info *info, + struct elf_link_hash_entry *dir, + struct elf_link_hash_entry *ind) +{ + struct csky_elf_link_hash_entry *edir, *eind; + + edir = (struct csky_elf_link_hash_entry *) dir; + eind = (struct csky_elf_link_hash_entry *) ind; + + if (eind->dyn_relocs != NULL) + { + if (edir->dyn_relocs != NULL) + { + struct elf_dyn_relocs **pp; + struct elf_dyn_relocs *p; + + /* Add reloc counts against the indirect sym to the direct sym + list. Merge any entries against the same section. */ + for (pp = &eind->dyn_relocs; (p = *pp) != NULL; ) + { + struct elf_dyn_relocs *q; + + for (q = edir->dyn_relocs; q != NULL; q = q->next) + if (q->sec == p->sec) + { + q->pc_count += p->pc_count; + q->count += p->count; + *pp = p->next; + break; + } + if (q == NULL) + pp = &p->next; + } + *pp = edir->dyn_relocs; + } + edir->dyn_relocs = eind->dyn_relocs; + eind->dyn_relocs = NULL; + } + if (ind->root.type == bfd_link_hash_indirect + && dir->got.refcount <= 0) + { + edir->tls_type = eind->tls_type; + eind->tls_type = GOT_UNKNOWN; + } + _bfd_elf_link_hash_copy_indirect (info, dir, ind); +} + +/* Used to decide how to sort relocs in an optimal manner for the + dynamic linker, before writing them out. */ + +static enum elf_reloc_type_class +csky_elf_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED, + const asection *rel_sec ATTRIBUTE_UNUSED, + const Elf_Internal_Rela *rela) +{ + switch ((int) ELF32_R_TYPE (rela->r_info)) + { + case R_CKCORE_RELATIVE: + return reloc_class_relative; + case R_CKCORE_JUMP_SLOT: + return reloc_class_plt; + case R_CKCORE_COPY: + return reloc_class_copy; + case R_CKCORE_IRELATIVE: + return reloc_class_ifunc; + default: + return reloc_class_normal; + } +} + +/* Return the section that should be marked against GC for a given + relocation. */ + +static asection * +csky_elf_gc_mark_hook (asection *sec, + struct bfd_link_info *info, + Elf_Internal_Rela *rel, + struct elf_link_hash_entry *h, + Elf_Internal_Sym *sym) +{ + if (h != NULL) + { + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_CKCORE_GNU_VTINHERIT: + case R_CKCORE_GNU_VTENTRY: + return NULL; + } + } + + return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym); +} + +/* Look through the relocs for a section during the first phase. + Since we don't do .gots or .plts, we just need to consider the + virtual table relocs for gc. */ + +static bfd_boolean +csky_elf_check_relocs (bfd * abfd, + struct bfd_link_info * info, + asection * sec, + const Elf_Internal_Rela * relocs) +{ + Elf_Internal_Shdr * symtab_hdr; + struct elf_link_hash_entry ** sym_hashes; + const Elf_Internal_Rela * rel; + const Elf_Internal_Rela * rel_end; + struct csky_elf_link_hash_table *htab; + asection *sreloc; + + /* if output type is relocatable, return. */ + if (bfd_link_relocatable (info)) + return TRUE; + + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + + symtab_hdr = & elf_tdata (abfd)->symtab_hdr; + sym_hashes = elf_sym_hashes (abfd); + + rel_end = relocs + sec->reloc_count; + sreloc = NULL; + for (rel = relocs; rel < rel_end; rel++) + { + struct elf_link_hash_entry *h; + unsigned long r_symndx; + Elf_Internal_Sym *isym; + int r_type; + + r_symndx = ELF32_R_SYM (rel->r_info); + r_type = ELF32_R_TYPE (rel->r_info); + if (r_symndx < symtab_hdr->sh_info) + { + /* A local symbol. */ + isym = bfd_sym_from_r_symndx (&htab->sym_cache, + abfd, r_symndx); + if (isym == NULL) + return FALSE; + h = NULL; + } + else + { + isym = NULL; + h = sym_hashes[r_symndx - symtab_hdr->sh_info]; + while (h->root.type == bfd_link_hash_indirect + || h->root.type == bfd_link_hash_warning) + h = (struct elf_link_hash_entry *) h->root.u.i.link; + } + + switch (r_type) + { + case R_CKCORE_PCREL_IMM26BY2: + case R_CKCORE_PCREL_IMM11BY2: + case R_CKCORE_PCREL_JSR_IMM11BY2: + case R_CKCORE_PCREL_JSR_IMM26BY2: + /* If the symbol is '*UND*', means this reloc is used for + * callgraph, don't need to leave to shared object. */ + if (r_symndx == 0) + break; + /* Else fall through. */ + case R_CKCORE_ADDR32: + case R_CKCORE_ADDR_HI16: + case R_CKCORE_ADDR_LO16: + if (h != NULL + && bfd_link_executable (info) + && r_type == R_CKCORE_ADDR32 + && h->type == STT_OBJECT + && (sec->flags & SEC_ALLOC) != 0 + && (sec->flags & SEC_READONLY)) + /* If this reloc is in a read-only section, we might + need a copy reloc. We can't check reliably at this + stage whether the section is read-only, as input + sections have not yet been mapped to output sections. + Tentatively set the flag for now, and correct in + adjust_dynamic_symbol. */ + h->non_got_ref = 1; + + /* If we are creating a shared library or relocatable executable, + and this is a reloc against a global symbol, then we need to + copy the reloc into the shared library. However, if we are + linking with -Bsymbolic, we do not need to copy a reloc + against a global symbol which is defined in an object we are + including in the link (i.e., DEF_REGULAR is set). At + this point we have not seen all the input files, so it is + possible that DEF_REGULAR is not set now but will be set + later (it is never cleared). We account for that possibility + below by storing information in the relocs_copied field of + the hash table entry. */ + if ((bfd_link_pic (info) && (sec->flags & SEC_ALLOC) != 0) + || (!bfd_link_pic (info) + && (sec->flags & SEC_ALLOC) != 0 + && h != NULL + && (h->root.type == bfd_link_hash_defweak + || !h->def_regular))) + { + struct elf_dyn_relocs *p; + struct elf_dyn_relocs **head; + /* We must copy these reloc types into the output file. + Create a reloc section in dynobj and make room for + this reloc. */ + if (sreloc == NULL) + { + if (htab->elf.dynobj == NULL) + htab->elf.dynobj = abfd; + + sreloc = _bfd_elf_make_dynamic_reloc_section + (sec, htab->elf.dynobj, 2, abfd, TRUE); + + if (sreloc == NULL) + return FALSE; + } + + if (h == NULL && !use_branch_stub + && ((ELF32_R_TYPE (rel->r_info) + == R_CKCORE_PCREL_IMM26BY2) + || (ELF32_R_TYPE (rel->r_info) + == R_CKCORE_PCREL_IMM11BY2))) + break; + + /* If this is a global symbol, we count the number of + relocations we need for this symbol. */ + if (h != NULL) + { + struct csky_elf_link_hash_entry *eh; + eh = (struct csky_elf_link_hash_entry *)h; + if ((ELF32_R_TYPE (rel->r_info) + == R_CKCORE_PCREL_JSR_IMM26BY2) + || (ELF32_R_TYPE (rel->r_info) + == R_CKCORE_PCREL_JSR_IMM11BY2)) + eh->jsri2bsr_refcount += 1; + head = &eh->dyn_relocs; + } + else + { + /* Track dynamic relocs needed for local syms too. + We really need local syms available to do this + easily. Oh well. */ + void **vpp; + asection *s; + Elf_Internal_Sym *loc_isym; + + loc_isym = bfd_sym_from_r_symndx (&htab->sym_cache, + abfd, r_symndx); + if (loc_isym == NULL) + return FALSE; + s = bfd_section_from_elf_index (abfd, loc_isym->st_shndx); + if (s == NULL) + s = sec; + vpp = &elf_section_data (s)->local_dynrel; + head = (struct elf_dyn_relocs **)vpp; + } + + p = *head; + if (p == NULL || p->sec != sec) + { + bfd_size_type amt = sizeof *p; + p = ((struct elf_dyn_relocs *) + bfd_alloc (htab->elf.dynobj, amt)); + if (p == NULL) + return FALSE; + p->next = *head; + *head = p; + p->sec = sec; + p->count = 0; + p->pc_count = 0; + } + + if (ELF32_R_TYPE (rel->r_info) == R_CKCORE_PCREL_IMM26BY2 + || ELF32_R_TYPE (rel->r_info) == R_CKCORE_PCREL_IMM11BY2) + p->pc_count += 1; + p->count += 1; + } + break; + + case R_CKCORE_PLT_IMM18BY4: + case R_CKCORE_PLT32: + /* This symbol requires a procedure linkage table entry. We + actually build the entry in adjust_dynamic_symbol, + because this might be a case of linking PIC code which is + never referenced by a dynamic object, in which case we + don't need to generate a procedure linkage table entry + after all. */ + + /* If this is a local symbol, we resolve it directly without + creating a procedure linkage table entry. */ + if (h == NULL) + continue; + if (ELF32_R_TYPE (rel->r_info) == R_CKCORE_PLT_IMM18BY4) + check_got_overflow = 1; + + h->needs_plt = 1; + h->plt.refcount += 1; + h->got.refcount += 1; + ((struct csky_elf_link_hash_entry *)h)->plt_refcount += 1; + break; + + case R_CKCORE_GOT12: + case R_CKCORE_PLT12: + case R_CKCORE_GOT32: + case R_CKCORE_GOT_HI16: + case R_CKCORE_GOT_LO16: + case R_CKCORE_PLT_HI16: + case R_CKCORE_PLT_LO16: + case R_CKCORE_GOT_IMM18BY4: + case R_CKCORE_TLS_IE32: + case R_CKCORE_TLS_GD32: + { + int tls_type, old_tls_type; + + if (h != NULL + && bfd_link_executable (info) + && r_type == R_CKCORE_GOT_IMM18BY4 + && (sec->flags & SEC_ALLOC) != 0 + && (sec->flags & SEC_READONLY)) + /* If this reloc is in a read-only section, we might + need a copy reloc. We can't check reliably at this + stage whether the section is read-only, as input + sections have not yet been mapped to output sections. + Tentatively set the flag for now, and correct in + adjust_dynamic_symbol. */ + h->non_got_ref = 1; + + switch (ELF32_R_TYPE (rel->r_info)) + { + case R_CKCORE_TLS_IE32: + tls_type = GOT_TLS_IE; + break; + case R_CKCORE_TLS_GD32: + tls_type = GOT_TLS_GD; + break; + default: + tls_type = GOT_NORMAL; + break; + } + if (h != NULL) + { + if (ELF32_R_TYPE (rel->r_info) == R_CKCORE_GOT_IMM18BY4) + check_got_overflow = 1; + h->got.refcount += 1; + old_tls_type = csky_elf_hash_entry (h)->tls_type; + } + else + { + bfd_signed_vma *local_got_refcounts; + + /* This is a global offset table entry for a local symbol. */ + /* we can write a new function named + elf32_csky_allocate_local_sym_info() to replace + following code. */ + local_got_refcounts = elf_local_got_refcounts (abfd); + if (local_got_refcounts == NULL) + { + bfd_size_type size; + + size = symtab_hdr->sh_info; + size *= (sizeof (bfd_signed_vma) + sizeof (char)); + local_got_refcounts = ((bfd_signed_vma *) + bfd_zalloc (abfd, size)); + if (local_got_refcounts == NULL) + return FALSE; + elf_local_got_refcounts (abfd) = local_got_refcounts; + csky_elf_local_got_tls_type (abfd) + = (char *) (local_got_refcounts + symtab_hdr->sh_info); + } + local_got_refcounts[r_symndx] += 1; + old_tls_type = csky_elf_local_got_tls_type (abfd)[r_symndx]; + } + + /* We will already have issued an error message if there is a + TLS / non-TLS mismatch, based on the symbol type. We don't + support any linker relaxations. So just combine any TLS + types needed. */ + if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL + && tls_type != GOT_NORMAL) + tls_type |= old_tls_type; + + if (old_tls_type != tls_type) + { + if (h != NULL) + csky_elf_hash_entry (h)->tls_type = tls_type; + else + csky_elf_local_got_tls_type (abfd)[r_symndx] = tls_type; + } + } + /* Fall through. */ + + case R_CKCORE_TLS_LDM32: + if (ELF32_R_TYPE (rel->r_info) == R_CKCORE_TLS_LDM32) + htab->tls_ldm_got.refcount++; + /* Fall through. */ + + case R_CKCORE_GOTOFF: + case R_CKCORE_GOTPC: + case R_CKCORE_GOTOFF_HI16: + case R_CKCORE_GOTOFF_LO16: + case R_CKCORE_GOTPC_HI16: + case R_CKCORE_GOTPC_LO16: + case R_CKCORE_GOTOFF_IMM18: + if (htab->elf.sgot == NULL) + { + if (htab->elf.dynobj == NULL) + htab->elf.dynobj = abfd; + if (!_bfd_elf_create_got_section (htab->elf.dynobj, info)) + return FALSE; + } + break; + + /* This relocation describes the C++ object vtable hierarchy. + Reconstruct it for later use during GC. */ + case R_CKCORE_GNU_VTINHERIT: + if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset)) + return FALSE; + break; + + /* This relocation describes which C++ vtable entries are actually + used. Record for later use during GC. */ + case R_CKCORE_GNU_VTENTRY: + BFD_ASSERT (h != NULL); + if (h != NULL + && !bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_addend)) + return FALSE; + break; + } + } + + return TRUE; +} + +static const struct bfd_elf_special_section csky_elf_special_sections[]= +{ + { STRING_COMMA_LEN (".ctors"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, + { STRING_COMMA_LEN (".dtors"), -2, SHT_PROGBITS, SHF_ALLOC + SHF_WRITE }, + { NULL, 0, 0, 0, 0 } +}; + +/* Function to keep CSKY specific flags in the ELF header. */ + +static bfd_boolean +csky_elf_set_private_flags (bfd * abfd, flagword flags) +{ + BFD_ASSERT (! elf_flags_init (abfd) + || elf_elfheader (abfd)->e_flags == flags); + + elf_elfheader (abfd)->e_flags = flags; + elf_flags_init (abfd) = TRUE; + return TRUE; +} + +static csky_arch_for_merge * +csky_find_arch_with_eflag (const unsigned long arch_eflag) +{ + csky_arch_for_merge *csky_arch = NULL; + + for (csky_arch = csky_archs; csky_arch->name != NULL; csky_arch++) + if (csky_arch->arch_eflag == arch_eflag) + break; + if (csky_arch == NULL) + { + _bfd_error_handler (_("warning: unrecognized arch eflag '%#lx'"), + arch_eflag); + bfd_set_error (bfd_error_wrong_format); + } + return csky_arch; +} + +/* Merge backend specific data from an object file to the output + object file when linking. */ + +static bfd_boolean +csky_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info) +{ + bfd *obfd = info->output_bfd; + flagword old_flags; + flagword new_flags; + csky_arch_for_merge *old_arch = NULL; + csky_arch_for_merge *new_arch = NULL; + + /* Check if we have the same endianness. */ + if (! _bfd_generic_verify_endian_match (ibfd, info)) + return FALSE; + + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour + || bfd_get_flavour (obfd) != bfd_target_elf_flavour) + return TRUE; + + new_flags = elf_elfheader (ibfd)->e_flags; + old_flags = elf_elfheader (obfd)->e_flags; + + if (! elf_flags_init (obfd)) + { + /* First call, no flags set. */ + elf_flags_init (obfd) = TRUE; + elf_elfheader (obfd)->e_flags = new_flags; + } + else if (new_flags == old_flags) + /* Do nothing. */ + ; + else if (new_flags == 0 || old_flags == 0) + /* When one flag is 0, assign the other one's flag. */ + elf_elfheader (obfd)->e_flags = new_flags | old_flags; + else + { + flagword newest_flag = 0; + + if ((new_flags & CSKY_ARCH_MASK) != 0 + && (old_flags & CSKY_ARCH_MASK) != 0) + { + new_arch = csky_find_arch_with_eflag (new_flags & CSKY_ARCH_MASK); + old_arch = csky_find_arch_with_eflag (old_flags & CSKY_ARCH_MASK); + /* Collect flags like e, f, g. */ + newest_flag = (old_flags & (~CSKY_ARCH_MASK)) + | (new_flags & (~CSKY_ARCH_MASK)); + if (new_arch != NULL && old_arch != NULL) + { + if (new_arch->class != old_arch->class) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%pB: machine flag conflict with target"), ibfd); + bfd_set_error (bfd_error_wrong_format); + return FALSE; + } + else if (new_arch->class_level != old_arch->class_level) + { + csky_arch_for_merge *newest_arch + = (new_arch->class_level > old_arch->class_level + ? new_arch : old_arch); + if (new_arch->do_warning || old_arch->do_warning) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("warning: file %pB's arch flag ck%s conflicts with " + "target ck%s, using ck%s"), + ibfd, new_arch->name, old_arch->name, + newest_arch->name); + bfd_set_error (bfd_error_wrong_format); + } + + newest_flag |= newest_arch->arch_eflag; + } + else + newest_flag |= ((new_flags & (CSKY_ARCH_MASK | CSKY_ABI_MASK)) + | (old_flags + & (CSKY_ARCH_MASK | CSKY_ABI_MASK))); + } + else + newest_flag |= ((new_flags & (CSKY_ARCH_MASK | CSKY_ABI_MASK)) + | (old_flags & (CSKY_ARCH_MASK | CSKY_ABI_MASK))); + } + else + newest_flag |= ((new_flags & (CSKY_ARCH_MASK | CSKY_ABI_MASK)) + | (old_flags & (CSKY_ARCH_MASK | CSKY_ABI_MASK))); + + elf_elfheader (obfd)->e_flags = newest_flag; + } + return TRUE; +} + +/* Ignore the discarded relocs in special sections in link time. */ + +static bfd_boolean +csky_elf_ignore_discarded_relocs (asection *sec) +{ + if (strcmp (sec->name, ".csky_stack_size") == 0) + return TRUE; + return FALSE; +} + +/* .csky_stack_size are not referenced directly. This pass marks all of + them as required. */ + +static bfd_boolean +elf32_csky_gc_mark_extra_sections (struct bfd_link_info *info, + elf_gc_mark_hook_fn gc_mark_hook ATTRIBUTE_UNUSED) +{ + bfd *sub; + + _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook); + + for (sub = info->input_bfds; sub != NULL; sub = sub->link.next) + { + asection *o; + + for (o = sub->sections; o != NULL; o = o->next) + if (strcmp (o->name, ".csky_stack_size") == 0) + o->gc_mark = 1; + } + + return TRUE; +} + +/* The linker repeatedly calls this function for each input section, + in the order that input sections are linked into output sections. + Build lists of input sections to determine groupings between which + we may insert linker stubs. */ + +void +elf32_csky_next_input_section (struct bfd_link_info *info, + asection *isec) +{ + struct csky_elf_link_hash_table *htab = csky_elf_hash_table (info); + if (htab == NULL) + return; + if (isec->output_section->index <= htab->top_index) + { + asection **list = htab->input_list + isec->output_section->index; + + if (*list != bfd_abs_section_ptr) + { + /* Steal the link_sec pointer for our list. */ +#define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec) + /* This happens to make the list in reverse order, + which we reverse later in group_sections. */ + PREV_SEC (isec) = *list; + *list = isec; + } + } +} + +/* See whether we can group stub sections together. Grouping stub + sections may result in fewer stubs. More importantly, we need to + put all .init* and .fini* stubs at the end of the .init or + .fini output sections respectively, because glibc splits the + _init and _fini functions into multiple parts. Putting a stub in + the middle of a function is not a good idea. */ + +static void +group_sections (struct csky_elf_link_hash_table *htab, + bfd_size_type stub_group_size, + bfd_boolean stubs_always_after_branch) +{ + asection **list = htab->input_list; + + do + { + asection *tail = *list; + asection *head; + + if (tail == bfd_abs_section_ptr) + continue; + + /* Reverse the list: we must avoid placing stubs at the + beginning of the section because the beginning of the text + section may be required for an interrupt vector in bare metal + code. */ +#define NEXT_SEC PREV_SEC + head = NULL; + while (tail != NULL) + { + /* Pop from tail. */ + asection *item = tail; + tail = PREV_SEC (item); + + /* Push on head. */ + NEXT_SEC (item) = head; + head = item; + } + + while (head != NULL) + { + asection *curr; + asection *next; + bfd_vma stub_group_start = head->output_offset; + bfd_vma end_of_next; + + curr = head; + while (NEXT_SEC (curr) != NULL) + { + next = NEXT_SEC (curr); + end_of_next = next->output_offset + next->size; + if (end_of_next - stub_group_start >= stub_group_size) + /* End of NEXT is too far from start, so stop. */ + break; + curr = next; + } + + /* OK, the size from the start to the start of CURR is less + * than stub_group_size and thus can be handled by one stub + * section. (Or the head section is itself larger than + * stub_group_size, in which case we may be toast.) + * We should really be keeping track of the total size of + * stubs added here, as stubs contribute to the final output + * section size. */ + do + { + next = NEXT_SEC (head); + /* Set up this stub group. */ + htab->stub_group[head->id].link_sec = curr; + } + while (head != curr && (head = next) != NULL); + + /* But wait, there's more! Input sections up to stub_group_size + * bytes after the stub section can be handled by it too. */ + if (!stubs_always_after_branch) + { + stub_group_start = curr->output_offset + curr->size; + + while (next != NULL) + { + end_of_next = next->output_offset + next->size; + if (end_of_next - stub_group_start >= stub_group_size) + /* End of NEXT is too far from stubs, so stop. */ + break; + /* Add NEXT to the stub group. */ + head = next; + next = NEXT_SEC (head); + htab->stub_group[head->id].link_sec = curr; + } + } + head = next; + } + } + while (list++ != htab->input_list + htab->top_index); + + free (htab->input_list); +#undef PREV_SEC +#undef NEXT_SEC +} + +/* If the symbol referenced by bsr is defined in shared object file, + or it is a weak symbol and we aim to create shared object file, + we must create a stub for this bsr. */ + +static bfd_boolean +sym_must_create_stub (struct elf_link_hash_entry *h, + struct bfd_link_info *info) +{ + if (h != NULL + && ((h->def_dynamic && !h->def_regular) + || (bfd_link_pic (info) && h->root.type == bfd_link_hash_defweak))) + return TRUE; + else + return FALSE; +} + +/* Calculate the template, template size and instruction size for a stub. + Return value is the instruction size. */ + +static unsigned int +find_stub_size_and_template (enum elf32_csky_stub_type stub_type, + const insn_sequence **stub_template, + int *stub_template_size) +{ + const insn_sequence *template_sequence = NULL; + int template_size = 0; + int i; + unsigned int size; + + template_sequence = stub_definitions[stub_type].template_sequence; + template_size = stub_definitions[stub_type].template_size; + + size = 0; + for (i = 0; i < template_size; i++) + { + switch (template_sequence[i].type) + { + case INSN16: + size += 2; + break; + + case INSN32: + case DATA_TYPE: + size += 4; + break; + + default: + BFD_FAIL (); + return FALSE; + } + } + + if (stub_template) + *stub_template = template_sequence; + if (stub_template_size) + *stub_template_size = template_size; + + return size; +} + +/* As above, but don't actually build the stub. Just bump offset so + we know stub section sizes. */ + +static bfd_boolean +csky_size_one_stub (struct bfd_hash_entry *gen_entry, + void * in_arg ATTRIBUTE_UNUSED) +{ + struct elf32_csky_stub_hash_entry *stub_entry; + const insn_sequence *template_sequence = NULL; + int template_size = 0; + int size = 0; + + /* Massage our args to the form they really have. */ + stub_entry = (struct elf32_csky_stub_hash_entry *) gen_entry; + + BFD_ASSERT (stub_entry->stub_type > csky_stub_none + && stub_entry->stub_type < ARRAY_SIZE (stub_definitions)); + size = find_stub_size_and_template (stub_entry->stub_type, + &template_sequence, &template_size); + stub_entry->stub_size = size; + stub_entry->stub_template = template_sequence; + stub_entry->stub_template_size = template_size; + + size = (size + 7) & ~7; + stub_entry->stub_sec->size += size; + return TRUE; +} + +/* Add a new stub entry to the stub hash. Not all fields of the new + stub entry are initialised. */ + +static struct elf32_csky_stub_hash_entry * +elf32_csky_add_stub (const char *stub_name, + asection *section, + struct csky_elf_link_hash_table *htab) +{ + asection *link_sec; + asection *stub_sec; + struct elf32_csky_stub_hash_entry *stub_entry; + + stub_sec = elf32_csky_create_or_find_stub_sec (&link_sec, section, htab); + if (stub_sec == NULL) + return NULL; + + /* Enter this entry into the linker stub hash table. */ + stub_entry = csky_stub_hash_lookup (&htab->stub_hash_table, stub_name, + TRUE, FALSE); + if (stub_entry == NULL) + { + _bfd_error_handler (_("%pB: cannot create stub entry %s"), + section->owner, stub_name); + return NULL; + } + + stub_entry->stub_sec = stub_sec; + stub_entry->stub_offset = 0; + stub_entry->id_sec = link_sec; + + return stub_entry; +} + +/* Determine and set the size of the stub section for a final link. + The basic idea here is to examine all the relocations looking for + PC-relative calls to a target that is unreachable with a "bsr" + instruction. */ + +bfd_boolean +elf32_csky_size_stubs (bfd *output_bfd, + bfd *stub_bfd, + struct bfd_link_info *info, + bfd_signed_vma group_size, + asection *(*add_stub_section) (const char*, asection*), + void (*layout_sections_again) (void)) +{ + bfd_size_type stub_group_size; + bfd_boolean stubs_always_after_branch; + struct csky_elf_link_hash_table *htab = csky_elf_hash_table (info); + + if (htab == NULL) + return FALSE; + + /* Propagate mach to stub bfd, because it may not have been + finalized when we created stub_bfd. */ + bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd), + bfd_get_mach (output_bfd)); + + /* Stash our params away. */ + htab->stub_bfd = stub_bfd; + htab->add_stub_section = add_stub_section; + htab->layout_sections_again = layout_sections_again; + stubs_always_after_branch = group_size < 0; + + if (group_size < 0) + stub_group_size = -group_size; + else + stub_group_size = group_size; + + if (stub_group_size == 1) + /* The 'bsr' range in abiv2 is +-64MB has to be used as the + default maximum size. + This value is 128K less than that, which allows for 131072 + byte stubs. If we exceed that, then we will fail to link. + The user will have to relink with an explicit group size + option. */ + stub_group_size = 66977792; + + group_sections (htab, stub_group_size, stubs_always_after_branch); + + while (1) + { + bfd *input_bfd; + unsigned int bfd_indx; + asection *stub_sec; + bfd_boolean stub_changed = FALSE; + + for (input_bfd = info->input_bfds, bfd_indx = 0; + input_bfd != NULL; + input_bfd = input_bfd->link.next, bfd_indx++) + { + Elf_Internal_Shdr *symtab_hdr; + asection *section; + Elf_Internal_Sym *local_syms = NULL; + + /* We'll need the symbol table in a second. */ + symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr; + if (symtab_hdr->sh_info == 0) + continue; + + /* Walk over each section attached to the input bfd. */ + for (section = input_bfd->sections; + section != NULL; + section = section->next) + { + Elf_Internal_Rela *internal_relocs, *irelaend, *irela; + + /* If there aren't any relocs, then there's nothing more + * to do. */ + if ((section->flags & SEC_RELOC) == 0 + || section->reloc_count == 0 + || (section->flags & SEC_CODE) == 0) + continue; + + /* If this section is a link-once section that will be + discarded, then don't create any stubs. */ + if (section->output_section == NULL + || section->output_section->owner != output_bfd) + continue; + + /* Get the relocs. */ + internal_relocs = _bfd_elf_link_read_relocs (input_bfd, + section, + NULL, NULL, + info->keep_memory); + + if (internal_relocs == NULL) + goto error_ret_free_local; + + /* Now examine each relocation. */ + irela = internal_relocs; + irelaend = irela + section->reloc_count; + for (; irela < irelaend; irela++) + { + unsigned int r_type, r_indx; + enum elf32_csky_stub_type stub_type; + struct elf32_csky_stub_hash_entry *stub_entry; + asection *sym_sec; + bfd_vma sym_value; + bfd_vma destination; + struct csky_elf_link_hash_entry *hash; + const char *sym_name; + char *stub_name; + const asection *id_sec; + unsigned char st_type; + + r_type = ELF32_R_TYPE (irela->r_info); + r_indx = ELF32_R_SYM (irela->r_info); + if (r_type >= (unsigned int) R_CKCORE_MAX) + { + bfd_set_error (bfd_error_bad_value); +error_ret_free_internal: + if (elf_section_data (section)->relocs == NULL) + free (internal_relocs); + goto error_ret_free_local; + } + + /* Only look for stubs on branch instructions. */ + if (r_type != (unsigned int) R_CKCORE_PCREL_IMM26BY2) + continue; + /* Now determine the call target, its name, value, + section. */ + sym_sec = NULL; + sym_value = 0; + destination = 0; + hash = NULL; + sym_name = NULL; + if (r_indx < symtab_hdr->sh_info) + { + /* It's a local symbol. */ + Elf_Internal_Sym *sym; + Elf_Internal_Shdr *hdr; + if (local_syms == NULL) + local_syms = + (Elf_Internal_Sym *) symtab_hdr->contents; + if (local_syms == NULL) + { + local_syms = + bfd_elf_get_elf_syms (input_bfd, + symtab_hdr, + symtab_hdr->sh_info, + 0, NULL, NULL, NULL); + if (local_syms == NULL) + goto error_ret_free_internal; + } + sym = local_syms + r_indx; + hdr = elf_elfsections (input_bfd)[sym->st_shndx]; + sym_sec = hdr->bfd_section; + if (!sym_sec) + /* This is an undefined symbol. It can never + be resolved. */ + continue; + if (ELF_ST_TYPE (sym->st_info) != STT_SECTION) + sym_value = sym->st_value; + destination = (sym_value + irela->r_addend + + sym_sec->output_offset + + sym_sec->output_section->vma); + st_type = ELF_ST_TYPE (sym->st_info); + sym_name = + bfd_elf_string_from_elf_section (input_bfd, + symtab_hdr->sh_link, + sym->st_name); + } + else + { + /* It's an external symbol. */ + int e_indx; + e_indx = r_indx - symtab_hdr->sh_info; + hash = ((struct csky_elf_link_hash_entry *) + elf_sym_hashes (input_bfd)[e_indx]); + + while (hash->elf.root.type == bfd_link_hash_indirect + || hash->elf.root.type == bfd_link_hash_warning) + hash = ((struct csky_elf_link_hash_entry *) + hash->elf.root.u.i.link); + if (hash->elf.root.type == bfd_link_hash_defined + || hash->elf.root.type == bfd_link_hash_defweak) + { + sym_sec = hash->elf.root.u.def.section; + sym_value = hash->elf.root.u.def.value; + + struct csky_elf_link_hash_table *globals = + csky_elf_hash_table (info); + /* FIXME For a destination in a shared library. */ + if (globals->elf.splt != NULL && hash != NULL + && hash->elf.plt.offset != (bfd_vma) -1) + continue; + else if (sym_sec->output_section != NULL) + destination = (sym_value + irela->r_addend + + sym_sec->output_offset + + sym_sec->output_section->vma); + } + else if (hash->elf.root.type == bfd_link_hash_undefined + || (hash->elf.root.type + == bfd_link_hash_undefweak)) + /* FIXME For a destination in a shared library. */ + continue; + else + { + bfd_set_error (bfd_error_bad_value); + goto error_ret_free_internal; + } + st_type = ELF_ST_TYPE (hash->elf.type); + sym_name = hash->elf.root.root.string; + } + do + { + /* Determine what (if any) linker stub is needed. */ + stub_type = csky_type_of_stub (info, section, irela, + st_type, hash, + destination, sym_sec, + input_bfd, sym_name); + if (stub_type == csky_stub_none) + break; + + /* Support for grouping stub sections. */ + id_sec = htab->stub_group[section->id].link_sec; + + /* Get the name of this stub. */ + stub_name = elf32_csky_stub_name (id_sec, sym_sec, hash, + irela); + if (!stub_name) + goto error_ret_free_internal; + /* We've either created a stub for this reloc already, + or we are about to. */ + stub_entry + = csky_stub_hash_lookup (&htab->stub_hash_table, + stub_name, + FALSE, FALSE); + if (stub_entry != NULL) + { + /* The proper stub has already been created. */ + free (stub_name); + stub_entry->target_value = sym_value; + break; + } + stub_entry = elf32_csky_add_stub (stub_name, section, + htab); + if (stub_entry == NULL) + { + free (stub_name); + goto error_ret_free_internal; + } + stub_entry->target_value = sym_value; + stub_entry->target_section = sym_sec; + stub_entry->stub_type = stub_type; + stub_entry->h = hash; + stub_entry->st_type = st_type; + + if (sym_name == NULL) + sym_name = "unnamed"; + stub_entry->output_name = + bfd_alloc (htab->stub_bfd, + (sizeof (STUB_ENTRY_NAME) + + strlen (sym_name))); + if (stub_entry->output_name == NULL) + { + free (stub_name); + goto error_ret_free_internal; + } + sprintf (stub_entry->output_name, STUB_ENTRY_NAME, + sym_name); + stub_changed = TRUE; + } + while (0); + } + /* We're done with the internal relocs, free them. */ + if (elf_section_data (section)->relocs == NULL) + free (internal_relocs); + } + } + if (!stub_changed) + break; + /* OK, we've added some stubs. Find out the new size of the + stub sections. */ + for (stub_sec = htab->stub_bfd->sections; + stub_sec != NULL; + stub_sec = stub_sec->next) + { + /* Ignore non-stub sections. */ + if (!strstr (stub_sec->name, STUB_SUFFIX)) + continue; + stub_sec->size = 0; + } + bfd_hash_traverse (&htab->stub_hash_table, csky_size_one_stub, htab); + /* Ask the linker to do its stuff. */ + (*htab->layout_sections_again) (); + } + + return TRUE; +error_ret_free_local: + return FALSE; +} + +static bfd_boolean +csky_build_one_stub (struct bfd_hash_entry *gen_entry, + void * in_arg) +{ +#define MAXRELOCS 2 + struct elf32_csky_stub_hash_entry *stub_entry; + struct bfd_link_info *info; + asection *stub_sec; + bfd *stub_bfd; + bfd_byte *loc; + bfd_vma sym_value; + int template_size; + int size; + const insn_sequence *template_sequence; + int i; + struct csky_elf_link_hash_table * globals; + int stub_reloc_idx[MAXRELOCS] = {-1, -1}; + int stub_reloc_offset[MAXRELOCS] = {0, 0}; + int nrelocs = 0; + struct elf_link_hash_entry *h = NULL; + + /* Massage our args to the form they really have. */ + stub_entry = (struct elf32_csky_stub_hash_entry *)gen_entry; + info = (struct bfd_link_info *) in_arg; + + globals = csky_elf_hash_table (info); + if (globals == NULL) + return FALSE; + stub_sec = stub_entry->stub_sec; + + /* Make a note of the offset within the stubs for this entry. */ + stub_entry->stub_offset = stub_sec->size; + loc = stub_sec->contents + stub_entry->stub_offset; + + stub_bfd = stub_sec->owner; + + /* This is the address of the stub destination. */ + h = &stub_entry->h->elf; + if (sym_must_create_stub (h, info) + && !(bfd_link_pic (info) + && h->root.type == bfd_link_hash_defweak + && h->def_regular + && !h->def_dynamic)) + sym_value = 0; + else + sym_value = (stub_entry->target_value + + stub_entry->target_section->output_offset + + stub_entry->target_section->output_section->vma); + + template_sequence = stub_entry->stub_template; + template_size = stub_entry->stub_template_size; + + size = 0; + for (i = 0; i < template_size; i++) + switch (template_sequence[i].type) + { + case INSN16: + bfd_put_16 (stub_bfd, (bfd_vma) template_sequence[i].data, + loc + size); + size += 2; + break; + case INSN32: + csky_put_insn_32 (stub_bfd, (bfd_vma) template_sequence[i].data, + loc + size); + size += 4; + break; + case DATA_TYPE: + bfd_put_32 (stub_bfd, (bfd_vma) template_sequence[i].data, + loc + size); + stub_reloc_idx[nrelocs] = i; + stub_reloc_offset[nrelocs++] = size; + size += 4; + break; + default: + BFD_FAIL (); + return FALSE; + } + stub_sec->size += size; + + /* Stub size has already been computed in csky_size_one_stub. Check + consistency. */ + BFD_ASSERT (size == stub_entry->stub_size); + + /* Assume there is at least one and at most MAXRELOCS entries to relocate + in each stub. */ + BFD_ASSERT (nrelocs != 0 && nrelocs <= MAXRELOCS); + + for (i = 0; i < nrelocs; i++) + { + if (sym_must_create_stub (h, info)) + { + Elf_Internal_Rela outrel; + asection * sreloc = globals->elf.srelgot; + + outrel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i]; + outrel.r_info = + ELF32_R_INFO (h->dynindx, + template_sequence[stub_reloc_idx[i]].r_type); + outrel.r_addend = template_sequence[stub_reloc_idx[i]].reloc_addend; + + loc = sreloc->contents; + loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela); + + if (loc != NULL) + bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc); + } + _bfd_final_link_relocate (elf32_csky_howto_from_type + (template_sequence[stub_reloc_idx[i]].r_type), + stub_bfd, stub_sec, stub_sec->contents, + stub_entry->stub_offset + stub_reloc_offset[i], + sym_value + stub_entry->target_addend, + template_sequence[stub_reloc_idx[i]].reloc_addend); + } + + return TRUE; +#undef MAXRELOCS +} + +/* Build all the stubs associated with the current output file. The + stubs are kept in a hash table attached to the main linker hash + table. We also set up the .plt entries for statically linked PIC + functions here. This function is called via arm_elf_finish in the + linker. */ + +bfd_boolean +elf32_csky_build_stubs (struct bfd_link_info *info) +{ + asection *stub_sec; + struct bfd_hash_table *table; + struct csky_elf_link_hash_table *htab; + + htab = csky_elf_hash_table (info); + + if (htab == NULL) + return FALSE; + + for (stub_sec = htab->stub_bfd->sections; + stub_sec != NULL; + stub_sec = stub_sec->next) + { + bfd_size_type size; + + /* Ignore non-stub sections. */ + if (!strstr (stub_sec->name, STUB_SUFFIX)) + continue; + + /* Allocate memory to hold the linker stubs. */ + size = stub_sec->size; + stub_sec->contents = bfd_zalloc (htab->stub_bfd, size); + if (stub_sec->contents == NULL && size != 0) + return FALSE; + stub_sec->size = 0; + } + + /* Build the stubs as directed by the stub hash table. */ + table = &htab->stub_hash_table; + bfd_hash_traverse (table, csky_build_one_stub, info); + + return TRUE; +} + +/* Set up various things so that we can make a list of input sections + for each output section included in the link. Returns -1 on error, + 0 when no stubs will be needed, and 1 on success. */ + +int +elf32_csky_setup_section_lists (bfd *output_bfd, + struct bfd_link_info *info) +{ + bfd *input_bfd; + unsigned int bfd_count; + unsigned int top_id, top_index; + asection *section; + asection **input_list, **list; + bfd_size_type amt; + struct csky_elf_link_hash_table *htab = csky_elf_hash_table (info); + + if (!htab) + return 0; + if (! is_elf_hash_table (htab)) + return 0; + + /* Count the number of input BFDs and find the top input section id. */ + for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0; + input_bfd != NULL; + input_bfd = input_bfd->link.next) + { + bfd_count += 1; + for (section = input_bfd->sections; + section != NULL; + section = section->next) + if (top_id < section->id) + top_id = section->id; + } + htab->bfd_count = bfd_count; + amt = sizeof (struct map_stub) * (top_id + 1); + htab->stub_group = bfd_zmalloc (amt); + if (htab->stub_group == NULL) + return -1; + + /* We can't use output_bfd->section_count here to find the top output + section index as some sections may have been removed, and + _bfd_strip_section_from_output doesn't renumber the indices. */ + for (section = output_bfd->sections, top_index = 0; + section != NULL; + section = section->next) + if (top_index < section->index) + top_index = section->index; + htab->top_index = top_index; + amt = sizeof (asection *) * (top_index + 1); + input_list = bfd_malloc (amt); + htab->input_list = input_list; + if (input_list == NULL) + return -1; + /* For sections we aren't interested in, mark their entries with a + value we can check later. */ + list = input_list + top_index; + do + *list = bfd_abs_section_ptr; + while (list-- != input_list); + for (section = output_bfd->sections; + section != NULL; + section = section->next) + if ((section->flags & SEC_CODE) != 0) + input_list[section->index] = NULL; + + return 1; +} + +static bfd_reloc_status_type +csky_relocate_contents (reloc_howto_type *howto, + bfd *input_bfd, + long relocation, + bfd_byte *location) +{ + int size; + bfd_vma x = 0; + bfd_reloc_status_type flag; + unsigned int rightshift = howto->rightshift; + unsigned int bitpos = howto->bitpos; + + /* If the size is negative, negate RELOCATION. This isn't very + general. */ + if (howto->size < 0) + relocation = -relocation; + + /* FIXME: these macros should be defined at file head or head file head. */ +#define CSKY_INSN_ADDI_TO_SUBI 0x04000000 +#define CSKY_INSN_MOV_RTB 0xc41d4820 // mov32 rx, r29, 0 +#define CSKY_INSN_MOV_RDB 0xc41c4820 // mov32 rx, r28, 0 +#define CSKY_INSN_GET_ADDI_RZ(x) (((x) & 0x03e00000) >> 21) +#define CSKY_INSN_SET_MOV_RZ(x) ((x) & 0x0000001f) +#define CSKY_INSN_JSRI_TO_LRW 0xea9a0000 +#define CSKY_INSN_JSR_R26 0xe8fa0000 + + /* Get the value we are going to relocate. */ + size = bfd_get_reloc_size (howto); + switch (size) + { + default: + case 0: + abort (); + case 1: + x = bfd_get_8 (input_bfd, location); + break; + case 2: + x = bfd_get_16 (input_bfd, location); + break; + case 4: + if (need_reverse_bits) + { + x = csky_get_insn_32 (input_bfd, location); + + if (R_CKCORE_DOFFSET_LO16 == howto->type) + { + if ((signed) relocation < 0) + { + x |= CSKY_INSN_ADDI_TO_SUBI; + relocation = -relocation; + } + else if (0 == relocation) + x = (CSKY_INSN_MOV_RDB | + CSKY_INSN_SET_MOV_RZ (CSKY_INSN_GET_ADDI_RZ (x))); + } + else if (R_CKCORE_TOFFSET_LO16 == howto->type) + { + if ((signed) relocation < 0) + { + x |= CSKY_INSN_ADDI_TO_SUBI; + relocation = -relocation; + } + else if (0 == relocation) + x = (CSKY_INSN_MOV_RTB | + CSKY_INSN_SET_MOV_RZ (CSKY_INSN_GET_ADDI_RZ (x))); + } + } + else + x = bfd_get_32 (input_bfd, location); + break; + } + /* Check for overflow. FIXME: We may drop bits during the addition + which we don't check for. We must either check at every single + operation, which would be tedious, or we must do the computations + in a type larger than bfd_vma, which would be inefficient. */ + flag = bfd_reloc_ok; + if (howto->complain_on_overflow != complain_overflow_dont) + { + int addrmask; + int fieldmask; + int signmask; + int ss; + int a; + int b; + int sum; + /* Get the values to be added together. For signed and unsigned + relocations, we assume that all values should be truncated to + the size of an address. For bitfields, all the bits matter. + See also bfd_check_overflow. */ +#define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1) + fieldmask = N_ONES (howto->bitsize); + signmask = ~fieldmask; + addrmask = N_ONES (bfd_arch_bits_per_address (input_bfd)) | fieldmask; + a = (relocation & addrmask) >> rightshift; + if (read_content_substitute) + x = read_content_substitute; + b = (x & howto->src_mask & addrmask) >> bitpos; + + switch (howto->complain_on_overflow) + { + case complain_overflow_signed: + /* If any sign bits are set, all sign bits must be set. + That is, A must be a valid negative address after + shifting. */ + signmask = ~(fieldmask >> 1); + /* Fall through. */ + + case complain_overflow_bitfield: + /* Much like the signed check, but for a field one bit + wider. We allow a bitfield to represent numbers in the + range -2**n to 2**n-1, where n is the number of bits in the + field. Note that when bfd_vma is 32 bits, a 32-bit reloc + can't overflow, which is exactly what we want. */ + ss = a & signmask; + if (ss != 0 && ss != ((addrmask >> rightshift) & signmask)) + flag = bfd_reloc_overflow; + /* We only need this next bit of code if the sign bit of B + is below the sign bit of A. This would only happen if + SRC_MASK had fewer bits than BITSIZE. Note that if + SRC_MASK has more bits than BITSIZE, we can get into + trouble; we would need to verify that B is in range, as + we do for A above. */ + ss = ((~howto->src_mask) >> 1) & howto->src_mask; + ss >>= bitpos; + + /* Set all the bits above the sign bit. */ + b = (b ^ ss) - ss; + + /* Now we can do the addition. */ + sum = a + b; + + /* See if the result has the correct sign. Bits above the + sign bit are junk now; ignore them. If the sum is + positive, make sure we did not have all negative inputs; + if the sum is negative, make sure we did not have all + positive inputs. The test below looks only at the sign + bits, and it really just + SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM) + + We mask with addrmask here to explicitly allow an address + wrap-around. The Linux kernel relies on it, and it is + the only way to write assembler code which can run when + loaded at a location 0x80000000 away from the location at + which it is linked. */ + + if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask) + flag = bfd_reloc_overflow; + break; + case complain_overflow_unsigned: + /* Checking for an unsigned overflow is relatively easy: + trim the addresses and add, and trim the result as well. + Overflow is normally indicated when the result does not + fit in the field. However, we also need to consider the + case when, e.g., fieldmask is 0x7fffffff or smaller, an + input is 0x80000000, and bfd_vma is only 32 bits; then we + will get sum == 0, but there is an overflow, since the + inputs did not fit in the field. Instead of doing a + separate test, we can check for this by or-ing in the + operands when testing for the sum overflowing its final + field. */ + sum = (a + b) & addrmask; + if ((a | b | sum) & signmask) + flag = bfd_reloc_overflow; + break; + default: + abort (); + } + + } + /* Put RELOCATION in the right bits. */ + relocation >>= (bfd_vma) rightshift; + + if ((howto->type == R_CKCORE_DOFFSET_LO16 + || howto->type == R_CKCORE_TOFFSET_LO16) + && relocation == 0) + /* Do nothing lsli32 rx, rz, 0. */ + ; + else + { + /* Fir V1, all this relocation must be x -1. */ + if (howto->type == R_CKCORE_PCREL_IMM11BY2 + || howto->type == R_CKCORE_PCREL_JSR_IMM11BY2 + || howto->type == R_CKCORE_DOFFSET_LO16 + || howto->type == R_CKCORE_TOFFSET_LO16) + relocation -= 1; + else if (howto->type == R_CKCORE_PCREL_IMM7BY4) + relocation = (relocation & 0x1f) + ((relocation << 3) & 0x300); + else if (howto->type == R_CKCORE_PCREL_FLRW_IMM8BY4) + relocation + = ((relocation << 4) & 0xf0) + ((relocation << 17) & 0x1e00000); + else if (howto->type == R_CKCORE_NOJSRI) + { + x = (x & howto->dst_mask) | CSKY_INSN_JSRI_TO_LRW; + relocation = 0; + csky_put_insn_32 (input_bfd, CSKY_INSN_JSR_R26, location + 4); + } + + relocation <<= (bfd_vma) bitpos; + /* Add RELOCATION to the right bits of X. */ + x = ((x & ~howto->dst_mask) + | (((x & howto->src_mask) + relocation) & howto->dst_mask)); + } + /* Put the relocated value back in the object file. */ + switch (size) + { + default: + abort (); + case 1: + bfd_put_8 (input_bfd, x, location); + break; + case 2: + bfd_put_16 (input_bfd, x, location); + break; + case 4: + if (need_reverse_bits) + csky_put_insn_32 (input_bfd, x, location); + else + bfd_put_32 (input_bfd, x, location); + break; + } + return flag; +} + +/* Look up an entry in the stub hash. Stub entries are cached because + creating the stub name takes a bit of time. */ + +static struct elf32_csky_stub_hash_entry * +elf32_csky_get_stub_entry (const asection *input_section, + const asection *sym_sec, + struct elf_link_hash_entry *hash, + const Elf_Internal_Rela *rel, + struct csky_elf_link_hash_table *htab) +{ + struct elf32_csky_stub_hash_entry *stub_entry; + struct csky_elf_link_hash_entry *h + = (struct csky_elf_link_hash_entry *) hash; + const asection *id_sec; + + if ((input_section->flags & SEC_CODE) == 0) + return NULL; + + /* If this input section is part of a group of sections sharing one + stub section, then use the id of the first section in the group. + Stub names need to include a section id, as there may well be + more than one stub used to reach say, printf, and we need to + distinguish between them. */ + id_sec = htab->stub_group[input_section->id].link_sec; + if (h != NULL && h->stub_cache != NULL + && h->stub_cache->h == h && h->stub_cache->id_sec == id_sec) + stub_entry = h->stub_cache; + else + { + char *stub_name; + stub_name = elf32_csky_stub_name (id_sec, sym_sec, h, rel); + if (stub_name == NULL) + return NULL; + stub_entry = csky_stub_hash_lookup (&htab->stub_hash_table, + stub_name, FALSE, FALSE); + if (h != NULL) + h->stub_cache = stub_entry; + free (stub_name); + } + + return stub_entry; +} + +static bfd_reloc_status_type +csky_final_link_relocate (reloc_howto_type *howto, + bfd *input_bfd, + asection *input_section, + bfd_byte *contents, + bfd_vma address, + bfd_vma value, + bfd_vma addend) +{ + bfd_vma relocation; + + /* Sanity check the address. */ + if (address > bfd_get_section_limit (input_bfd, input_section)) + return bfd_reloc_outofrange; + + /* This function assumes that we are dealing with a basic relocation + against a symbol. We want to compute the value of the symbol to + relocate to. This is just VALUE, the value of the symbol, + plus ADDEND, any addend associated with the reloc. */ + relocation = value + addend; + + /* If the relocation is PC relative, we want to set RELOCATION to + the distance between the symbol (currently in RELOCATION) and the + location we are relocating. Some targets (e.g., i386-aout) + arrange for the contents of the section to be the negative of the + offset of the location within the section; for such targets + pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF) + simply leave the contents of the section as zero; for such + targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not + need to subtract out the offset of the location within the + section (which is just ADDRESS). */ + if (howto->pc_relative) + { + relocation -= (input_section->output_section->vma + + input_section->output_offset); + if (howto->pcrel_offset) + relocation -= address; + } + + return csky_relocate_contents (howto, input_bfd, relocation, + contents + address); + +} + +/* Return the base VMA address which should be subtracted from real addresses + when resolving @dtpoff relocation. + This is PT_TLS segment p_vaddr. */ + +static bfd_vma +dtpoff_base (struct bfd_link_info *info) +{ + /* If tls_sec is NULL, we should have signalled an error already. */ + if (elf_hash_table (info)->tls_sec == NULL) + return 0; + return elf_hash_table (info)->tls_sec->vma; +} + +/* Return the relocation value for @tpoff relocation + if STT_TLS virtual address is ADDRESS. */ + +static bfd_vma +tpoff (struct bfd_link_info *info, bfd_vma address) +{ + struct elf_link_hash_table *htab = elf_hash_table (info); + bfd_vma base; + + /* If tls_sec is NULL, we should have signalled an error already. */ + if (htab->tls_sec == NULL) + return 0; + base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power); + return address - htab->tls_sec->vma + base; +} + +/* Relocate a csky section. */ + +static bfd_boolean +csky_elf_relocate_section (bfd * output_bfd, + struct bfd_link_info * info, + bfd * input_bfd, + asection * input_section, + bfd_byte * contents, + Elf_Internal_Rela * relocs, + Elf_Internal_Sym * local_syms, + asection ** local_sections) +{ + Elf_Internal_Shdr *symtab_hdr; + struct elf_link_hash_entry **sym_hashes; + Elf_Internal_Rela *rel; + Elf_Internal_Rela *relend; + const char *name; + bfd_boolean ret = TRUE; + struct csky_elf_link_hash_table * htab; + bfd_vma *local_got_offsets = elf_local_got_offsets (input_bfd); + + htab = csky_elf_hash_table (info); + if (htab == NULL) + return FALSE; + + symtab_hdr = & elf_symtab_hdr (input_bfd); + sym_hashes = elf_sym_hashes (input_bfd); + + rel = relocs; + relend = relocs + input_section->reloc_count; + for (; rel < relend; rel++) + { + enum elf_csky_reloc_type r_type + = (enum elf_csky_reloc_type) ELF32_R_TYPE (rel->r_info); + unsigned long r_symndx; + reloc_howto_type * howto; + Elf_Internal_Sym * sym; + asection * sec; + bfd_vma relocation; + bfd_vma off; + struct elf_link_hash_entry * h; + bfd_vma addend = (bfd_vma)rel->r_addend; + bfd_reloc_status_type r = bfd_reloc_ok; + bfd_boolean unresolved_reloc = FALSE; + int do_final_relocate = TRUE; + bfd_boolean relative_reloc = FALSE; + bfd_signed_vma disp; + + /* Ignore these relocation types: + R_CKCORE_GNU_VTINHERIT, R_CKCORE_GNU_VTENTRY. */ + if (r_type == R_CKCORE_GNU_VTINHERIT || r_type == R_CKCORE_GNU_VTENTRY) + continue; + + if ((unsigned) r_type >= (unsigned) R_CKCORE_MAX) + { + /* The r_type is error, not support it. */ + /* xgettext:c-format */ + _bfd_error_handler (_("%pB: unsupported relocation type: %#x"), + input_bfd, r_type); + bfd_set_error (bfd_error_bad_value); + ret = FALSE; + continue; + } + + howto = &csky_elf_howto_table[(int) r_type]; + + r_symndx = ELF32_R_SYM(rel->r_info); + h = NULL; + sym = NULL; + sec = NULL; + unresolved_reloc = FALSE; + + if (r_symndx < symtab_hdr->sh_info) + { + /* Get symbol table entry. */ + sym = local_syms + r_symndx; + sec = local_sections[r_symndx]; + relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel); + addend = (bfd_vma)rel->r_addend; + } + else + { + bfd_boolean warned, ignored; + + RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel, + r_symndx, symtab_hdr, sym_hashes, + h, sec, relocation, + unresolved_reloc, warned, ignored); + } + + if (sec != NULL && discarded_section (sec)) + { + /* For relocs against symbols from removed linkonce sections, + or sections discarded by a linker script, we just want the + section contents zeroed. Avoid any special processing. + And if the symbol is referenced in '.csky_stack_size' section, + set the address to SEC_DISCARDED(0xffffffff). */ +#if 0 + /* The .csky_stack_size section is just for callgraph. */ + if (strcmp (input_section->name, ".csky_stack_size") == 0) + { +/* FIXME: it should define in head file. */ +#define SEC_DISCARDED 0xffffffff + bfd_put_32 (input_bfd, SEC_DISCARDED, contents + rel->r_offset); + rel->r_info = 0; + rel->r_addend = 0; + continue; + } + else +#endif + RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section, + rel, 1, relend, howto, 0, + contents); + } + + if (bfd_link_relocatable (info)) + continue; + + read_content_substitute = 0; + + /* Final link. */ + disp = (relocation + + (bfd_signed_vma) addend + - input_section->output_section->vma + - input_section->output_offset + - rel->r_offset); +/* It is for ck8xx. */ +#define CSKY_INSN_BSR32 0xe0000000 +/* It is for ck5xx/ck6xx. */ +#define CSKY_INSN_BSR16 0xf800 +#define within_range(x, L) (-(1 << (L - 1)) < (x) && (x) < (1 << (L -1)) - 2) + switch (howto->type) + { + case R_CKCORE_PCREL_IMM18BY2: + /* When h is NULL, means the instruction written as + grs rx, imm32 + if the highest bit is set, prevent the high 32bits + turn to 0xffffffff when signed extern in 64bit + host machine. */ + if (h == NULL && (addend & 0x80000000)) + addend &= 0xffffffff; + break; + case R_CKCORE_GOT12: + case R_CKCORE_PLT12: + case R_CKCORE_GOT_HI16: + case R_CKCORE_GOT_LO16: + case R_CKCORE_PLT_HI16: + case R_CKCORE_PLT_LO16: + case R_CKCORE_GOT32: + case R_CKCORE_GOT_IMM18BY4: + /* Relocation is to the entry for this symbol in the global + offset table. */ + BFD_ASSERT (htab->elf.sgot != NULL); + if (h != NULL) + { + /* Global symbol is defined by other modules. */ + bfd_boolean dyn; + off = h->got.offset; + dyn = htab->elf.dynamic_sections_created; + if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, + bfd_link_pic (info), h) + || (bfd_link_pic (info) && SYMBOL_REFERENCES_LOCAL (info,h)) + || (ELF_ST_VISIBILITY(h->other) + && h->root.type == bfd_link_hash_undefweak)) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined + locally, or the symbol was forced to be local + because of a version file. We must initialize + this entry in the global offset table. Since the + offset must always be a multiple of 4, we use the + least significant bit to record whether we have + initialized it already. + When doing a dynamic link, we create a .rela.dyn + relocation entry to initialize the value. This + is done in the finish_dynamic_symbol routine. FIXME */ + if (off & 1) + off &= ~1; + else + { + bfd_put_32 (output_bfd, relocation, + htab->elf.sgot->contents + off); + h->got.offset |= 1; + +/* TRUE if relative relocation should be generated. GOT reference to + global symbol in PIC will lead to dynamic symbol. It becomes a + problem when "time" or "times" is defined as a variable in an + executable, clashing with functions of the same name in libc. If a + symbol isn't undefined weak symbol, don't make it dynamic in PIC and + generate relative relocation. */ +#define GENERATE_RELATIVE_RELOC_P(INFO, H) \ + ((H)->dynindx == -1 \ + && !(H)->forced_local \ + && (H)->root.type != bfd_link_hash_undefweak \ + && bfd_link_pic (INFO)) + + if (GENERATE_RELATIVE_RELOC_P (info, h)) + /* If this symbol isn't dynamic + in PIC, generate R_CKCORE_RELATIVE here. */ + relative_reloc = TRUE; + } + } + else + unresolved_reloc = FALSE; + } /* End if h != NULL. */ + else + { + BFD_ASSERT (local_got_offsets != NULL); + off = local_got_offsets[r_symndx]; + + /* The offset must always be a multiple of 4. We use + the least significant bit to record whether we have + already generated the necessary reloc. */ + if (off & 1) + off &= ~1; + else + { + bfd_put_32 (output_bfd, relocation, + htab->elf.sgot->contents + off); + local_got_offsets[r_symndx] |= 1; + if (bfd_link_pic (info)) + relative_reloc = TRUE; + } + } + if (relative_reloc) + { + asection *srelgot; + Elf_Internal_Rela outrel; + bfd_byte *loc; + + srelgot = htab->elf.srelgot; + BFD_ASSERT (srelgot != NULL); + + outrel.r_offset + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + off); + outrel.r_info = ELF32_R_INFO (0, R_CKCORE_RELATIVE); + outrel.r_addend = relocation; + loc = srelgot->contents; + loc += (srelgot->reloc_count++ * sizeof (Elf32_External_Rela)); + if (loc != NULL) + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + } + relocation = htab->elf.sgot->output_offset + off; + break; + + case R_CKCORE_GOTOFF_IMM18: + case R_CKCORE_GOTOFF: + case R_CKCORE_GOTOFF_HI16: + case R_CKCORE_GOTOFF_LO16: + /* Relocation is relative to the start of the global offset + table. */ + /* Note that sgot->output_offset is not involved in this + calculation. We always want the start of .got. If we + defined _GLOBAL_OFFSET_TABLE in a different way, as is + permitted by the ABI, we might have to change this + calculation. */ + relocation -= htab->elf.sgot->output_section->vma; + break; + + case R_CKCORE_GOTPC: + case R_CKCORE_GOTPC_HI16: + case R_CKCORE_GOTPC_LO16: + /* Use global offset table as symbol value. */ + relocation = htab->elf.sgot->output_section->vma; + addend = -addend; + unresolved_reloc = FALSE; + break; + + case R_CKCORE_DOFFSET_IMM18: + case R_CKCORE_DOFFSET_IMM18BY2: + case R_CKCORE_DOFFSET_IMM18BY4: + { + asection *sdata = bfd_get_section_by_name (output_bfd, ".data"); + relocation -= sdata->output_section->vma; + } + break; + + case R_CKCORE_DOFFSET_LO16: + { + asection *sdata = bfd_get_section_by_name (output_bfd, ".data"); + relocation -= sdata->output_section->vma; + } + break; + + case R_CKCORE_TOFFSET_LO16: + { + asection *stext = bfd_get_section_by_name (output_bfd, ".text"); + if (stext) + relocation -= stext->output_section->vma; + } + break; + + case R_CKCORE_PLT_IMM18BY4: + case R_CKCORE_PLT32: + /* Relocation is to the entry for this symbol in the + procedure linkage table. */ + + /* Resolve a PLT32 reloc against a local symbol directly, + without using the procedure linkage table. */ + if (h == NULL) + break; + + if (h->plt.offset == (bfd_vma) -1 || htab->elf.splt == NULL) + { + /* We didn't make a PLT entry for this symbol. This + happens when statically linking PIC code, or when + using -Bsymbolic. */ + if (h->got.offset != (bfd_vma) -1) + { + bfd_boolean dyn; + + off = h->got.offset; + dyn = htab->elf.dynamic_sections_created; + if (!WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, + bfd_link_pic (info), h) + || (bfd_link_pic (info) + && SYMBOL_REFERENCES_LOCAL (info, h)) + || (ELF_ST_VISIBILITY (h->other) + && h->root.type == bfd_link_hash_undefweak)) + { + /* This is actually a static link, or it is a + -Bsymbolic link and the symbol is defined + locally, or the symbol was forced to be local + because of a version file. We must initialize + this entry in the global offset table. Since the + offset must always be a multiple of 4, we use the + least significant bit to record whether we have + initialized it already. + + When doing a dynamic link, we create a .rela.dyn + relocation entry to initialize the value. This + is done in the finish_dynamic_symbol routine. + FIXME! */ + if (off & 1) + off &= ~1; + else + { + h->got.offset |= 1; + if (GENERATE_RELATIVE_RELOC_P (info, h)) + relative_reloc = TRUE; + } + } + bfd_put_32 (output_bfd, relocation, + htab->elf.sgot->contents + off); + + if (relative_reloc) + { + asection *srelgot; + Elf_Internal_Rela outrel; + bfd_byte *loc; + + srelgot = htab->elf.srelgot; + BFD_ASSERT (srelgot != NULL); + + outrel.r_offset + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + off); + outrel.r_info = ELF32_R_INFO (0, R_CKCORE_RELATIVE); + outrel.r_addend = relocation; + loc = srelgot->contents; + loc += (srelgot->reloc_count++ + * sizeof (Elf32_External_Rela)); + if (loc != NULL) + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + } + relocation = off + htab->elf.sgot->output_offset; + } + break; + } + /* The relocation is the got offset. */ + if (bfd_csky_abi (output_bfd) == CSKY_ABI_V2) + relocation = (h->plt.offset / PLT_ENTRY_SIZE + 2) * 4; + else + relocation = (h->plt.offset / PLT_ENTRY_SIZE_P + 2) * 4; + unresolved_reloc = FALSE; + break; + + case R_CKCORE_PCREL_IMM26BY2: + case R_CKCORE_PCREL_JSR_IMM26BY2: + case R_CKCORE_PCREL_JSR_IMM11BY2: + case R_CKCORE_PCREL_IMM11BY2: + case R_CKCORE_CALLGRAPH: + /* Emit callgraph information first. */ + /* TODO: deal with callgraph. */ + if (ELF32_R_TYPE (rel->r_info) == R_CKCORE_CALLGRAPH) + break; + /* Some reloc need further handling. */ + /* h == NULL means the symbol is a local symbol, + r_symndx == 0 means the symbol is 'ABS' and + the relocation is already handled in assemble, + here just use for callgraph. */ + /* TODO: deal with callgraph. */ + if (h == NULL && r_symndx == 0) + { + do_final_relocate = FALSE; + break; + } + + /* Ignore weak references to undefined symbols. */ + if (h != NULL && h->root.type == bfd_link_hash_undefweak) + { + do_final_relocate = FALSE; + break; + } + + /* Using branch stub. */ + if (use_branch_stub == TRUE + && ELF32_R_TYPE (rel->r_info) == R_CKCORE_PCREL_IMM26BY2) + { + struct elf32_csky_stub_hash_entry *stub_entry = NULL; + if (sym_must_create_stub (h, info)) + stub_entry = elf32_csky_get_stub_entry (input_section, + input_section, + h, rel, htab); + else if (disp > BSR_MAX_FWD_BRANCH_OFFSET + || disp < BSR_MAX_BWD_BRANCH_OFFSET) + stub_entry = elf32_csky_get_stub_entry (input_section, + input_section, + h, rel, htab); + if (stub_entry != NULL) + relocation + = (stub_entry->stub_offset + + stub_entry->stub_sec->output_offset + + stub_entry->stub_sec->output_section->vma); + break; + } + + else if (h == NULL + || (h->root.type == bfd_link_hash_defined + && h->dynindx == -1) + || ((h->def_regular && !h->def_dynamic) + && (h->root.type != bfd_link_hash_defweak + || ! bfd_link_pic (info)))) + { + if (ELF32_R_TYPE (rel->r_info) == R_CKCORE_PCREL_JSR_IMM26BY2) + { + if (within_range (disp, 26)) + { + /* In range for BSR32. */ + howto = &csky_elf_howto_table[R_CKCORE_PCREL_IMM26BY2]; + read_content_substitute = CSKY_INSN_BSR32; + } + else if (bfd_csky_arch (output_bfd) == CSKY_ARCH_810) + /* if bsr32 cannot reach, generate + "lrw r25, label; jsr r25" instead of + jsri label. */ + howto = &csky_elf_howto_table[R_CKCORE_NOJSRI]; + } /* if ELF32_R_TYPE (rel->r_info)... */ + else if (ELF32_R_TYPE (rel->r_info) + == R_CKCORE_PCREL_JSR_IMM11BY2) + { + if (within_range (disp, 11)) + { + /* In range for BSR16. */ + howto = &csky_elf_howto_table[R_CKCORE_PCREL_IMM11BY2]; + read_content_substitute = CSKY_INSN_BSR16; + } + } + break; + } /* else if h == NULL... */ + + else if (bfd_csky_arch (output_bfd) == CSKY_ARCH_810 + && (ELF32_R_TYPE (rel->r_info) + == R_CKCORE_PCREL_JSR_IMM26BY2)) + { + howto = &csky_elf_howto_table[R_CKCORE_NOJSRI]; + break; + } + /* Other situation, h->def_dynamic == 1, + undefined_symbol when output file is shared object, etc. */ + /* Else fall through. */ + + case R_CKCORE_ADDR_HI16: + case R_CKCORE_ADDR_LO16: + if (bfd_link_pic (info) + || (!bfd_link_pic (info) + && h != NULL + && h->dynindx != -1 + && !h->non_got_ref + && ((h->def_dynamic && !h->def_regular) + || (htab->elf.dynamic_sections_created + && (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined + || h->root.type == bfd_link_hash_indirect))))) + { + Elf_Internal_Rela outrel; + bfd_boolean skip, relocate; + bfd_byte *loc; + + /* When generating a shared object, these relocations + are copied into the output file to be resolved at + run time. */ + skip = FALSE; + relocate = FALSE; + + outrel.r_offset = + _bfd_elf_section_offset (output_bfd, info, input_section, + rel->r_offset); + if (outrel.r_offset == (bfd_vma) -1) + skip = TRUE; + else if (outrel.r_offset == (bfd_vma) -2) + { + skip = TRUE; + relocate = TRUE; + } + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); + if (skip) + memset (&outrel, 0, sizeof (outrel)); + else if (h != NULL + && h->dynindx != -1 + && (!bfd_link_pic (info) + || (!SYMBOLIC_BIND (info, h) + && h->root.type == bfd_link_hash_defweak) + || !h->def_regular)) + { + outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); + outrel.r_addend = rel->r_addend; + } + else + { + /* This symbol is local, or marked to become local. */ + relocate = TRUE; + outrel.r_info = ELF32_R_INFO (0, r_type); + outrel.r_addend = relocation + rel->r_addend; + } + loc = htab->elf.srelgot->contents; + loc += (htab->elf.srelgot->reloc_count++ + * sizeof (Elf32_External_Rela)); + + if (loc != NULL) + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + + /* If this reloc is against an external symbol, we do not + want to diddle with the addend. Otherwise, we need to + include the symbol value so that it becomes an addend + for the dynamic reloc. */ + if (!relocate) + continue; + } /* if bfd_link_pic (info) ... */ + break; + + case R_CKCORE_ADDR32: + /* r_symndx will be zero only for relocs against symbols + from removed linkonce sections, or sections discarded + by a linker script. + This relocation don't nedd to handle, the value will + be set to SEC_DISCARDED(0xffffffff). */ + if (r_symndx == 0 + && strcmp (sec->name, ".csky_stack_size") == 0) + { + do_final_relocate = FALSE; + break; + } + if (r_symndx >= symtab_hdr->sh_info + && h->non_got_ref + && bfd_link_executable (info)) + break; + + if (r_symndx == 0 || (input_section->flags & SEC_ALLOC) == 0) + break; + + if (bfd_link_pic (info) + || (h != NULL + && h->dynindx != -1 + && ((h->def_dynamic && !h->def_regular) + || (htab->elf.dynamic_sections_created + && (h->root.type == bfd_link_hash_undefweak + || h->root.type == bfd_link_hash_undefined + || h->root.type == bfd_link_hash_indirect))))) + { + Elf_Internal_Rela outrel; + bfd_boolean skip, relocate; + bfd_byte *loc; + + /* When generating a shared object, these relocations + are copied into the output file to be resolved at + run time. */ + skip = FALSE; + relocate = FALSE; + + outrel.r_offset = + _bfd_elf_section_offset (output_bfd, info, input_section, + rel->r_offset); + + if (outrel.r_offset == (bfd_vma) -1) + skip = TRUE; + else if (outrel.r_offset == (bfd_vma) -2) + { + skip = TRUE; + relocate = TRUE; + } + + outrel.r_offset += (input_section->output_section->vma + + input_section->output_offset); + + if (skip) + memset (&outrel, 0, sizeof (outrel)); + else if (h != NULL + && h->dynindx != -1 + && (!bfd_link_pic (info) + || (!SYMBOLIC_BIND (info, h) + && h->root.type == bfd_link_hash_defweak) + || !h->def_regular)) + { + outrel.r_info = ELF32_R_INFO (h->dynindx, r_type); + outrel.r_addend = rel->r_addend; + } + else + { + /* This symbol is local, or marked to become local. */ + outrel.r_info = ELF32_R_INFO (0, R_CKCORE_RELATIVE); + outrel.r_addend = relocation + rel->r_addend; + } + + loc = htab->elf.srelgot->contents; + loc += (htab->elf.srelgot->reloc_count++ + * sizeof (Elf32_External_Rela)); + + if (loc != NULL) + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + + /* If this reloc is against an external symbol, we do + want to diddle with the addend. Otherwise, we need to + include the symbol value so that it becomes an addend + for the dynamic reloc. */ + if (! relocate) + continue; + } + break; + + case R_CKCORE_TLS_LDO32: + relocation = relocation - dtpoff_base (info); + break; + + case R_CKCORE_TLS_LDM32: + BFD_ASSERT (htab->elf.sgot != NULL); + off = htab->tls_ldm_got.offset; + if (off & 1) + off &= ~1; + else + { + /* If we don't know the module number, + create a relocation for it. */ + if (!bfd_link_executable (info)) + { + Elf_Internal_Rela outrel; + bfd_byte *loc; + + BFD_ASSERT (htab->elf.srelgot != NULL); + outrel.r_addend = 0; + outrel.r_offset + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + off); + outrel.r_info = ELF32_R_INFO (0, R_CKCORE_TLS_DTPMOD32); + bfd_put_32 (output_bfd, outrel.r_addend, + htab->elf.sgot->contents + off); + + loc = htab->elf.srelgot->contents; + loc += (htab->elf.srelgot->reloc_count++ + * sizeof (Elf32_External_Rela)); + if (loc) + bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc); + } + else + bfd_put_32 (output_bfd, 1, + htab->elf.sgot->contents + off); + htab->tls_ldm_got.offset |= 1; + } + relocation + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + off + - (input_section->output_section->vma + + input_section->output_offset + rel->r_offset)); + break; + case R_CKCORE_TLS_LE32: + if (bfd_link_dll (info)) + { + _bfd_error_handler + /* xgettext:c-format */ + (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted " + "in shared object"), + input_bfd, input_section, (uint64_t)rel->r_offset, + howto->name); + return FALSE; + } + else + relocation = tpoff (info, relocation); + break; + case R_CKCORE_TLS_GD32: + case R_CKCORE_TLS_IE32: + { + int indx; + char tls_type; + + BFD_ASSERT (htab->elf.sgot != NULL); + + indx = 0; + if (h != NULL) + { + bfd_boolean dyn; + dyn = htab->elf.dynamic_sections_created; + if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, + bfd_link_pic (info), h) + && (!bfd_link_pic (info) + || !SYMBOL_REFERENCES_LOCAL (info, h))) + { + unresolved_reloc = FALSE; + indx = h->dynindx; + } + off = h->got.offset; + tls_type = ((struct csky_elf_link_hash_entry *)h)->tls_type; + } + else + { + BFD_ASSERT (local_got_offsets != NULL); + off = local_got_offsets[r_symndx]; + tls_type = csky_elf_local_got_tls_type (input_bfd)[r_symndx]; + } + + BFD_ASSERT (tls_type != GOT_UNKNOWN); + + if (off & 1) + off &= ~1; + else + { + bfd_boolean need_relocs = FALSE; + Elf_Internal_Rela outrel; + bfd_byte *loc = NULL; + int cur_off = off; + /* The GOT entries have not been initialized yet. Do it + now, and emit any relocations. If both an IE GOT and a + GD GOT are necessary, we emit the GD first. */ + if ((!bfd_link_executable (info) || indx != 0) + && (h == NULL + || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT + && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h)) + || h->root.type != bfd_link_hash_undefined)) + { + need_relocs = TRUE; + BFD_ASSERT (htab->elf.srelgot != NULL); + + loc = htab->elf.srelgot->contents; + loc += (htab->elf.srelgot->reloc_count + * sizeof (Elf32_External_Rela)); + } + if (tls_type & GOT_TLS_GD) + { + if (need_relocs) + { + outrel.r_addend = 0; + outrel.r_offset + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + + cur_off); + outrel.r_info + = ELF32_R_INFO (indx, R_CKCORE_TLS_DTPMOD32); + bfd_put_32 (output_bfd, outrel.r_addend, + htab->elf.sgot->contents + cur_off); + if (loc) + bfd_elf32_swap_reloca_out (output_bfd, + &outrel, loc); + loc += sizeof (Elf32_External_Rela); + htab->elf.srelgot->reloc_count++; + if (indx == 0) + bfd_put_32 (output_bfd, + relocation - dtpoff_base (info), + (htab->elf.sgot->contents + + cur_off + 4)); + else + { + outrel.r_addend = 0; + outrel.r_info + = ELF32_R_INFO (indx, R_CKCORE_TLS_DTPOFF32); + outrel.r_offset += 4; + bfd_put_32 (output_bfd, outrel.r_addend, + (htab->elf.sgot->contents + + cur_off + 4)); + outrel.r_info = + ELF32_R_INFO (indx, + R_CKCORE_TLS_DTPOFF32); + if (loc) + bfd_elf32_swap_reloca_out (output_bfd, + &outrel, + loc); + htab->elf.srelgot->reloc_count++; + loc += sizeof (Elf32_External_Rela); + } + + } + else + { + /* If are not emitting relocations for a + general dynamic reference, then we must be in a + static link or an executable link with the + symbol binding locally. Mark it as belonging + to module 1, the executable. */ + bfd_put_32 (output_bfd, 1, + htab->elf.sgot->contents + cur_off); + bfd_put_32 (output_bfd, + relocation - dtpoff_base (info), + htab->elf.sgot->contents + + cur_off + 4); + } + cur_off += 8; + } + if (tls_type & GOT_TLS_IE) + { + if (need_relocs) + { + if (indx == 0) + outrel.r_addend = relocation - dtpoff_base (info); + else + outrel.r_addend = 0; + outrel.r_offset + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + cur_off); + outrel.r_info + = ELF32_R_INFO (indx, R_CKCORE_TLS_TPOFF32); + + bfd_put_32 (output_bfd, outrel.r_addend, + htab->elf.sgot->contents + cur_off); + if (loc) + bfd_elf32_swap_reloca_out (output_bfd, + &outrel, loc); + htab->elf.srelgot->reloc_count++; + loc += sizeof (Elf32_External_Rela); + } + else + bfd_put_32 (output_bfd, tpoff (info, relocation), + htab->elf.sgot->contents + cur_off); + } + if (h != NULL) + h->got.offset |= 1; + else + local_got_offsets[r_symndx] |= 1; + } + if ((tls_type & GOT_TLS_GD) && howto->type != R_CKCORE_TLS_GD32) + off += 8; + relocation + = (htab->elf.sgot->output_section->vma + + htab->elf.sgot->output_offset + off + - (input_section->output_section->vma + + input_section->output_offset + + rel->r_offset)); + break; + } + default: + /* No substitution when final linking. */ + read_content_substitute = 0; + break; + } /* End switch (howto->type). */ + + /* Make sure 32-bit data in the text section will not be affected by + our special endianness. + However, this currently affects noting, since the ADDR32 howto type + does no change with the data read. But we may need this mechanism in + the future. */ + + if (howto->size == 2 + && (howto->type == R_CKCORE_ADDR32 + || howto->type == R_CKCORE_GOT32 + || howto->type == R_CKCORE_GOTOFF + || howto->type == R_CKCORE_GOTPC + || howto->type == R_CKCORE_PLT32 + || howto->type == R_CKCORE_TLS_LE32 + || howto->type == R_CKCORE_TLS_IE32 + || howto->type == R_CKCORE_TLS_LDM32 + || howto->type == R_CKCORE_TLS_GD32 + || howto->type == R_CKCORE_TLS_LDO32 + || howto->type == R_CKCORE_RELATIVE)) + need_reverse_bits = 0; + else + need_reverse_bits = 1; + /* Do the final link. */ + if (howto->type != R_CKCORE_PCREL_JSR_IMM11BY2 + && howto->type != R_CKCORE_PCREL_JSR_IMM26BY2 + && howto->type != R_CKCORE_CALLGRAPH + && do_final_relocate) + r = csky_final_link_relocate (howto, input_bfd, input_section, + contents, rel->r_offset, + relocation, addend); + + if (r != bfd_reloc_ok) + { + ret = FALSE; + switch (r) + { + default: + break; + case bfd_reloc_overflow: + if (h != NULL) + name = NULL; + else + { + name = bfd_elf_string_from_elf_section (input_bfd, + symtab_hdr->sh_link, + sym->st_name); + if (name == NULL) + break; + if (*name == '\0') + name = bfd_section_name (input_bfd, sec); + } + (*info->callbacks->reloc_overflow) + (info, + (h ? &h->root : NULL), + name, howto->name, (bfd_vma) 0, + input_bfd, input_section, rel->r_offset); + break; + } + } + } /* End for (;rel < relend; rel++). */ + return ret; +} + +static bfd_boolean +csky_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note) +{ + int offset; + size_t size; + + switch (note->descsz) + { + default: + return FALSE; + /* Sizeof (struct elf_prstatus) on C-SKY V1 arch. */ + case 148: + elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); + elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24); + offset = 72; + size = 72; + break; + /* Sizeof (struct elf_prstatus) on C-SKY V1 arch. */ + case 220: + elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12); + elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24); + offset = 72; + size = 34 * 4; + break; + } + /* Make a ".reg/999" section. */ + return _bfd_elfcore_make_pseudosection (abfd, ".reg", + size, note->descpos + offset); +} + +static bfd_boolean +csky_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note) +{ + switch (note->descsz) + { + default: + return FALSE; + + /* Sizeof (struct elf_prpsinfo) on linux csky. */ + case 124: + elf_tdata (abfd)->core->program + = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16); + elf_tdata (abfd)->core->command + = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80); + } + + /* Note that for some reason, a spurious space is tacked + onto the end of the args in some (at least one anyway) + implementations, so strip it off if it exists. */ + { + char *command = elf_tdata (abfd)->core->command; + int n = strlen (command); + + if (0 < n && command[n - 1] == ' ') + command[n - 1] = '\0'; + } + + return TRUE; +} + +/* End of external entry points for sizing and building linker stubs. */ + +/* CPU-related basic API. */ +#define TARGET_BIG_SYM csky_elf32_be_vec +#define TARGET_BIG_NAME "elf32-csky-big" +#define TARGET_LITTLE_SYM csky_elf32_le_vec +#define TARGET_LITTLE_NAME "elf32-csky-little" +#define ELF_ARCH bfd_arch_csky +#define ELF_MACHINE_CODE EM_CSKY +#define ELF_MACHINE_ALT1 EM_CSKY_OLD +#define ELF_MAXPAGESIZE 0x1000 +#define elf_info_to_howto csky_elf_info_to_howto +#define elf_info_to_howto_rel NULL +#define elf_backend_special_sections csky_elf_special_sections +#define bfd_elf32_bfd_link_hash_table_create csky_elf_link_hash_table_create + +/* Target related API. */ +#define bfd_elf32_mkobject csky_elf_mkobject +#define bfd_elf32_bfd_merge_private_bfd_data csky_elf_merge_private_bfd_data +#define bfd_elf32_bfd_set_private_flags csky_elf_set_private_flags +#define elf_backend_copy_indirect_symbol csky_elf_copy_indirect_symbol + +/* GC section related API. */ +#define elf_backend_can_gc_sections 1 +#define elf_backend_gc_mark_hook csky_elf_gc_mark_hook +#define elf_backend_gc_mark_extra_sections elf32_csky_gc_mark_extra_sections + +/* Relocation related API. */ +#define elf_backend_reloc_type_class csky_elf_reloc_type_class +#define bfd_elf32_bfd_reloc_type_lookup csky_elf_reloc_type_lookup +#define bfd_elf32_bfd_reloc_name_lookup csky_elf_reloc_name_lookup +#define elf_backend_ignore_discarded_relocs csky_elf_ignore_discarded_relocs +#define elf_backend_relocate_section csky_elf_relocate_section +#define elf_backend_check_relocs csky_elf_check_relocs + +/* Dynamic relocate related API. */ +#define elf_backend_create_dynamic_sections _bfd_elf_create_dynamic_sections +#define elf_backend_adjust_dynamic_symbol csky_elf_adjust_dynamic_symbol +#define elf_backend_size_dynamic_sections csky_elf_size_dynamic_sections +#define elf_backend_finish_dynamic_symbol csky_elf_finish_dynamic_symbol +#define elf_backend_finish_dynamic_sections csky_elf_finish_dynamic_sections +#define elf_backend_rela_normal 1 +#define elf_backend_can_refcount 1 +#define elf_backend_plt_readonly 1 +#define elf_backend_want_got_sym 1 +#define elf_backend_want_dynrelro 1 +#define elf_backend_got_header_size 12 +#define elf_backend_want_got_plt 1 + +/* C-SKY coredump support. */ +#define elf_backend_grok_prstatus csky_elf_grok_prstatus +#define elf_backend_grok_psinfo csky_elf_grok_psinfo + +#include "elf32-target.h" diff --git a/bfd/libbfd.h b/bfd/libbfd.h index a884aab..cd4b096 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -3217,6 +3217,71 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_WASM32_CODE_POINTER", "BFD_RELOC_WASM32_INDEX", "BFD_RELOC_WASM32_PLT_SIG", + "BFD_RELOC_CKCORE_NONE", + "BFD_RELOC_CKCORE_ADDR32", + "BFD_RELOC_CKCORE_PCREL_IMM8BY4", + "BFD_RELOC_CKCORE_PCREL_IMM11BY2", + "BFD_RELOC_CKCORE_PCREL_IMM4BY2", + "BFD_RELOC_CKCORE_PCREL32", + "BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2", + "BFD_RELOC_CKCORE_GNU_VTINHERIT", + "BFD_RELOC_CKCORE_GNU_VTENTRY", + "BFD_RELOC_CKCORE_RELATIVE", + "BFD_RELOC_CKCORE_COPY", + "BFD_RELOC_CKCORE_GLOB_DAT", + "BFD_RELOC_CKCORE_JUMP_SLOT", + "BFD_RELOC_CKCORE_GOTOFF", + "BFD_RELOC_CKCORE_GOTPC", + "BFD_RELOC_CKCORE_GOT32", + "BFD_RELOC_CKCORE_PLT32", + "BFD_RELOC_CKCORE_ADDRGOT", + "BFD_RELOC_CKCORE_ADDRPLT", + "BFD_RELOC_CKCORE_PCREL_IMM26BY2", + "BFD_RELOC_CKCORE_PCREL_IMM16BY2", + "BFD_RELOC_CKCORE_PCREL_IMM16BY4", + "BFD_RELOC_CKCORE_PCREL_IMM10BY2", + "BFD_RELOC_CKCORE_PCREL_IMM10BY4", + "BFD_RELOC_CKCORE_ADDR_HI16", + "BFD_RELOC_CKCORE_ADDR_LO16", + "BFD_RELOC_CKCORE_GOTPC_HI16", + "BFD_RELOC_CKCORE_GOTPC_LO16", + "BFD_RELOC_CKCORE_GOTOFF_HI16", + "BFD_RELOC_CKCORE_GOTOFF_LO16", + "BFD_RELOC_CKCORE_GOT12", + "BFD_RELOC_CKCORE_GOT_HI16", + "BFD_RELOC_CKCORE_GOT_LO16", + "BFD_RELOC_CKCORE_PLT12", + "BFD_RELOC_CKCORE_PLT_HI16", + "BFD_RELOC_CKCORE_PLT_LO16", + "BFD_RELOC_CKCORE_ADDRGOT_HI16", + "BFD_RELOC_CKCORE_ADDRGOT_LO16", + "BFD_RELOC_CKCORE_ADDRPLT_HI16", + "BFD_RELOC_CKCORE_ADDRPLT_LO16", + "BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2", + "BFD_RELOC_CKCORE_TOFFSET_LO16", + "BFD_RELOC_CKCORE_DOFFSET_LO16", + "BFD_RELOC_CKCORE_PCREL_IMM18BY2", + "BFD_RELOC_CKCORE_DOFFSET_IMM18", + "BFD_RELOC_CKCORE_DOFFSET_IMM18BY2", + "BFD_RELOC_CKCORE_DOFFSET_IMM18BY4", + "BFD_RELOC_CKCORE_GOTOFF_IMM18", + "BFD_RELOC_CKCORE_GOT_IMM18BY4", + "BFD_RELOC_CKCORE_PLT_IMM18BY4", + "BFD_RELOC_CKCORE_PCREL_IMM7BY4", + "BFD_RELOC_CKCORE_TLS_LE32", + "BFD_RELOC_CKCORE_TLS_IE32", + "BFD_RELOC_CKCORE_TLS_GD32", + "BFD_RELOC_CKCORE_TLS_LDM32", + "BFD_RELOC_CKCORE_TLS_LDO32", + "BFD_RELOC_CKCORE_TLS_DTPMOD32", + "BFD_RELOC_CKCORE_TLS_DTPOFF32", + "BFD_RELOC_CKCORE_TLS_TPOFF32", + "BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4", + "BFD_RELOC_CKCORE_NOJSRI", + "BFD_RELOC_CKCORE_CALLGRAPH", + "BFD_RELOC_CKCORE_IRELATIVE", + "BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4", + "BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4", "@@overflow: BFD_RELOC_UNUSED@@", }; #endif diff --git a/bfd/reloc.c b/bfd/reloc.c index 68bc8a8..c8ddb2f 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -7988,6 +7988,139 @@ ENUMX ENUMDOC WebAssembly relocations. +ENUM + BFD_RELOC_CKCORE_NONE +ENUMX + BFD_RELOC_CKCORE_ADDR32 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM8BY4 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM11BY2 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM4BY2 +ENUMX + BFD_RELOC_CKCORE_PCREL32 +ENUMX + BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2 +ENUMX + BFD_RELOC_CKCORE_GNU_VTINHERIT +ENUMX + BFD_RELOC_CKCORE_GNU_VTENTRY +ENUMX + BFD_RELOC_CKCORE_RELATIVE +ENUMX + BFD_RELOC_CKCORE_COPY +ENUMX + BFD_RELOC_CKCORE_GLOB_DAT +ENUMX + BFD_RELOC_CKCORE_JUMP_SLOT +ENUMX + BFD_RELOC_CKCORE_GOTOFF +ENUMX + BFD_RELOC_CKCORE_GOTPC +ENUMX + BFD_RELOC_CKCORE_GOT32 +ENUMX + BFD_RELOC_CKCORE_PLT32 +ENUMX + BFD_RELOC_CKCORE_ADDRGOT +ENUMX + BFD_RELOC_CKCORE_ADDRPLT +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM26BY2 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM16BY2 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM16BY4 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM10BY2 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM10BY4 +ENUMX + BFD_RELOC_CKCORE_ADDR_HI16 +ENUMX + BFD_RELOC_CKCORE_ADDR_LO16 +ENUMX + BFD_RELOC_CKCORE_GOTPC_HI16 +ENUMX + BFD_RELOC_CKCORE_GOTPC_LO16 +ENUMX + BFD_RELOC_CKCORE_GOTOFF_HI16 +ENUMX + BFD_RELOC_CKCORE_GOTOFF_LO16 +ENUMX + BFD_RELOC_CKCORE_GOT12 +ENUMX + BFD_RELOC_CKCORE_GOT_HI16 +ENUMX + BFD_RELOC_CKCORE_GOT_LO16 +ENUMX + BFD_RELOC_CKCORE_PLT12 +ENUMX + BFD_RELOC_CKCORE_PLT_HI16 +ENUMX + BFD_RELOC_CKCORE_PLT_LO16 +ENUMX + BFD_RELOC_CKCORE_ADDRGOT_HI16 +ENUMX + BFD_RELOC_CKCORE_ADDRGOT_LO16 +ENUMX + BFD_RELOC_CKCORE_ADDRPLT_HI16 +ENUMX + BFD_RELOC_CKCORE_ADDRPLT_LO16 +ENUMX + BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2 +ENUMX + BFD_RELOC_CKCORE_TOFFSET_LO16 +ENUMX + BFD_RELOC_CKCORE_DOFFSET_LO16 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM18BY2 +ENUMX + BFD_RELOC_CKCORE_DOFFSET_IMM18 +ENUMX + BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 +ENUMX + BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 +ENUMX + BFD_RELOC_CKCORE_GOTOFF_IMM18 +ENUMX + BFD_RELOC_CKCORE_GOT_IMM18BY4 +ENUMX + BFD_RELOC_CKCORE_PLT_IMM18BY4 +ENUMX + BFD_RELOC_CKCORE_PCREL_IMM7BY4 +ENUMX + BFD_RELOC_CKCORE_TLS_LE32 +ENUMX + BFD_RELOC_CKCORE_TLS_IE32 +ENUMX + BFD_RELOC_CKCORE_TLS_GD32 +ENUMX + BFD_RELOC_CKCORE_TLS_LDM32 +ENUMX + BFD_RELOC_CKCORE_TLS_LDO32 +ENUMX + BFD_RELOC_CKCORE_TLS_DTPMOD32 +ENUMX + BFD_RELOC_CKCORE_TLS_DTPOFF32 +ENUMX + BFD_RELOC_CKCORE_TLS_TPOFF32 +ENUMX + BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 +ENUMX + BFD_RELOC_CKCORE_NOJSRI +ENUMX + BFD_RELOC_CKCORE_CALLGRAPH +ENUMX + BFD_RELOC_CKCORE_IRELATIVE +ENUMX + BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4 +ENUMX + BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4 +ENUMDOC + C-SKY relocations. + ENDSENUM BFD_RELOC_UNUSED CODE_FRAGMENT diff --git a/bfd/targets.c b/bfd/targets.c index 531703d..b59dd76 100644 --- a/bfd/targets.c +++ b/bfd/targets.c @@ -630,6 +630,8 @@ extern const bfd_target cris_aout_vec; extern const bfd_target cris_elf32_vec; extern const bfd_target cris_elf32_us_vec; extern const bfd_target crx_elf32_vec; +extern const bfd_target csky_elf32_be_vec; +extern const bfd_target csky_elf32_le_vec; extern const bfd_target d10v_elf32_vec; extern const bfd_target d30v_elf32_vec; extern const bfd_target dlx_elf32_be_vec; @@ -960,6 +962,9 @@ static const bfd_target * const _bfd_target_vector[] = &crx_elf32_vec, + &csky_elf32_be_vec, + &csky_elf32_le_vec, + &d10v_elf32_vec, &d30v_elf32_vec, diff --git a/binutils/ChangeLog b/binutils/ChangeLog index b40b267..35c04b4 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,11 @@ +2018-07-30 Andrew Jenner <andrew@codesourcery.com> + + * readelf.c: Include elf/csky.h. + (guess_is_rela): Handle EM_CSKY. + (dump_relocations): Likewise. + (get_machine_name): Likewise. + (is_32bit_abs_reloc): Likewise. + 2018-07-25 Nick Clifton <nickc@redhat.com> * rdcoff.c (parse_coff_struct_type): Free fields array upon early diff --git a/binutils/readelf.c b/binutils/readelf.c index fe8560c..90dbdf7 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -98,6 +98,7 @@ #include "elf/cr16.h" #include "elf/cris.h" #include "elf/crx.h" +#include "elf/csky.h" #include "elf/d10v.h" #include "elf/d30v.h" #include "elf/dlx.h" @@ -797,6 +798,7 @@ guess_is_rela (unsigned int e_machine) case EM_CR16: case EM_CRIS: case EM_CRX: + case EM_CSKY: case EM_D30V: case EM_CYGNUS_D30V: case EM_FR30: @@ -1348,6 +1350,10 @@ dump_relocations (Filedata * filedata, rtype = elf_frv_reloc_type (type); break; + case EM_CSKY: + rtype = elf_csky_reloc_type (type); + break; + case EM_FT32: rtype = elf_ft32_reloc_type (type); break; @@ -2501,6 +2507,7 @@ get_machine_name (unsigned e_machine) case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY"; case EM_CYGNUS_FRV: return "Fujitsu FR-V"; case EM_S12Z: return "Freescale S12Z"; + case EM_CSKY: return "C-SKY"; default: snprintf (buff, sizeof (buff), _("<unknown>: 0x%x"), e_machine); @@ -12307,6 +12314,8 @@ is_32bit_abs_reloc (Filedata * filedata, unsigned int reloc_type) return reloc_type == 3; /* R_CR16_NUM32. */ case EM_CRX: return reloc_type == 15; /* R_CRX_NUM32. */ + case EM_CSKY: + return reloc_type == 1; /* R_CKCORE_ADDR32. */ case EM_CYGNUS_FRV: return reloc_type == 1; case EM_CYGNUS_D10V: diff --git a/gas/ChangeLog b/gas/ChangeLog index f2a0c6a..3f5c4e5 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,24 @@ +2018-07-30 Andrew Jenner <andrew@codesourcery.com> + + * Makefile.am (TARGET_CPU_CFILES): Add entry for C-SKY. + (TARGET_CPU_HFILES, TARGET_ENV_HFILES): Likewise. + * Makefile.in: Regenerated. + * config/tc-csky.c: New file. + * config/tc-csky.h: New file. + * config/te-csky_abiv1.h: New file. + * config/te-csky_abiv1_linux.h: New file. + * config/te-csky_abiv2.h: New file. + * config/te-csky_abiv2_linux.h: New file. + * configure.tgt: Add C-SKY. + * doc/Makefile.am (CPU_DOCS): Add entry for C-SKY. + * doc/Makefile.in: Regenerated. + * doc/all.texi: Set CSKY feature. + * doc/as.texi (Overview): Add C-SKY options. + (Machine Dependencies): Likewise. + * doc/c-csky.texi: New file. + * testsuite/gas/csky/*: New test cases. + * NEWS: Mention the support. + 2018-07-29 John David Anglin <danglin@gcc.gnu.org> * config/tc-hppa.c: Include "struc-symbol.h". diff --git a/gas/Makefile.am b/gas/Makefile.am index 959e9e9..8f520d3 100644 --- a/gas/Makefile.am +++ b/gas/Makefile.am @@ -138,6 +138,7 @@ TARGET_CPU_CFILES = \ config/tc-cr16.c \ config/tc-cris.c \ config/tc-crx.c \ + config/tc-csky.c \ config/tc-d10v.c \ config/tc-d30v.c \ config/tc-dlx.c \ @@ -212,6 +213,7 @@ TARGET_CPU_HFILES = \ config/tc-cr16.h \ config/tc-cris.h \ config/tc-crx.h \ + config/tc-csky.h \ config/tc-d10v.h \ config/tc-d30v.h \ config/tc-dlx.h \ @@ -308,6 +310,10 @@ TARG_ENV_HFILES = \ config/te-armfbsdeabi.h \ config/te-armfbsdvfp.h \ config/te-armlinuxeabi.h \ + config/te-csky_abiv1.h \ + config/te-csky_abiv1_linux.h \ + config/te-csky_abiv2.h \ + config/te-csky_abiv2_linux.h \ config/te-freebsd.h \ config/te-generic.h \ config/te-gnu.h \ diff --git a/gas/Makefile.in b/gas/Makefile.in index 42ae871..862f948 100644 --- a/gas/Makefile.in +++ b/gas/Makefile.in @@ -527,6 +527,7 @@ TARGET_CPU_CFILES = \ config/tc-cr16.c \ config/tc-cris.c \ config/tc-crx.c \ + config/tc-csky.c \ config/tc-d10v.c \ config/tc-d30v.c \ config/tc-dlx.c \ @@ -601,6 +602,7 @@ TARGET_CPU_HFILES = \ config/tc-cr16.h \ config/tc-cris.h \ config/tc-crx.h \ + config/tc-csky.h \ config/tc-d10v.h \ config/tc-d30v.h \ config/tc-dlx.h \ @@ -697,6 +699,10 @@ TARG_ENV_HFILES = \ config/te-armfbsdeabi.h \ config/te-armfbsdvfp.h \ config/te-armlinuxeabi.h \ + config/te-csky_abiv1.h \ + config/te-csky_abiv1_linux.h \ + config/te-csky_abiv2.h \ + config/te-csky_abiv2_linux.h \ config/te-freebsd.h \ config/te-generic.h \ config/te-gnu.h \ @@ -896,6 +902,8 @@ config/tc-cris.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-crx.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) +config/tc-csky.$(OBJEXT): config/$(am__dirstamp) \ + config/$(DEPDIR)/$(am__dirstamp) config/tc-d10v.$(OBJEXT): config/$(am__dirstamp) \ config/$(DEPDIR)/$(am__dirstamp) config/tc-d30v.$(OBJEXT): config/$(am__dirstamp) \ @@ -1146,6 +1154,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cr16.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-cris.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-crx.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-csky.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-d10v.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-d30v.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@config/$(DEPDIR)/tc-dlx.Po@am__quote@ @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the C-SKY processor series. + * Add support for the MIPS Loongson MultiMedia extensions Instructions (MMI) ASE. diff --git a/gas/config/tc-csky.c b/gas/config/tc-csky.c new file mode 100644 index 0000000..bd0672f --- /dev/null +++ b/gas/config/tc-csky.c @@ -0,0 +1,7299 @@ +/* tc-csky.c -- Assembler for C-SKY + Copyright (C) 1989-2018 Free Software Foundation, Inc. + Created by Lifang Xia (lifang_xia@c-sky.com) + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "as.h" +#include <limits.h> +#include <stdint.h> +#include <stdarg.h> +#include <ctype.h> +#include "safe-ctype.h" +#include "subsegs.h" +#include "obstack.h" +#include "libiberty.h" +#include "struc-symbol.h" + +#ifdef OBJ_ELF +#include "elf/csky.h" +#include "dw2gencfi.h" +#endif +#include "tc-csky.h" +#include "dwarf2dbg.h" + +#define BUILD_AS 1 + +#define OPCODE_MAX_LEN 20 +#define HAS_SUB_OPERAND 0xfffffffful + +/* This value is just for lrw to distinguish "[]" label. */ +#define NEED_OUTPUT_LITERAL 1 + +#define IS_EXTERNAL_SYM(sym, sec) (S_GET_SEGMENT (sym) != sec) +#define IS_SUPPORT_OPCODE16(opcode) (opcode->isa_flag16 | isa_flag) +#define IS_SUPPORT_OPCODE32(opcode) (opcode->isa_flag32 | isa_flag) + + +#define KB * 1024 +#define MB KB * 1024 +#define GB MB * 1024 + +/* Define DSP version flags. For different CPU, the version of DSP + instructions may be different. */ +#define CSKY_DSP_FLAG_V1 (1 << 0) /* Normal DSP instructions. */ +#define CSKY_DSP_FLAG_V2 (1 << 1) /* CK803S enhanced DSP. */ + +/* Literal pool related macros. */ +/* 1024 - 1 entry - 2 byte rounding. */ +#define v1_SPANPANIC (998) +#define v1_SPANCLOSE (900) +#define v1_SPANEXIT (600) +#define v2_SPANPANIC (1024 - 4) + +/* 1024 is flrw offset. + 24 is the biggest size for single instruction. + for lrw16 (3+7, 512 bytes). */ +#define v2_SPANCLOSE (512 - 24) + +/* For lrw16, 112 average size for a function. */ +#define v2_SPANEXIT (512 - 112) + +/* For lrw16 (3+7, 512 bytes). */ +#define v2_SPANCLOSE_ELRW (1016 - 24) + +/* For lrw16, 112 average size for a function. */ +#define v2_SPANEXIT_ELRW (1016 - 112) +#define MAX_POOL_SIZE (1024 / 4) +#define POOL_END_LABEL ".LE" +#define POOL_START_LABEL ".LS" + +/* Used in v1_relax_table. */ +/* These are the two types of relaxable instruction. */ +#define COND_JUMP 1 +#define UNCD_JUMP 2 +#define COND_JUMP_PIC 3 +#define UNCD_JUMP_PIC 4 + +#define UNDEF_DISP 0 +#define DISP12 1 +#define DISP32 2 +#define UNDEF_WORD_DISP 3 + +#define C12_LEN 2 +/* Allow for align: bt/jmpi/.long + align. */ +#define C32_LEN 10 +/* Allow for align: bt/subi/stw/bsr/lrw/add/ld/addi/jmp/.long + align. */ +#define C32_LEN_PIC 24 +#define U12_LEN 2 +/* Allow for align: jmpi/.long + align. */ +#define U32_LEN 8 +/* Allow for align: subi/stw/bsr/lrw/add/ld/addi/jmp/.long + align. */ +#define U32_LEN_PIC 22 + +#define C(what,length) (((what) << 2) + (length)) +#define UNCD_JUMP_S (do_pic ? UNCD_JUMP_PIC : UNCD_JUMP) +#define COND_JUMP_S (do_pic ? COND_JUMP_PIC : COND_JUMP) +#define U32_LEN_S (do_pic ? U32_LEN_PIC : U32_LEN) +#define C32_LEN_S (do_pic ? C32_LEN_PIC : C32_LEN) + +/* Used in v2_relax_table. */ +#define COND_DISP10_LEN 2 /* bt/bf_16. */ +#define COND_DISP16_LEN 4 /* bt/bf_32. */ + +#define SCOND_DISP10_LEN 2 /* bt/bf_16, for CK801 only. */ +#define SCOND_DISP16_LEN 6 /* !(bt/bf_16) + br_32. */ + +#define UNCD_DISP10_LEN 2 /* br_16. */ +#define UNCD_DISP16_LEN 4 /* br_32. */ +#define UNCD_DISP26_LEN 4 /* br32_old. */ + +#define JCOND_DISP10_LEN 2 /* bt/bf_16. */ +#define JCOND_DISP16_LEN 4 /* bt/bf_32. */ +#define JCOND_DISP32_LEN 12 /* !(bt/bf_16)/jmpi 32/.align 2/literal 4. */ +#define JCOND_DISP26_LEN 8 /* bt/bf_32/br_32 old. */ + +#define JUNCD_DISP26_LEN 4 /* bt/bf_32 old. */ +#define JUNCD_DISP10_LEN 2 /* br_16. */ +#define JUNCD_DISP16_LEN 4 /* bt/bf_32. */ +#define JUNCD_DISP32_LEN 10 /* jmpi_32/.align 2/literal 4/ CHANGED!. */ +#define JCOMP_DISP26_LEN 8 /* bne_32/br_32 old. */ + +#define JCOMP_DISP16_LEN 4 /* bne_32 old. */ +#define JCOMPZ_DISP16_LEN 4 /* bhlz_32. */ +#define JCOMPZ_DISP32_LEN 14 /* bsz_32/jmpi 32/.align 2/literal 4. */ +#define JCOMPZ_DISP26_LEN 8 /* bsz_32/br_32 old. */ +#define JCOMP_DISP32_LEN 14 /* be_32/jmpi_32/.align 2/literal old. */ + +#define BSR_DISP10_LEN 2 /* bsr_16. */ +#define BSR_DISP26_LEN 4 /* bsr_32. */ +#define LRW_DISP7_LEN 2 /* lrw16. */ +#define LRW_DISP16_LEN 4 /* lrw32. */ + +/* Declare worker functions. */ +bfd_boolean v1_work_lrw (void); +bfd_boolean v1_work_jbsr (void); +bfd_boolean v1_work_fpu_fo (void); +bfd_boolean v1_work_fpu_fo_fc (void); +bfd_boolean v1_work_fpu_write (void); +bfd_boolean v1_work_fpu_read (void); +bfd_boolean v1_work_fpu_writed (void); +bfd_boolean v1_work_fpu_readd (void); +bfd_boolean v2_work_istack (void); +bfd_boolean v2_work_btsti (void); +bfd_boolean v2_work_addi (void); +bfd_boolean v2_work_subi (void); +bfd_boolean v2_work_add_sub (void); +bfd_boolean v2_work_rotlc (void); +bfd_boolean v2_work_bgeni (void); +bfd_boolean v2_work_not (void); +bfd_boolean v2_work_jbtf (void); +bfd_boolean v2_work_jbr (void); +bfd_boolean v2_work_lrw (void); +bfd_boolean v2_work_lrsrsw (void); +bfd_boolean v2_work_jbsr (void); +bfd_boolean v2_work_jsri (void); +bfd_boolean v2_work_movih (void); +bfd_boolean v2_work_ori (void); +bfd_boolean float_work_fmovi (void); +bfd_boolean dsp_work_bloop (void); + +/* csky-opc.h must be included after workers are declared. */ +#include "opcodes/csky-opc.h" +#include "opcode/csky.h" + +enum +{ + RELAX_NONE = 0, + RELAX_OVERFLOW, + + COND_DISP10 = 20, /* bt/bf_16. */ + COND_DISP16, /* bt/bf_32. */ + + SCOND_DISP10, /* br_16 */ + SCOND_DISP16, /* !(bt/bf_32) + br_32. */ + + UNCD_DISP10, /* br_16. */ + UNCD_DISP16, /* br_32. */ + + JCOND_DISP10, /* bt/bf_16. */ + JCOND_DISP16, /* bt/bf_32. */ + JCOND_DISP32, /* !(bt/bf_32)/jmpi + literal. */ + + JUNCD_DISP10, /* br_16. */ + JUNCD_DISP16, /* br_32. */ + JUNCD_DISP32, /* jmpi + literal. */ + + JCOMPZ_DISP16, /* bez/bnez/bhz/blsz/blz/bhsz. */ + JCOMPZ_DISP32, /* !(jbez/jbnez/jblsz/jblz/jbhsz) + jmpi + literal. */ + + BSR_DISP26, /* bsr_32. */ + + LRW_DISP7, /* lrw16. */ + LRW2_DISP8, /* lrw16, -mno-bsr16,8 bit offset. */ + LRW_DISP16, /* lrw32. */ +}; + +unsigned int mach_flag = 0; +unsigned int arch_flag = 0; +unsigned int other_flag = 0; +unsigned int isa_flag = 0; +unsigned int dsp_flag = 0; + +typedef struct stack_size_entry +{ + struct stack_size_entry *next; + symbolS *function; + unsigned int stack_size; +} stack_size_entry; + +struct csky_arch_info +{ + const char *name; + unsigned int arch_flag; + unsigned int bfd_mach_flag; +}; + +struct csky_cpu_info +{ + const char *name; + unsigned int mach_flag; + unsigned int isa_flag; +}; + +typedef enum +{ + INSN_OPCODE, + INSN_OPCODE16F, + INSN_OPCODE32F, +} inst_flag; + +/* Macro information. */ +struct csky_macro_info +{ + const char *name; + /* How many operands : if operands == 5, all of 1,2,3,4 are ok. */ + long oprnd_num; + int isa_flag; + /* Do the work. */ + void (*handle_func)(void); +}; + +struct csky_insn_info +{ + /* Name of the opcode. */ + char *name; + /* Output instruction. */ + unsigned int inst; + /* Pointer for frag. */ + char *output; + /* End of instruction. */ + char *opcode_end; + /* Flag for INSN_OPCODE16F, INSN_OPCODE32F, INSN_OPCODE, INSN_MACRO. */ + inst_flag flag_force; + /* Operand number. */ + int number; + struct csky_opcode *opcode; + struct csky_macro_info *macro; + /* Insn size for check_literal. */ + unsigned int isize; + /* Max size of insn for relax frag_var. */ + unsigned int max; + /* Indicates which element is in csky_opcode_info op[] array. */ + int opcode_idx; + /* The value of each operand in instruction when layout. */ + int idx; + int val[MAX_OPRND_NUM]; + struct relax_info + { + int max; + int var; + int subtype; + } relax; + /* The following are used for constant expressions. */ + expressionS e1; + expressionS e2; +}; + +/* Literal pool data structures. */ +struct literal +{ + unsigned short refcnt; + unsigned char ispcrel; + unsigned char unused; + bfd_reloc_code_real_type r_type; + expressionS e; + struct tls_addend tls_addend; + unsigned char isdouble; + uint64_t dbnum; +}; + +static void csky_idly (void); +static void csky_rolc (void); +static void csky_sxtrb (void); +static void csky_movtf (void); +static void csky_addc64 (void); +static void csky_subc64 (void); +static void csky_or64 (void); +static void csky_xor64 (void); +static void csky_neg (void); +static void csky_rsubi (void); +static void csky_arith (void); +static void csky_decne (void); +static void csky_lrw (void); + +static enum bfd_reloc_code_real insn_reloc; + +/* Assembler operand parse errors use these identifiers. */ + +enum error_number +{ + /* The following are errors. */ + ERROR_CREG_ILLEGAL = 0, + ERROR_REG_OVER_RANGE, + ERROR_GREG_ILLEGAL, + ERROR_802J_REG_OVER_RANGE, + ERROR_REG_FORMAT, + ERROR_REG_LIST, + ERROR_IMM_ILLEGAL, + ERROR_IMM_OVERFLOW, /* 5 */ + ERROR_IMM_POWER, + ERROR_JMPIX_OVER_RANGE, + ERROR_EXP_CREG, + ERROR_EXP_GREG, + ERROR_EXP_CONSTANT, + ERROR_EXP_EVEN_FREG, + ERROR_RELOC_ILLEGAL, + ERROR_MISSING_OPERAND, /* 10 */ + ERROR_MISSING_COMMA, + ERROR_MISSING_LBRACKET, + ERROR_MISSING_RBRACKET, + ERROR_MISSING_LSQUARE_BRACKETS, + ERROR_MISSING_RSQUARE_BRACKETS, /* 15 */ + ERROR_MISSING_LANGLE_BRACKETS, + ERROR_MISSING_RANGLE_BRACKETS, + ERROR_OFFSET_UNALIGNED, + ERROR_BAD_END, + ERROR_UNDEFINE, + ERROR_CPREG_ILLEGAL, /* 20 */ + ERROR_OPCODE_PSRBIT, + ERROR_OPERANDS_ILLEGAL, + ERROR_OPERANDS_NUMBER, + ERROR_OPCODE_ILLEGAL, + + /* The following are warnings. */ + WARNING_OPTIONS, + WARNING_IDLY, + + /* Error and warning end. */ + ERROR_NONE, +}; + +/* Global error state. ARG1 and ARG2 are opaque data interpreted + as appropriate for the error code. */ + +struct csky_error_state +{ + enum error_number err_num; + int opnum; + const void *arg1; + const void *arg2; +} error_state; + +/* This macro is used to set error number and arg1 in the global state. */ + +#define SET_ERROR_NUMBER(err, msg) \ + do { \ + if (error_state.err_num > err) \ + { \ + error_state.err_num = err; \ + error_state.arg1 = (void *)msg; \ + } \ + } while (0) + + +/* Map error identifiers onto a format string, which will use + arg1 and arg2 from the global error state. */ +struct csky_error_format_map +{ + enum error_number num; + const char *fmt; +}; + +static const struct csky_error_format_map err_formats[] = +{ + {ERROR_CREG_ILLEGAL, "Operand %d error: control register is illegal."}, + {ERROR_REG_OVER_RANGE, "Operand %d error: r%d register is over range."}, + {ERROR_GREG_ILLEGAL, "Operand %d error: general register is illegal."}, + {ERROR_802J_REG_OVER_RANGE, "Operand %d register %s out of range (802j only has registers:0-15,23,24,25,30)"}, + {ERROR_REG_FORMAT, "Operand %d error: %s."}, + {ERROR_REG_LIST, "Register list format is illegal."}, + {ERROR_IMM_ILLEGAL, "Operand %d is not an immediate."}, + {ERROR_IMM_OVERFLOW, "Operand %d immediate is overflow."}, + {ERROR_IMM_POWER, "immediate %d is not a power of two"}, + {ERROR_JMPIX_OVER_RANGE, "The second operand must be 16/24/32/40"}, + {ERROR_EXP_CREG, "Operand %d error: control register is expected."}, + {ERROR_EXP_GREG, "Operand %d error: general register is expected."}, + {ERROR_EXP_CONSTANT, "Operand %d error: constant is expected."}, + {ERROR_EXP_EVEN_FREG, "Operand %d error: even float register is expected."}, + {ERROR_RELOC_ILLEGAL, "@%s reloc is not supported"}, + {ERROR_MISSING_OPERAND, "Operand %d is missing."}, + {ERROR_MISSING_COMMA, "Missing ','"}, + {ERROR_MISSING_LBRACKET, "Missing '('"}, + {ERROR_MISSING_RBRACKET, "Missing ')'"}, + {ERROR_MISSING_LSQUARE_BRACKETS, "Missing '['"}, + {ERROR_MISSING_RSQUARE_BRACKETS, "Missing ']'"}, + {ERROR_MISSING_LANGLE_BRACKETS, "Missing '<'"}, + {ERROR_MISSING_RANGLE_BRACKETS, "Missing '>'"}, + {ERROR_OFFSET_UNALIGNED, "Operand %d is unaligned. It must be %d aligned!"}, + {ERROR_BAD_END, "Operands mismatch, it has a bad end: %s"}, + {ERROR_UNDEFINE, NULL}, + {ERROR_CPREG_ILLEGAL, "Operand %d illegal, expect a cpreg(cpr0-cpr63)."}, + {ERROR_OPCODE_PSRBIT, "The operands must be 'ie'/'ee'/'fe'."}, + {ERROR_OPERANDS_ILLEGAL, "Operands mismatch: %s."}, + {ERROR_OPERANDS_NUMBER, "Operands number mismatch, %d operands expected."}, + {ERROR_OPCODE_ILLEGAL, "The instruction is not recognized."}, + {WARNING_OPTIONS, "Option %s is not support in %s."}, + {WARNING_IDLY, "idly %d is encoded to: idly 4 "}, + {ERROR_NONE, "There is no error."}, +}; + +static int do_pic = 0; /* for jbr/jbf/jbt relax jmpi reloc. */ +static int do_pff = -1; /* for insert two br ahead of literals. */ +static int do_force2bsr = -1; /* for jbsr->bsr. */ +static int do_jsri2bsr = 1; /* for jsri->bsr. */ +static int do_nolrw = 0; /* lrw to movih & ori, only for V2. */ +static int do_long_jump = -1; /* control if jbf,jbt,jbr relax to jmpi. */ +static int do_extend_lrw = -1; /* delete bsr16 in both two options, + add btesti16, lrw offset +1 in -melrw. */ +static int do_func_dump = 0; /* dump literals after every function. */ +static int do_br_dump = 1; /* work for -mabr/-mno-abr, control the literals dump. */ +static int do_intr_stack = -1; /* control interrupt stack module, 801&802&803 + default on, 807&810, default off. */ + +#ifdef INCLUDE_BRANCH_STUB +static int do_use_branchstub = -1; +#else +static int do_use_branchstub = 0; +#endif + +/* These are only used for options parsing. Values are bitmasks and are + OR'ed into the processor flag bits in md_begin. */ +static int do_opt_mmp = 0; +static int do_opt_mcp = 0; +static int do_opt_mcache = 0; +static int do_opt_msecurity = 0; +static int do_opt_mhard_float = 0; +static int do_opt_mtrust = 0; +static int do_opt_mdsp = 0; +static int do_opt_medsp = 0; +static int do_opt_mvdsp = 0; + +const relax_typeS *md_relax_table = NULL; +struct literal *literal_insn_offset; +static struct literal litpool[MAX_POOL_SIZE]; +static unsigned poolsize = 0; +static unsigned poolnumber = 0; +static unsigned long poolspan = 0; +static unsigned int SPANPANIC; +static unsigned int SPANCLOSE; +static unsigned int SPANEXIT; + +static stack_size_entry *all_stack_size_data = NULL; +static stack_size_entry **last_stack_size_data = &all_stack_size_data; + +/* Control by ".no_literal_dump N" + * 1 : don't dump literal pool between insn1 and insnN+1 + * 0 : do nothing. */ +static int do_noliteraldump = 0; + +/* Label for current pool. */ +static symbolS * poolsym; +static char poolname[8]; + +static bfd_boolean mov_r1_before; +static bfd_boolean mov_r1_after; + +const relax_typeS csky_relax_table [] = +{ + /* C-SKY V1 relax table. */ + {0, 0, 0, 0}, /* RELAX_NONE */ + {0, 0, 0, 0}, /* RELAX_OVERFLOW */ + {0, 0, 0, 0}, + {0, 0, 0, 0}, + + /* COND_JUMP */ + { 0, 0, 0, 0 }, /* UNDEF_DISP */ + { 2048, -2046, C12_LEN, C (COND_JUMP, DISP32) }, /* DISP12 */ + { 0, 0, C32_LEN, 0 }, /* DISP32 */ + { 0, 0, C32_LEN, 0 }, /* UNDEF_WORD_DISP */ + + /* UNCD_JUMP */ + { 0, 0, 0, 0 }, /* UNDEF_DISP */ + { 2048, -2046, U12_LEN, C (UNCD_JUMP, DISP32) }, /* DISP12 */ + { 0, 0, U32_LEN, 0 }, /* DISP32 */ + { 0, 0, U32_LEN, 0 }, /* UNDEF_WORD_DISP */ + + /* COND_JUMP_PIC */ + { 0, 0, 0, 0 }, /* UNDEF_DISP */ + { 2048, -2046, C12_LEN, C (COND_JUMP_PIC, DISP32) }, /* DISP12 */ + { 0, 0, C32_LEN_PIC, 0 }, /* DISP32 */ + { 0, 0, C32_LEN_PIC, 0 }, /* UNDEF_WORD_DISP */ + + /* UNCD_JUMP_PIC */ + { 0, 0, 0, 0 }, /* UNDEF_DISP */ + { 2048, -2046, U12_LEN, C (UNCD_JUMP_PIC, DISP32) }, /* DISP12 */ + { 0, 0, U32_LEN_PIC, 0 }, /* DISP32 */ + { 0, 0, U32_LEN_PIC, 0 }, /* UNDEF_WORD_DISP */ + + /* C-SKY V2 relax table. */ + /* forward backward length more */ + { 1 KB - 2, -1 KB, COND_DISP10_LEN, COND_DISP16 }, /* COND_DISP10 */ + { 64 KB - 2, -64 KB, COND_DISP16_LEN, RELAX_OVERFLOW }, /* COND_DISP16 */ + + { 1 KB - 2, -1 KB, SCOND_DISP10_LEN, SCOND_DISP16 }, /* SCOND_DISP10 */ + { 64 KB - 2, -64 KB, SCOND_DISP16_LEN, RELAX_OVERFLOW }, /* SCOND_DISP16 */ + + { 1 KB - 2, -1 KB, UNCD_DISP10_LEN, UNCD_DISP16 }, /* UNCD_DISP10 */ + { 64 KB - 2, -64 KB, UNCD_DISP16_LEN, RELAX_OVERFLOW }, /* UNCD_DISP16 */ + + { 1 KB - 2, -1 KB, JCOND_DISP10_LEN, JCOND_DISP16 }, /* JCOND_DISP10 */ + { 64 KB - 2, -64 KB, JCOND_DISP16_LEN, JCOND_DISP32 }, /* JCOND_DISP16 */ + { 0, 0, JCOND_DISP32_LEN, RELAX_NONE }, /* JCOND_DISP32 */ + + { 1 KB - 2, -1 KB, JUNCD_DISP10_LEN, JUNCD_DISP16 }, /* JUNCD_DISP10 */ + { 64 KB - 2, -64 KB, JUNCD_DISP16_LEN, JUNCD_DISP32 }, /* JUNCD_DISP16 */ + { 0, 0, JUNCD_DISP32_LEN, RELAX_NONE }, /* JUNCD_DISP32 */ + + { 64 KB - 2, -64 KB, JCOMPZ_DISP16_LEN, JCOMPZ_DISP32 }, /* JCOMPZ_DISP16 */ + { 0, 0, JCOMPZ_DISP32_LEN, RELAX_NONE }, /* JCOMPZ_DISP32 */ + + { 64 MB - 2, -64 MB, BSR_DISP26_LEN, RELAX_OVERFLOW }, /* BSR_DISP26 */ + + { 508, 0, LRW_DISP7_LEN, LRW_DISP16 }, /* LRW_DISP7 */ + { 1016, 0, LRW_DISP7_LEN, LRW_DISP16 }, /* LRW2_DISP8 */ + { 64 KB, 0, LRW_DISP16_LEN, RELAX_OVERFLOW }, /* LRW_DISP16 */ + +}; + +static void csky_write_insn (char *ptr, valueT use, int nbytes); +void md_number_to_chars (char * buf, valueT val, int n); +long md_pcrel_from_section (fixS * fixP, segT seg); + +/* C-SKY architecture table. */ +const struct csky_arch_info csky_archs[] = +{ + {"ck510", CSKY_ARCH_510, bfd_mach_ck510}, + {"ck610", CSKY_ARCH_610, bfd_mach_ck610}, + {"ck801", CSKY_ARCH_801, bfd_mach_ck801}, + {"ck802", CSKY_ARCH_802, bfd_mach_ck802}, + {"ck803", CSKY_ARCH_803, bfd_mach_ck803}, +#define CSKY_ARCH_807_BASE CSKY_ARCH_807 | CSKY_ARCH_DSP +#define CSKY_ARCH_810_BASE CSKY_ARCH_810 | CSKY_ARCH_DSP + {"ck807", CSKY_ARCH_807_BASE, bfd_mach_ck807}, + {"ck810", CSKY_ARCH_810_BASE, bfd_mach_ck810}, + {NULL, 0, 0} +}; + +/* C-SKY cpus table. */ +const struct csky_cpu_info csky_cpus[] = +{ + /* CK510 series. */ +#define CSKYV1_ISA_DSP CSKY_ISA_DSP | CSKY_ISA_MAC_DSP + {"ck510", CSKY_ARCH_510, CSKYV1_ISA_E1}, + {"ck510e", CSKY_ARCH_510 | CSKY_ARCH_DSP, CSKYV1_ISA_E1 | CSKYV1_ISA_DSP}, + {"ck520", CSKY_ARCH_510 | CSKY_ARCH_MAC, CSKYV1_ISA_E1 | CSKY_ISA_MAC | CSKY_ISA_MAC_DSP}, + +#define CSKY_ISA_610 CSKYV1_ISA_E1 | CSKY_ISA_CP + /* CK610 series. */ + {"ck610", CSKY_ARCH_610, CSKY_ISA_610}, + {"ck610e", CSKY_ARCH_610 | CSKY_ARCH_DSP, CSKY_ISA_610 | CSKYV1_ISA_DSP}, + {"ck610f", CSKY_ARCH_610 | CSKY_ARCH_FLOAT, CSKY_ISA_610 | CSKY_ISA_FLOAT_E1}, + {"ck610ef", CSKY_ARCH_610 | CSKY_ARCH_FLOAT | CSKY_ARCH_DSP, CSKY_ISA_610 | CSKY_ISA_FLOAT_E1 | CSKYV1_ISA_DSP}, + {"ck610fe", CSKY_ARCH_610 | CSKY_ARCH_FLOAT | CSKY_ARCH_DSP, CSKY_ISA_610 | CSKY_ISA_FLOAT_E1 | CSKYV1_ISA_DSP}, + {"ck620", CSKY_ARCH_610 | CSKY_ARCH_MAC, CSKY_ISA_610 | CSKY_ISA_MAC | CSKY_ISA_MAC_DSP}, + + /* CK801 series. */ +#define CSKY_ISA_801 CSKYV2_ISA_E1 +#define CSKYV2_ISA_DSP (CSKY_ISA_DSP | CSKY_ISA_DSP_1E2) + {"ck801", CSKY_ARCH_801, CSKY_ISA_801}, + {"ck801t", CSKY_ARCH_801, CSKY_ISA_801 | CSKY_ISA_TRUST}, + + /* CK802 series. */ +#define CSKY_ISA_802 (CSKY_ISA_801 | CSKYV2_ISA_1E2 | CSKY_ISA_NVIC) + {"ck802", CSKY_ARCH_802, CSKY_ISA_802}, + {"ck802j", CSKY_ARCH_802 | CSKY_ARCH_JAVA, CSKY_ISA_802 | CSKY_ISA_JAVA}, + {"ck802t", CSKY_ARCH_802, CSKY_ISA_802 | CSKY_ISA_TRUST}, + + /* CK803 series. */ +#define CSKY_ISA_803 (CSKY_ISA_802 | CSKYV2_ISA_2E3 | CSKY_ISA_MP) +#define CSKY_ISA_803R1 (CSKY_ISA_803 | CSKYV2_ISA_3E3R1) +#define CSKY_ISA_FLOAT_803 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E3) + {"ck803", CSKY_ARCH_803, CSKY_ISA_803 }, + {"ck803h", CSKY_ARCH_803, CSKY_ISA_803 }, + {"ck803t", CSKY_ARCH_803, CSKY_ISA_803 | CSKY_ISA_TRUST}, + {"ck803ht", CSKY_ARCH_803, CSKY_ISA_803 | CSKY_ISA_TRUST}, + {"ck803f", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKY_ISA_FLOAT_803}, + {"ck803fh", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKY_ISA_FLOAT_803}, + {"ck803e", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803 | CSKYV2_ISA_DSP}, + {"ck803eh", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803 | CSKYV2_ISA_DSP}, + {"ck803et", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803 | CSKYV2_ISA_DSP | CSKY_ISA_TRUST}, + {"ck803eht", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803 | CSKYV2_ISA_DSP | CSKY_ISA_TRUST}, + {"ck803ef", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_803}, + {"ck803efh", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_803}, + {"ck803ft", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST}, + {"ck803eft", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST}, + {"ck803efht", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST}, + {"ck803r1", CSKY_ARCH_803, CSKY_ISA_803R1 }, + {"ck803hr1", CSKY_ARCH_803, CSKY_ISA_803R1 }, + {"ck803tr1", CSKY_ARCH_803, CSKY_ISA_803R1 | CSKY_ISA_TRUST}, + {"ck803htr1", CSKY_ARCH_803, CSKY_ISA_803R1 | CSKY_ISA_TRUST}, + {"ck803fr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803}, + {"ck803fhr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803}, + {"ck803er1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE}, + {"ck803ehr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE}, + {"ck803etr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST}, + {"ck803ehtr1", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_TRUST}, + {"ck803efr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803}, + {"ck803efhr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803}, + {"ck803ftr1", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST}, + {"ck803eftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST}, + {"ck803ehftr1", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_DSP_ENHANCE | CSKY_ISA_FLOAT_803 | CSKY_ISA_TRUST}, + + {"ck803s", CSKY_ARCH_803, CSKY_ISA_803R1 }, + {"ck803se", CSKY_ARCH_803 | CSKY_ARCH_DSP, CSKY_ISA_803R1 | CSKYV2_ISA_DSP}, + {"ck803sj", CSKY_ARCH_803 | CSKY_ARCH_JAVA, CSKY_ISA_803R1 | CSKY_ISA_JAVA}, + {"ck803sf", CSKY_ARCH_803 | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKY_ISA_FLOAT_803}, + {"ck803sef", CSKY_ARCH_803 | CSKY_ARCH_DSP | CSKY_ARCH_FLOAT, CSKY_ISA_803R1 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_803}, + {"ck803st", CSKY_ARCH_803, CSKY_ISA_803R1 | CSKY_ISA_TRUST}, + + /* CK807 series. */ +#define CSKY_ISA_807 (CSKY_ISA_803 | CSKYV2_ISA_3E7 | CSKY_ISA_DSP | CSKY_ISA_MP_1E2 | CSKY_ISA_CACHE) +#define CSKY_ISA_FLOAT_807 (CSKY_ISA_FLOAT_803 | CSKY_ISA_FLOAT_3E4 | CSKY_ISA_FLOAT_1E2) + {"ck807e", CSKY_ARCH_807_BASE, CSKY_ISA_807 | CSKYV2_ISA_DSP}, + {"ck807ef", CSKY_ARCH_807_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_807 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_807}, + {"ck807", CSKY_ARCH_807_BASE, CSKY_ISA_807 | CSKYV2_ISA_DSP}, + {"ck807f", CSKY_ARCH_807_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_807 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_807}, + + /* CK810 series. */ +#define CSKY_ISA_810 (CSKY_ISA_807 | CSKYV2_ISA_7E10) +#define CSKY_ISA_FLOAT_810 (CSKY_ISA_FLOAT_E1 | CSKY_ISA_FLOAT_1E2) + {"ck810e", CSKY_ARCH_810_BASE, CSKY_ISA_810 | CSKYV2_ISA_DSP}, + {"ck810et", CSKY_ARCH_810_BASE, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_TRUST}, + {"ck810ef", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_810}, + {"ck810eft", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST}, + {"ck810", CSKY_ARCH_810_BASE, CSKY_ISA_810 | CSKYV2_ISA_DSP}, + {"ck810v", CSKY_ARCH_810_BASE, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP}, + {"ck810f", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_FLOAT_810}, + {"ck810t", CSKY_ARCH_810_BASE, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_TRUST}, + {"ck810tv", CSKY_ARCH_810_BASE, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_TRUST}, + {"ck810ft", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST}, + {"ck810ftv", CSKY_ARCH_810_BASE | CSKY_ARCH_FLOAT, CSKY_ISA_810 | CSKYV2_ISA_DSP | CSKY_ISA_VDSP | CSKY_ISA_FLOAT_810 | CSKY_ISA_TRUST}, + + {NULL, 0, 0} +}; + +int md_short_jump_size = 2; +int md_long_jump_size = 4; + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful. */ +const char comment_chars[] = "#"; + +/* This array holds the chars that only start a comment at the beginning of + a line. If the line seems to have the form '# 123 filename' + .line and .file directives will appear in the pre-processed output. */ +/* Note that input_file.c hand checks for '#' at the beginning of the + first line of the input file. This is because the compiler outputs + #NO_APP at the beginning of its output. */ +/* Also note that comments like this one will always work. */ +const char line_comment_chars[] = "#"; + +const char line_separator_chars[] = ";"; + +/* Chars that can be used to separate mant + from exp in floating point numbers. */ +const char EXP_CHARS[] = "eE"; + +/* Chars that mean this number is a floating point constant. + As in 0f12.456 + or 0d1.2345e12 */ + +const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; + +const char *md_shortopts = ""; + +struct option md_longopts[] = { +#define OPTION_MARCH (OPTION_MD_BASE + 0) + {"march", required_argument, NULL, OPTION_MARCH}, +#define OPTION_MCPU (OPTION_MD_BASE + 1) + {"mcpu", required_argument, NULL, OPTION_MCPU}, + + /* Remaining options just set boolean flags. */ + {"EL", no_argument, &target_big_endian, 0}, + {"mlittle-endian", no_argument, &target_big_endian, 0}, + {"EB", no_argument, &target_big_endian, 1}, + {"mbig-endian", no_argument, &target_big_endian, 1}, + {"fpic", no_argument, &do_pic, 1}, + {"pic", no_argument, &do_pic, 1}, + {"mljump", no_argument, &do_long_jump, 1}, + {"mno-ljump", no_argument, &do_long_jump, 0}, + {"force2bsr", no_argument, &do_force2bsr, 1}, + {"mforce2bsr", no_argument, &do_force2bsr, 1}, + {"no-force2bsr", no_argument, &do_force2bsr, 0}, + {"mno-force2bsr", no_argument, &do_force2bsr, 0}, + {"jsri2bsr", no_argument, &do_jsri2bsr, 1}, + {"mjsri2bsr", no_argument, &do_jsri2bsr, 1}, + {"no-jsri2bsr", no_argument, &do_jsri2bsr, 0}, + {"mno-jsri2bsr", no_argument, &do_jsri2bsr, 0}, + {"mnolrw", no_argument, &do_nolrw, 1}, + {"mno-lrw", no_argument, &do_nolrw, 1}, + {"melrw", no_argument, &do_extend_lrw, 1}, + {"mno-elrw", no_argument, &do_extend_lrw, 0}, + {"mlaf", no_argument, &do_func_dump, 1}, + {"mliterals-after-func", no_argument, &do_func_dump, 1}, + {"mno-laf", no_argument, &do_func_dump, 0}, + {"mno-literals-after-func", no_argument, &do_func_dump, 0}, + {"mlabr", no_argument, &do_br_dump, 1}, + {"mliterals-after-br", no_argument, &do_br_dump, 1}, + {"mno-labr", no_argument, &do_br_dump, 0}, + {"mnoliterals-after-br", no_argument, &do_br_dump, 0}, + {"mistack", no_argument, &do_intr_stack, 1}, + {"mno-istack", no_argument, &do_intr_stack, 0}, +#ifdef INCLUDE_BRANCH_STUB + {"mbranch-stub", no_argument, &do_use_branchstub, 1}, + {"mno-branch-stub", no_argument, &do_use_branchstub, 0}, +#endif + {"mhard-float", no_argument, &do_opt_mhard_float, CSKY_ARCH_FLOAT}, + {"mmp", no_argument, &do_opt_mmp, CSKY_ARCH_MP}, + {"mcp", no_argument, &do_opt_mcp, CSKY_ARCH_CP}, + {"mcache", no_argument, &do_opt_mcache, CSKY_ARCH_CACHE}, + {"msecurity", no_argument, &do_opt_msecurity, CSKY_ARCH_MAC}, + {"mtrust", no_argument, &do_opt_mtrust, CSKY_ISA_TRUST}, + {"mdsp", no_argument, &do_opt_mdsp, CSKY_DSP_FLAG_V1}, + {"medsp", no_argument, &do_opt_medsp, CSKY_DSP_FLAG_V2}, + {"mvdsp", no_argument, &do_opt_mvdsp, CSKY_ISA_VDSP}, +}; + +size_t md_longopts_size = sizeof (md_longopts); + +static struct csky_insn_info csky_insn; + +static struct hash_control *csky_opcodes_hash; +static struct hash_control *csky_macros_hash; + +static struct csky_macro_info v1_macros_table[] = +{ + {"idly", 1, CSKYV1_ISA_E1, csky_idly}, + {"rolc", 2, CSKYV1_ISA_E1, csky_rolc}, + {"rotlc", 2, CSKYV1_ISA_E1, csky_rolc}, + {"sxtrb0", 2, CSKYV1_ISA_E1, csky_sxtrb}, + {"sxtrb1", 2, CSKYV1_ISA_E1, csky_sxtrb}, + {"sxtrb2", 2, CSKYV1_ISA_E1, csky_sxtrb}, + {"movtf", 3, CSKYV1_ISA_E1, csky_movtf}, + {"addc64", 3, CSKYV1_ISA_E1, csky_addc64}, + {"subc64", 3, CSKYV1_ISA_E1, csky_subc64}, + {"or64", 3, CSKYV1_ISA_E1, csky_or64}, + {"xor64", 3, CSKYV1_ISA_E1, csky_xor64}, + {NULL,0,0,0} +}; + +static struct csky_macro_info v2_macros_table[] = +{ + {"neg", 1, CSKYV2_ISA_E1, csky_neg}, + {"rsubi", 2, CSKYV2_ISA_1E2, csky_rsubi}, + {"incf", 1, CSKYV2_ISA_1E2, csky_arith}, + {"inct", 1, CSKYV2_ISA_1E2, csky_arith}, + {"decf", 1, CSKYV2_ISA_2E3, csky_arith}, + {"decgt", 1, CSKYV2_ISA_2E3, csky_arith}, + {"declt", 1, CSKYV2_ISA_2E3, csky_arith}, + {"decne", 1, CSKYV2_ISA_1E2, csky_decne}, + {"dect", 1, CSKYV2_ISA_1E2, csky_arith}, + {"lslc", 1, CSKYV2_ISA_1E2, csky_arith}, + {"lsrc", 1, CSKYV2_ISA_1E2, csky_arith}, + {"xsr", 1, CSKYV2_ISA_1E2, csky_arith}, + {NULL,0,0,0} +}; + +/* For option -mnolrw, replace lrw by movih & ori. */ +static struct csky_macro_info v2_lrw_macro_opcode = + {"lrw", 2, CSKYV2_ISA_1E2, csky_lrw}; + +/* This function is used to show errors or warnings. */ + +static void +csky_show_error (enum error_number err, int idx, void *arg1, void *arg2) +{ + if (err == ERROR_NONE) + return; + + switch (err) + { + case ERROR_REG_LIST: + case ERROR_OPCODE_PSRBIT: + case ERROR_OPCODE_ILLEGAL: + case ERROR_JMPIX_OVER_RANGE: + case ERROR_MISSING_COMMA: + case ERROR_MISSING_LBRACKET: + case ERROR_MISSING_RBRACKET: + case ERROR_MISSING_LSQUARE_BRACKETS: + case ERROR_MISSING_RSQUARE_BRACKETS: + case ERROR_MISSING_LANGLE_BRACKETS: + case ERROR_MISSING_RANGLE_BRACKETS: + /* Add NULL to fix warnings. */ + as_bad (_(err_formats[err].fmt), NULL); + break; + case ERROR_CREG_ILLEGAL: + case ERROR_GREG_ILLEGAL: + case ERROR_IMM_ILLEGAL: + case ERROR_IMM_OVERFLOW: + case ERROR_EXP_CREG: + case ERROR_EXP_GREG: + case ERROR_EXP_CONSTANT: + case ERROR_EXP_EVEN_FREG: + case ERROR_MISSING_OPERAND: + case ERROR_CPREG_ILLEGAL: + as_bad (_(err_formats[err].fmt), idx); + break; + case ERROR_OPERANDS_NUMBER: + case ERROR_IMM_POWER: + as_bad (_(err_formats[err].fmt), (long)arg1); + break; + + case ERROR_OFFSET_UNALIGNED: + as_bad (_(err_formats[err].fmt), idx, (long)arg1); + break; + case ERROR_RELOC_ILLEGAL: + case ERROR_BAD_END: + case ERROR_OPERANDS_ILLEGAL: + as_bad (_(err_formats[err].fmt), (char *)arg1); + break; + case ERROR_REG_OVER_RANGE: + as_bad (_(err_formats[err].fmt), idx, (long) arg1); + break; + case ERROR_802J_REG_OVER_RANGE: + case ERROR_REG_FORMAT: + as_bad (_(err_formats[err].fmt), idx, (char *)arg1); + break; + case ERROR_UNDEFINE: + /* Add NULL to fix warnings. */ + as_bad ((char *)arg1, NULL); + break; + case WARNING_IDLY: + as_warn (_(err_formats[err].fmt), (long)arg1); + break; + case WARNING_OPTIONS: + as_warn (_(err_formats[err].fmt), (char *)arg1, (char *)arg2); + break; + default: + break; + } +} + +/* Handle errors in branch relaxation. */ + +static void +csky_branch_report_error (const char* file, unsigned int line, + symbolS* sym, offsetT val) +{ + as_bad_where (file ? file : _("unknown"), + line, + _("pcrel offset for branch to %s too far (0x%lx)"), + sym ? S_GET_NAME (sym) : _("<unknown>"), + (long) val); +} + +/* Set appropriate flags for the cpu matching STR. */ + +static void +parse_cpu (const char *str) +{ + int i = 0; + + for (; csky_cpus[i].name != NULL; i++) + if (strcasecmp (str, csky_cpus[i].name) == 0) + { + mach_flag |= csky_cpus[i].mach_flag; + isa_flag = csky_cpus[i].isa_flag; + other_flag |= (csky_cpus[i].mach_flag & ~CSKY_ARCH_MASK); + return; + } + as_bad (_("unknown cpu `%s'"), str); +} + +/* Set appropriate flags for the arch matching STR. */ + +static void +parse_arch (const char *str) +{ + int i = 0; + for (; csky_archs[i].name != NULL; i++) + if (strcasecmp (str, csky_archs[i].name) == 0) + { + arch_flag |= csky_archs[i].arch_flag; + return; + } + as_bad (_("unknown architecture `%s'"), str); +} + + +#ifdef OBJ_ELF +/* Implement the TARGET_FORMAT macro. */ + +const char * +elf32_csky_target_format (void) +{ + return (target_big_endian + ? "elf32-csky-big" + : "elf32-csky-little"); +} +#endif + +/* Turn an integer of n bytes (in val) into a stream of bytes appropriate + for use in the a.out file, and stores them in the array pointed to by buf. + This knows about the endian-ness of the target machine and does + THE RIGHT THING, whatever it is. Possible values for n are 1 (byte) + 2 (short) and 4 (long) Floating numbers are put out as a series of + LITTLENUMS (shorts, here at least). */ + +void +md_number_to_chars (char * buf, valueT val, int n) +{ + if (target_big_endian) + number_to_chars_bigendian (buf, val, n); + else + number_to_chars_littleendian (buf, val, n); +} + +/* Get a log2(val). */ + +static int +csky_log_2 (unsigned int val) +{ + int log = -1; + if ((val & (val - 1)) == 0) + for (; val; val >>= 1) + log ++; + else + csky_show_error (ERROR_IMM_POWER, 0, (void *)(long)val, NULL); + return log; +} + +/* Output one instruction to the buffer at PTR. */ + +static void +csky_write_insn (char *ptr, valueT use, int nbytes) +{ + if (nbytes == 2) + md_number_to_chars (ptr, use, nbytes); + else /* 32-bit instruction. */ + { + /* Significant figures are in low bits. */ + md_number_to_chars (ptr, use >> 16, 2); + md_number_to_chars (ptr + 2, use & 0xFFFF, 2); + } +} + +/* Read an NBYTES instruction from the buffer at PTR. NBYTES should + be either 2 or 4. This function is used in branch relaxation. */ + +static valueT +csky_read_insn (char *ptr, int nbytes) +{ + unsigned char *uptr = (unsigned char *)ptr; + valueT v = 0; + int lo, hi; /* hi/lo byte index in binary stream. */ + + if (target_big_endian) + { + hi = 0; + lo = 1; + } + else + { + hi = 1; + lo = 0; + } + v = uptr[lo] | (uptr[hi] << 8); + if (nbytes == 4) + { + v <<= 16; + v |= uptr[lo + 2] | (uptr[hi + 2] << 8); + } + return v; +} + +/* Construct a label name into S from the 3-character prefix P and + number N formatted as a 4-digit hex number. */ + +static void +make_internal_label (char *s, const char *p, int n) +{ + static const char hex[] = "0123456789ABCDEF"; + + s[0] = p[0]; + s[1] = p[1]; + s[2] = p[2]; + s[3] = hex[(n >> 12) & 0xF]; + s[4] = hex[(n >> 8) & 0xF]; + s[5] = hex[(n >> 4) & 0xF]; + s[6] = hex[(n) & 0xF]; + s[7] = 0; +} + +/* md_operand is a no-op on C-SKY; we do everything elsewhere. */ + +void +md_operand (expressionS *expressionP ATTRIBUTE_UNUSED) +{ + return; +} + +/* Under ELF we need to default _GLOBAL_OFFSET_TABLE. + Otherwise we have no need to default values of symbols. */ + +symbolS * +md_undefined_symbol (char *name ATTRIBUTE_UNUSED) +{ +#ifdef OBJ_ELF + /* TODO: */ +#endif + return NULL; +} + +/* Use IEEE format for floating-point constants. */ + +const char * +md_atof (int type, char *litP, int *sizeP) +{ + return ieee_md_atof (type, litP, sizeP, target_big_endian); +} + +/* Print option help to FP. */ + +void +md_show_usage (FILE *fp) +{ + int i, n; + const int margin = 48; + + fprintf (fp, _("C-SKY assembler options:\n")); + + fprintf (fp, _("\ + -march=ARCH select architecture ARCH:")); + for (i = 0, n = margin; csky_archs[i].name != NULL; i++) + { + int l = strlen (csky_archs[i].name); + if (n + l >= margin) + { + fprintf (fp, "\n\t\t\t\t"); + n = l; + } + else + { + fprintf (fp, " "); + n += l + 1; + } + fprintf (fp, "%s", csky_archs[i].name); + } + fprintf (fp, "\n"); + + fprintf (fp, _("\ + -mcpu=CPU select processor CPU:")); + for (i = 0, n = margin; csky_cpus[i].name != NULL; i++) + { + int l = strlen (csky_cpus[i].name); + if (n + l >= margin) + { + fprintf (fp, "\n\t\t\t\t"); + n = l; + } + else + { + fprintf (fp, " "); + n += l + 1; + } + fprintf (fp, "%s", csky_cpus[i].name); + } + fprintf (fp, "\n"); + + fprintf (fp, _("\ + -EL -mlittle-endian generate little-endian output\n")); + fprintf (fp, _("\ + -EB -mbig-endian generate big-endian output\n")); + fprintf (fp, _("\ + -fpic -pic generate position-independent code\n")); + + fprintf (fp, _("\ + -mljump transform jbf, jbt, jbr to jmpi (CK800 only)\n")); + fprintf (fp, _("\ + -mno-ljump\n")); + +#ifdef INCLUDE_BRANCH_STUB + fprintf (fp, _("\ + -mbranch-stub enable branch stubs for PC-relative calls\n")); + fprintf (fp, _("\ + -mno-branch-stub\n")); +#endif + + fprintf (fp, _("\ + -force2bsr -mforce2bsr transform jbsr to bsr\n")); + fprintf (fp, _("\ + -no-force2bsr -mno-force2bsr\n")); + fprintf (fp, _("\ + -jsri2bsr -mjsri2bsr transform jsri to bsr\n")); + fprintf (fp, _("\ + -no-jsri2bsr -mno-jsri2bsr\n")); + + fprintf (fp, _("\ + -mnolrw -mno-lrw implement lrw as movih + ori\n")); + fprintf (fp, _("\ + -melrw enable extended lrw (CK800 only)\n")); + fprintf (fp, _("\ + -mno-elrw\n")); + + fprintf (fp, _("\ + -mlaf -mliterals-after-func emit literals after each function\n")); + fprintf (fp, _("\ + -mno-laf -mno-literals-after-func\n")); + fprintf (fp, _("\ + -mlabr -mliterals-after-br emit literals after branch instructions\n")); + fprintf (fp, _("\ + -mno-labr -mnoliterals-after-br\n")); + + fprintf (fp, _("\ + -mistack enable interrupt stack instructions\n")); + fprintf (fp, _("\ + -mno-istack\n")); + + fprintf (fp, _("\ + -mhard-float enable hard float instructions\n")); + fprintf (fp, _("\ + -mmp enable multiprocessor instructions\n")); + fprintf (fp, _("\ + -mcp enable coprocessor instructions\n")); + fprintf (fp, _("\ + -mcache enable cache prefetch instruction\n")); + fprintf (fp, _("\ + -msecurity enable security instructions\n")); + fprintf (fp, _("\ + -mtrust enable trust instructions\n")); + fprintf (fp, _("\ + -mdsp enable DSP instructions\n")); + fprintf (fp, _("\ + -medsp enable enhanced DSP instructions\n")); + fprintf (fp, _("\ + -mvdsp enable vector DSP instructions\n")); +} + +/* Target-specific initialization and option handling. */ + +void +md_begin (void) +{ + unsigned int bfd_mach_flag = 0; + struct csky_opcode const *opcode; + struct csky_macro_info const *macro; + struct csky_arch_info const *p_arch; + struct csky_cpu_info const *p_cpu; + unsigned int flags = (other_flag | do_opt_mmp | do_opt_mcp | do_opt_mcache + | do_opt_msecurity | do_opt_mhard_float); + dsp_flag |= do_opt_mdsp | do_opt_medsp; + isa_flag |= do_opt_mtrust | do_opt_mvdsp; + + if (dsp_flag) + flags |= CSKY_ARCH_DSP; + + if (mach_flag != 0) + { + if ((mach_flag & CSKY_ARCH_MASK) != arch_flag && arch_flag != 0) + as_warn (_("-mcpu conflict with -march option, using -mcpu")); + if ((mach_flag & ~CSKY_ARCH_MASK) != flags && flags != 0) + as_warn (_("-mcpu conflict with other model parameters, using -mcpu")); + } + else if (arch_flag != 0) + mach_flag |= arch_flag | flags; + else + { +#ifdef TARGET_WITH_CPU + int i = 0; + for (; csky_cpus[i].name != NULL; i++) + { + if (strcmp (TARGET_WITH_CPU, csky_cpus[i].name) == 0) + { + mach_flag |= csky_cpus[i].mach_flag; + isa_flag = csky_cpus[i].isa_flag; + break; + } + } +#else +#if _CSKY_ABI==1 + mach_flag |= CSKY_ARCH_610 | flags; +#else + mach_flag |= CSKY_ARCH_810_BASE | flags; +#endif +#endif + } + + if (IS_CSKY_ARCH_610 (mach_flag) || IS_CSKY_ARCH_510 (mach_flag)) + { + if ((mach_flag & CSKY_ARCH_MP) && (mach_flag & CSKY_ARCH_MAC)) + as_fatal ("520/620 conflicts with -mmp option"); + else if ((mach_flag & CSKY_ARCH_MP) && (mach_flag & CSKY_ARCH_DSP)) + as_fatal ("510e/610e conflicts with -mmp option"); + else if ((mach_flag & CSKY_ARCH_DSP) && (mach_flag & CSKY_ARCH_MAC)) + as_fatal ("520/620 conflicts with 510e/610e or -mdsp option"); + } + if (IS_CSKY_ARCH_510 (mach_flag) && (mach_flag & CSKY_ARCH_FLOAT)) + { + mach_flag = (mach_flag & (~CSKY_ARCH_MASK)); + mach_flag |= CSKY_ARCH_610; + } + + /* Find bfd_mach_flag, it will set to bfd backend data. */ + for (p_arch = csky_archs; p_arch->arch_flag != 0; p_arch++) + if ((mach_flag & CSKY_ARCH_MASK) == (p_arch->arch_flag & CSKY_ARCH_MASK)) + { + bfd_mach_flag = p_arch->bfd_mach_flag; + break; + } + + /* Find isa_flag. */ + for (p_cpu = csky_cpus; p_cpu->mach_flag != 0; p_cpu++) + if ((mach_flag & CPU_ARCH_MASK) == p_cpu->mach_flag) + { + isa_flag |= p_cpu->isa_flag; + break; + } + + /* Check if -mdsp and -medsp conflict. If cpu is ck803, we will + use enhanced dsp instruction. Otherwise, we will use normal dsp. */ + if (dsp_flag) + { + if (IS_CSKY_ARCH_803 (mach_flag)) + { + /* In 803, dspv1 is conflict with dspv2. We keep dspv2. */ + if ((dsp_flag & CSKY_DSP_FLAG_V1) && (dsp_flag & CSKY_DSP_FLAG_V2)) + as_warn (_("option -mdsp conflicts with -medsp, only enabling -medsp")); + isa_flag &= ~(CSKY_ISA_MAC_DSP | CSKY_ISA_DSP); + isa_flag |= CSKY_ISA_DSP_ENHANCE; + } + else + { + isa_flag &= ~CSKY_ISA_DSP_ENHANCE; + as_warn (_("-medsp option is only supported by ck803s, ignoring -medsp")); + } + ; + } + + if (do_use_branchstub == -1) + do_use_branchstub = !IS_CSKY_ARCH_V1 (mach_flag); + else if (do_use_branchstub == 1) + { + if (IS_CSKY_ARCH_V1 (mach_flag)) + { + as_warn (_("C-SKY ABI v1 (ck510/ck610) does not support -mbranch-stub")); + do_use_branchstub = 0; + } + else if (do_force2bsr == 0) + { + as_warn (_("-mno-force2bsr is ignored with -mbranch-stub")); + do_force2bsr = 1; + } + } + + if (IS_CSKY_ARCH_801 (mach_flag) || IS_CSKY_ARCH_802 (mach_flag)) + { + if (!do_force2bsr) + as_warn (_("-mno-force2bsr is ignored for ck801/ck802")); + do_force2bsr = 1; + } + else if (do_force2bsr == -1) + do_force2bsr = do_use_branchstub; + + if (do_pff == -1) + { + if (IS_CSKY_ARCH_V1 (mach_flag)) + do_pff = 1; + else + do_pff = 0; + } + + if (do_extend_lrw == -1) + { + if (IS_CSKY_ARCH_801 (mach_flag)) + do_extend_lrw = 1; + else + do_extend_lrw = 0; + } + if (IS_CSKY_ARCH_801 (mach_flag) || IS_CSKY_ARCH_802 (mach_flag)) + { + if (do_long_jump > 0) + as_warn (_("-mljump is ignored for ck801/ck802")); + do_long_jump = 0; + } + else if (do_long_jump == -1) + do_long_jump = 1; + if (do_intr_stack == -1) + { + /* control interrupt stack module, 801&802&803 default on + 807&810, default off. */ + if (IS_CSKY_ARCH_807 (mach_flag) || IS_CSKY_ARCH_810 (mach_flag)) + do_intr_stack = 0; + else + do_intr_stack = 1; + } + /* TODO: add isa_flag(SIMP/CACHE/APS). */ + isa_flag |= (mach_flag & CSKY_ARCH_MAC) ? CSKY_ISA_MAC : 0; + isa_flag |= (mach_flag & CSKY_ARCH_MP) ? CSKY_ISA_MP : 0; + isa_flag |= (mach_flag & CSKY_ARCH_CP) ? CSKY_ISA_CP : 0; + + /* Set abi flag and get table address. */ + if (IS_CSKY_ARCH_V1 (mach_flag)) + { + mach_flag = mach_flag | CSKY_ABI_V1; + opcode = csky_v1_opcodes; + macro = v1_macros_table; + SPANPANIC = v1_SPANPANIC; + SPANCLOSE = v1_SPANCLOSE; + SPANEXIT = v1_SPANEXIT; + md_relax_table = csky_relax_table; + } + else + { + mach_flag = mach_flag | CSKY_ABI_V2; + opcode = csky_v2_opcodes; + macro = v2_macros_table; + SPANPANIC = v2_SPANPANIC; + if (do_extend_lrw) + { + SPANCLOSE = v2_SPANCLOSE_ELRW; + SPANEXIT = v2_SPANEXIT_ELRW; + } + else + { + SPANCLOSE = v2_SPANCLOSE; + SPANEXIT = v2_SPANEXIT; + } + md_relax_table = csky_relax_table; + } + + /* Establish hash table for opcodes and macros. */ + csky_macros_hash = hash_new (); + csky_opcodes_hash = hash_new (); + for ( ; opcode->mnemonic != NULL; opcode++) + if ((isa_flag & (opcode->isa_flag16 | opcode->isa_flag32)) != 0) + hash_insert (csky_opcodes_hash, opcode->mnemonic, (char *)opcode); + for ( ; macro->name != NULL; macro++) + if ((isa_flag & macro->isa_flag) != 0) + hash_insert (csky_macros_hash, macro->name, (char *)macro); + if (do_nolrw && (isa_flag & CSKYV2_ISA_1E2) != 0) + hash_insert (csky_macros_hash, + v2_lrw_macro_opcode.name, + (char *)&v2_lrw_macro_opcode); + /* Set e_flag to ELF Head. */ + bfd_set_private_flags (stdoutput, mach_flag); + /* Set bfd_mach to bfd backend data. */ + bfd_set_arch_mach (stdoutput, bfd_arch_csky, bfd_mach_flag); +} + +/* The C-SKY assembler emits mapping symbols $t and $d to mark the + beginning of a sequence of instructions and data (such as a constant pool), + respectively. This is similar to what ARM does. */ + +static void +make_mapping_symbol (map_state state, valueT value, fragS *frag) +{ + symbolS * symbolP; + const char * symname; + int type; + switch (state) + { + case MAP_DATA: + symname = "$d"; + type = BSF_NO_FLAGS; + break; + case MAP_TEXT: + symname = "$t"; + type = BSF_NO_FLAGS; + break; + default: + abort (); + } + + symbolP = symbol_new (symname, now_seg, value, frag); + symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL; +} + +/* We need to keep track of whether we are emitting code or data; this + function switches state and emits a mapping symbol if necessary. */ + +static void +mapping_state (map_state state) +{ + map_state current_state + = seg_info (now_seg)->tc_segment_info_data.current_state; + + if (current_state == state) + return; + else if (current_state == MAP_UNDEFINED && state == MAP_DATA) + return; + else if (current_state == MAP_UNDEFINED && state == MAP_TEXT) + { + struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root; + if (frag_now != frag_first || frag_now_fix () > 0) + make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first); + } + + seg_info (now_seg)->tc_segment_info_data.current_state = state; + make_mapping_symbol (state, (valueT) frag_now_fix (), frag_now); +} + +/* Dump the literal pool. */ + +static void +dump_literals (int isforce) +{ +#define CSKYV1_BR_INSN 0xF000 +#define CSKYV2_BR_INSN 0x0400 + unsigned int i; + struct literal * p; + symbolS * brarsym = NULL; + + /* V1 nop encoding: 0x1200 : mov r0, r0. */ + static char v1_nop_insn_big[2] = {0x12, 0x00}; + static char v1_nop_insn_little[2] = {0x00, 0x12}; + + if (poolsize == 0) + return; + + /* Must we branch around the literal table? */ + if (isforce) + { + char brarname[8]; + make_internal_label (brarname, POOL_END_LABEL, poolnumber); + brarsym = symbol_make (brarname); + symbol_table_insert (brarsym); + mapping_state (MAP_TEXT); + if (IS_CSKY_ARCH_V1 (mach_flag)) + { + csky_insn.output + = frag_var (rs_machine_dependent, + csky_relax_table[C (UNCD_JUMP_S, DISP32)].rlx_length, + csky_relax_table[C (UNCD_JUMP_S, DISP12)].rlx_length, + C (UNCD_JUMP_S, 0), brarsym, 0, 0); + md_number_to_chars (csky_insn.output, CSKYV1_BR_INSN, 2); + } + else + { + csky_insn.output + = frag_var (rs_machine_dependent, + UNCD_DISP16_LEN, + UNCD_DISP10_LEN, + UNCD_DISP10, + brarsym, 0, 0); + md_number_to_chars (csky_insn.output, CSKYV2_BR_INSN, 2); + } + } + /* Make sure that the section is sufficiently aligned and that + the literal table is aligned within it. */ + if (do_pff) + { + valueT br_self; + csky_insn.output = frag_more (2); + /* .Lxx: br .Lxx */ + if (IS_CSKY_V1 (mach_flag)) + br_self = CSKYV1_BR_INSN | 0x7ff; + else + br_self = CSKYV2_BR_INSN; + md_number_to_chars (csky_insn.output, br_self, 2); + if (!isforce) + { + csky_insn.output = frag_more (2); + /* .Lxx: br .Lxx */ + md_number_to_chars (csky_insn.output, br_self, 2); + } + } + mapping_state (MAP_DATA); + + record_alignment (now_seg, 2); + if (IS_CSKY_ARCH_V1 (mach_flag)) + frag_align_pattern (2, + (target_big_endian + ? v1_nop_insn_big : v1_nop_insn_little), + 2, 0); + else + frag_align (2, 0, 3); + + colon (S_GET_NAME (poolsym)); + + for (i = 0, p = litpool; i < poolsize; i += (p->isdouble ? 2 : 1), p++) + { + insn_reloc = p->r_type; + if (insn_reloc == BFD_RELOC_CKCORE_TLS_IE32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_GD32) + literal_insn_offset = p; + if (p->isdouble) + { + if (target_big_endian) + { + p->e.X_add_number = p->dbnum >> 32; + emit_expr (& p->e, 4); + p->e.X_add_number = p->dbnum & 0xffffffff; + emit_expr (& p->e, 4); + } + else + { + p->e.X_add_number = p->dbnum & 0xffffffff; + emit_expr (& p->e, 4); + p->e.X_add_number = p->dbnum >> 32; + emit_expr (& p->e, 4); + } + } + else + emit_expr (& p->e, 4); + } + + if (isforce && IS_CSKY_ARCH_V2 (mach_flag)) + { + /* Add one nop insn at end of literal for disassembler. */ + mapping_state (MAP_TEXT); + csky_insn.output = frag_more (2); + md_number_to_chars (csky_insn.output, CSKYV2_INST_NOP, 2); + } + + insn_reloc = BFD_RELOC_NONE; + + if (brarsym != NULL) + colon (S_GET_NAME (brarsym)); + poolsize = 0; +} + +static int +enter_literal (expressionS *e, + int ispcrel, + unsigned char isdouble, + uint64_t dbnum) +{ + unsigned int i; + struct literal * p; + if (poolsize >= MAX_POOL_SIZE - 2) + { + /* The literal pool is as full as we can handle. We have + to be 2 entries shy of the 1024/4=256 entries because we + have to allow for the branch (2 bytes) and the alignment + (2 bytes before the first insn referencing the pool and + 2 bytes before the pool itself) == 6 bytes, rounds up + to 2 entries. */ + + /* Save the parsed symbol's reloc. */ + enum bfd_reloc_code_real last_reloc_before_dump = insn_reloc; + dump_literals (1); + insn_reloc = last_reloc_before_dump; + } + + if (poolsize == 0) + { + /* Create new literal pool. */ + if (++ poolnumber > 0xFFFF) + as_fatal (_("more than 65K literal pools")); + + make_internal_label (poolname, POOL_START_LABEL, poolnumber); + poolsym = symbol_make (poolname); + symbol_table_insert (poolsym); + poolspan = 0; + } + + /* Search pool for value so we don't have duplicates. */ + for (p = litpool, i = 0; i < poolsize; i += (p->isdouble ? 2 : 1), p++) + { + if (e->X_op == p->e.X_op + && e->X_add_symbol == p->e.X_add_symbol + && e->X_add_number == p->e.X_add_number + && ispcrel == p->ispcrel + && insn_reloc == p->r_type + && isdouble == p->isdouble + && insn_reloc != BFD_RELOC_CKCORE_TLS_GD32 + && insn_reloc != BFD_RELOC_CKCORE_TLS_LDM32 + && insn_reloc != BFD_RELOC_CKCORE_TLS_LDO32 + && insn_reloc != BFD_RELOC_CKCORE_TLS_IE32 + && insn_reloc != BFD_RELOC_CKCORE_TLS_LE32) + { + p->refcnt ++; + return i; + } + } + p->refcnt = 1; + p->ispcrel = ispcrel; + p->e = *e; + p->r_type = insn_reloc; + p->isdouble = isdouble; + if (isdouble) + p->dbnum = dbnum; + + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + { + p->tls_addend.frag = frag_now; + p->tls_addend.offset = csky_insn.output - frag_now->fr_literal; + literal_insn_offset = p; + } + poolsize += (p->isdouble ? 2 : 1); + return i; +} + +/* Check whether we must dump the literal pool here. + kind == 0 is any old instruction. + kind > 0 means we just had a control transfer instruction. + kind == 1 means within a function. + kind == 2 means we just left a function. + + OFFSET is the length of the insn being processed. + + SPANCLOSE and SPANEXIT are smaller numbers than SPANPANIC. + SPANPANIC means that we must dump now. + The dump_literals (1) call inserts a branch around the table, so + we first look to see if its a situation where we won't have to + insert a branch (e.g., the previous instruction was an unconditional + branch). + + SPANPANIC is the point where we must dump a single-entry pool. + it accounts for alignments and an inserted branch. + the 'poolsize*2' accounts for the scenario where we do: + lrw r1,lit1; lrw r2,lit2; lrw r3,lit3 + Note that the 'lit2' reference is 2 bytes further along + but the literal it references will be 4 bytes further along, + so we must consider the poolsize into this equation. + This is slightly over-cautious, but guarantees that we won't + panic because a relocation is too distant. */ + +static void +check_literals (int kind, int offset) +{ + poolspan += offset; + + if ((poolspan > SPANEXIT || do_func_dump) + && kind > 1 + && (do_br_dump || do_func_dump)) + dump_literals (0); + else if (poolspan > SPANCLOSE && (kind > 0) && do_br_dump) + dump_literals (0); + else if (poolspan + >= (SPANPANIC - (IS_CSKY_ARCH_V1 (mach_flag) ? poolsize * 2 : 0))) + dump_literals (1); + /* We have not dumped literal pool before insn1, + and will not dump literal pool between insn1 and insnN+1, + so reset poolspan to original length. */ + else if (do_noliteraldump == 1) + poolspan -= offset; + + if (do_noliteraldump == 1) + do_noliteraldump = 0; +} + +/* The next group of functions are helpers for parsing various kinds + of instruction operand syntax. */ + +/* Parse operands of the form + <symbol>@GOTOFF+<nnn> + and similar .plt or .got references. + + If we find one, set up the correct relocation in RELOC and copy the + input string, minus the `@GOTOFF' into a malloc'd buffer for + parsing by the calling routine. Return this buffer, and if ADJUST + is non-null set it to the length of the string we removed from the + input line. Otherwise return NULL. */ + +static char * +lex_got (enum bfd_reloc_code_real *reloc, + int *adjust) +{ + struct _gotrel + { + const char *str; + const enum bfd_reloc_code_real rel; + }; + static const struct _gotrel gotrel[] = + { + { "GOTOFF", BFD_RELOC_CKCORE_GOTOFF }, + { "GOTPC", BFD_RELOC_CKCORE_GOTPC }, + { "GOTTPOFF", BFD_RELOC_CKCORE_TLS_IE32 }, + { "GOT", BFD_RELOC_CKCORE_GOT32 }, + { "PLT", BFD_RELOC_CKCORE_PLT32 }, + { "BTEXT", BFD_RELOC_CKCORE_TOFFSET_LO16}, + { "BDATA", BFD_RELOC_CKCORE_DOFFSET_LO16}, + { "TLSGD32", BFD_RELOC_CKCORE_TLS_GD32 }, + { "TLSLDM32", BFD_RELOC_CKCORE_TLS_LDM32 }, + { "TLSLDO32", BFD_RELOC_CKCORE_TLS_LDO32 }, + { "TPOFF", BFD_RELOC_CKCORE_TLS_LE32 } + }; + + char *cp; + unsigned int j; + + for (cp = input_line_pointer; *cp != '@'; cp++) + if (is_end_of_line[(unsigned char) *cp]) + return NULL; + + for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) + { + int len = strlen (gotrel[j].str); + + if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) + { + if (gotrel[j].rel != 0) + { + *reloc = gotrel[j].rel; + if (adjust) + *adjust = len; + + /* input_line_pointer is the str pointer after relocation + token like @GOTOFF. */ + input_line_pointer += len + 1; + return input_line_pointer; + } + + csky_show_error (ERROR_RELOC_ILLEGAL, 0, + (void *)gotrel[j].str, NULL); + return NULL; + } + } + + /* Might be a symbol version string. Don't as_bad here. */ + return NULL; +} + +/* Parse an expression, returning it in E. */ + +static char * +parse_exp (char *s, expressionS *e) +{ + char *save; + char *new; + + /* Skip whitespace. */ + while (ISSPACE (*s)) + ++s; + + save = input_line_pointer; + input_line_pointer = s; + + insn_reloc = BFD_RELOC_NONE; + expression (e); + lex_got (&insn_reloc, NULL); + + if (e->X_op == O_absent) + SET_ERROR_NUMBER (ERROR_MISSING_OPERAND, NULL); + + new = input_line_pointer; + input_line_pointer = save; + + return new; +} + +/* Parse a floating-point number from S into its target representation. + If ISDOUBLE is true, return the result in *DBNUM; otherwise + it's returned in E->X_add_number. Returns the result of advancing + S past the constant. */ + +static char * +parse_fexp (char *s, expressionS *e, unsigned char isdouble, uint64_t *dbnum) +{ + int length; /* Number of chars in an object. */ + register char const *err = NULL; /* Error from scanning float literal. */ + char temp[8]; + + /* input_line_pointer->1st char of a flonum (we hope!). */ + input_line_pointer = s; + + if (input_line_pointer[0] == '0' + && ISALPHA (input_line_pointer[1])) + input_line_pointer += 2; + + if (isdouble) + err = md_atof ('d', temp, &length); + else + err = md_atof ('f', temp, &length); + know (length <= 8); + know (err != NULL || length > 0); + + if (!is_end_of_line[(unsigned char) *input_line_pointer]) + as_bad (_("immediate operand required")); + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + input_line_pointer++; + + if (err) + { + as_bad (_("bad floating literal: %s"), err); + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + input_line_pointer++; + know (is_end_of_line[(unsigned char) input_line_pointer[-1]]); + return input_line_pointer; + } + + e->X_add_symbol = 0x0; + e->X_op_symbol = 0x0; + e->X_op = O_constant; + e->X_unsigned = 1; + e->X_md = 0x0; + + if (!isdouble) + { + uint32_t fnum; + if (target_big_endian) + fnum = (((temp[0] << 24) & 0xffffffff) + | ((temp[1] << 16) & 0xffffff) + | ((temp[2] << 8) & 0xffff) + | (temp[3] & 0xff)); + else + fnum = (((temp[3] << 24) & 0xffffffff) + | ((temp[2] << 16) & 0xffffff) + | ((temp[1] << 8) & 0xffff) + | (temp[0] & 0xff)); + e->X_add_number = fnum; } + else + { + if (target_big_endian) + { + *dbnum = (((temp[0] << 24) & 0xffffffff) + | ((temp[1] << 16) & 0xffffff) + | ((temp[2] << 8) & 0xffff) + | (temp[3] & 0xff)); + *dbnum <<= 32; + *dbnum |= (((temp[4] << 24) & 0xffffffff) + | ((temp[5] << 16) & 0xffffff) + | ((temp[6] << 8) & 0xffff) + | (temp[7] & 0xff)); + } + else + { + *dbnum = (((temp[7] << 24) & 0xffffffff) + | ((temp[6] << 16) & 0xffffff) + | ((temp[5] << 8) & 0xffff) + | (temp[4] & 0xff)); + *dbnum <<= 32; + *dbnum |= (((temp[3] << 24) & 0xffffffff) + | ((temp[2] << 16) & 0xffffff) + | ((temp[1] << 8) & 0xffff) + | (temp[0] & 0xff)); + } + } + return input_line_pointer; +} + +static char * +parse_rt (char *s, + int ispcrel, + expressionS *ep, + long reg ATTRIBUTE_UNUSED) +{ + expressionS e; + int n; + + if (ep) + /* Indicate nothing there. */ + ep->X_op = O_absent; + + if (*s == '[') + { + s = parse_exp (s + 1, &e); + + if (*s == ']') + s++; + else + SET_ERROR_NUMBER (ERROR_MISSING_RSQUARE_BRACKETS, NULL); + + if (ep) + *ep = e; + } + else + { + s = parse_exp (s, &e); + if (BFD_RELOC_CKCORE_DOFFSET_LO16 == insn_reloc + || BFD_RELOC_CKCORE_TOFFSET_LO16 == insn_reloc) + { + if (ep) + *ep = e; + return s; + } + if (ep) + *ep = e; + /* If the instruction has work, literal handling is in the work. */ + if (!csky_insn.opcode->work) + { + n = enter_literal (&e, ispcrel, 0, 0); + if (ep) + *ep = e; + + /* Create a reference to pool entry. */ + ep->X_op = O_symbol; + ep->X_add_symbol = poolsym; + ep->X_add_number = n << 2; + } + } + return s; +} + +static char * +parse_rtf (char *s, int ispcrel, expressionS *ep) +{ + expressionS e; + int n = 0; + + if (ep) + /* Indicate nothing there. */ + ep->X_op = O_absent; + + if (*s == '[') + { + s = parse_exp (s + 1, & e); + + if (*s == ']') + s++; + else + as_bad (_("missing ']'")); + + if (ep) + *ep = e; + } + else + { + uint64_t dbnum; + if (strstr (csky_insn.opcode->mnemonic, "flrws")) + { + s = parse_fexp (s, &e, 0, &dbnum); + n = enter_literal (&e, ispcrel, 0, dbnum); + } + else if (strstr (csky_insn.opcode->mnemonic, "flrwd")) + { + s = parse_fexp (s, &e, 1, &dbnum); + n = enter_literal (&e, ispcrel, 1, dbnum); + } + else + as_bad (_("unrecognized opcode")); + + if (ep) + *ep = e; + + /* Create a reference to pool entry. */ + ep->X_op = O_symbol; + ep->X_add_symbol = poolsym; + ep->X_add_number = n << 2; + } + return s; +} + +static bfd_boolean +parse_type_ctrlreg (char** oper) +{ + int i = -1; + int len = 0; + + if (TOLOWER (*(*oper + 0)) == 'c' + && TOLOWER (*(*oper + 1)) == 'r' + && ISDIGIT (*(*oper + 2))) + { + /* The control registers are named crxx. */ + i = *(*oper + 2) - 0x30; + i = ISDIGIT (*(*oper + 3)) ? (*(*oper + 3) - 0x30) + 10 * i : i; + len = ISDIGIT (*(*oper + 3)) ? 4 : 3; + *oper += len; + } + else if (!(TOLOWER (*(*oper + 0)) == 'c' + && TOLOWER (*(*oper + 1)) == 'r')) + { + /* The control registers are aliased. */ + struct csky_reg *reg = &csky_ctrl_regs[0]; + while (reg->name) + { + if (memcmp (*oper, reg->name, strlen (reg->name)) == 0 + && (!reg->flag || (isa_flag & reg->flag))) + { + i = reg->index; + len = strlen (reg->name); + *oper += len; + break; + } + reg++; + } + } + + if (IS_CSKY_V2 (mach_flag)) + { + char *s = *oper; + int crx; + int sel; + if (i != -1) + { + crx = i; + sel = 0; + } + else + { + if (s[0] == 'c' && s[1] == 'r') + { + s += 2; + if (*s == '<') + { + s++; + if (s[0] == '3' && s[1] >= '0' && s[1] <= '1') + { + crx = 30 + s[1] - '0'; + s += 2; + } + else if (s[0] == '2' && s[1] >= '0' && s[1] <= '9') + { + crx = 20 + s[1] - '0'; + s += 2; + } + else if (s[0] == '1' && s[1] >= '0' && s[1] <= '9') + { + crx = 10 + s[1] - '0'; + s += 2; + } + else if (s[0] >= '0' && s[0] <= '9') + { + crx = s[0] - '0'; + s += 1; + } + else + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, "control"); + return FALSE; + } + if (*s == ',') + s++; + else + { + SET_ERROR_NUMBER (ERROR_CREG_ILLEGAL, NULL); + return FALSE; + } + char *pS = s; + while (*pS != '>' && !is_end_of_line[(unsigned char) *pS]) + pS++; + if (*pS == '>') + *pS = '\0'; + else + { + /* Error. Missing '>'. */ + SET_ERROR_NUMBER (ERROR_MISSING_RANGLE_BRACKETS, NULL); + return FALSE; + } + expressionS e; + s = parse_exp (s, &e); + if (e.X_op == O_constant + && e.X_add_number >= 0 + && e.X_add_number <= 31) + { + *oper = s; + sel = e.X_add_number; + } + else + return FALSE; + } + else + { + /* Error. Missing '<'. */ + SET_ERROR_NUMBER (ERROR_MISSING_LANGLE_BRACKETS, NULL); + return FALSE; + } + } + else + { + SET_ERROR_NUMBER (ERROR_CREG_ILLEGAL, NULL); + return FALSE; + } + } + i = (sel << 5) | crx; + } + csky_insn.val[csky_insn.idx++] = i; + return TRUE; +} + +static bfd_boolean +is_reg_sp_with_bracket (char **oper) +{ + const char **regs; + int sp_idx; + int len; + + if (IS_CSKY_V1 (mach_flag)) + sp_idx = 0; + else + sp_idx = 14; + + if (**oper != '(') + return FALSE; + *oper += 1; + regs = csky_general_reg; + len = strlen (regs[sp_idx]); + if (memcmp (*oper, regs[sp_idx], len) == 0) + { + *oper += len; + if (**oper != ')') + return FALSE; + *oper += 1; + csky_insn.val[csky_insn.idx++] = sp_idx; + return TRUE; + } + else + { + if (IS_CSKY_V1 (mach_flag)) + regs = cskyv1_general_alias_reg; + else + regs = cskyv2_general_alias_reg; + len = strlen (regs[sp_idx]); + if (memcmp (*oper, regs[sp_idx], len) == 0) + { + *oper += len; + if (**oper != ')') + return FALSE; + *oper += 1; + return TRUE; + } + } + return FALSE; +} + +static bfd_boolean +is_reg_sp (char **oper) +{ + const char **regs; + int sp_idx; + int len; + if (IS_CSKY_V1 (mach_flag)) + sp_idx = 0; + else + sp_idx = 14; + + regs = csky_general_reg; + len = strlen (regs[sp_idx]); + if (memcmp (*oper, regs[sp_idx], len) == 0) + { + *oper += len; + csky_insn.val[csky_insn.idx++] = sp_idx; + return TRUE; + } + else + { + if (IS_CSKY_V1 (mach_flag)) + regs = cskyv1_general_alias_reg; + else + regs = cskyv2_general_alias_reg; + len = strlen (regs[sp_idx]); + if (memcmp (*oper, regs[sp_idx], len) == 0) + { + *oper += len; + csky_insn.val[csky_insn.idx++] = sp_idx; + return TRUE; + } + } + return FALSE; +} + +static int +csky_get_reg_val (char *str, int *len) +{ + long reg = 0; + if (TOLOWER (str[0]) == 'r' && ISDIGIT (str[1])) + { + if (ISDIGIT (str[1]) && ISDIGIT (str[2])) + { + reg = (str[1] - '0') * 10 + str[2] - '0'; + *len = 3; + } + else if (ISDIGIT (str[1])) + { + reg = str[1] - '0'; + *len = 2; + } + else + return -1; + } + else if (TOLOWER (str[0]) == 's' && TOLOWER (str[1]) == 'p' + && !ISDIGIT (str[2])) + { + /* sp. */ + if (IS_CSKY_V1 (mach_flag)) + reg = 0; + else + reg = 14; + *len = 2; + } + else if (TOLOWER (str[0]) == 'g' && TOLOWER (str[1]) == 'b' + && !ISDIGIT (str[2])) + { + /* gb. */ + if (IS_CSKY_V1 (mach_flag)) + reg = 14; + else + reg = 28; + *len = 2; + } + else if (TOLOWER (str[0]) == 'l' && TOLOWER (str[1]) == 'r' + && !ISDIGIT (str[2])) + { + /* lr. */ + reg = 15; + *len = 2; + } + else if (TOLOWER (str[0]) == 't' && TOLOWER (str[1]) == 'l' + && TOLOWER (str[2]) == 's' && !ISDIGIT (str[3])) + { + /* tls. */ + if (IS_CSKY_V2 (mach_flag)) + reg = 31; + else + return -1; + *len = 3; + } + else if (TOLOWER (str[0]) == 's' && TOLOWER (str[1]) == 'v' + && TOLOWER (str[2]) == 'b' && TOLOWER (str[3]) == 'r') + { + if (IS_CSKY_V2 (mach_flag)) + reg = 30; + else + return -1; + *len = 4; + } + else if (TOLOWER (str[0]) == 'a') + { + if (ISDIGIT (str[1]) && !ISDIGIT (str[2])) + { + if (IS_CSKY_V1 (mach_flag) && (str[1] - '0') <= 5) + /* a0 - a5. */ + reg = 2 + str[1] - '0'; + else if (IS_CSKY_V2 (mach_flag) && (str[1] - '0') <= 3) + /* a0 - a3. */ + reg = str[1] - '0'; + else + return -1; + *len = 2; + } + } + else if (TOLOWER (str[0]) == 't') + { + if (IS_CSKY_V2 (mach_flag)) + { + reg = atoi (str + 1); + if (reg > 9) + return -1; + + if (reg > 1) + /* t2 - t9. */ + reg = reg + 16; + else + /* t0 - t1. */ + reg = reg + 12; + *len = 2; + } + } + else if (TOLOWER (str[0]) == 'l') + { + if (str[1] < '0' || str[1] > '9') + return -1; + if (IS_CSKY_V2 (mach_flag)) + { + reg = atoi (str + 1); + if (reg > 9) + return -1; + if (reg > 7) + /* l8 - l9. */ + reg = reg + 8; + else + /* l0 - l7. */ + reg = reg + 4; + } + else + { + reg = atoi (str + 1); + if (reg > 5) + return -1; + /* l0 - l6 -> r8 - r13. */ + reg = reg + 8; + } + *len = 2; + } + else + return -1; + + /* Is register available? */ + if (IS_CSKY_ARCH_801 (mach_flag)) + { + /* CK801 register range is r0-r8 & r13-r15. */ + if ((reg > 8 && reg < 13) || reg > 15) + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, reg); + return -1; + } + } + else if (IS_CSKY_ARCH_802 (mach_flag)) + { + /* CK802 register range is r0-r15 & r23-r25 & r30. */ + if ((reg > 15 && reg < 23) || (reg > 25 && reg != 30)) + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, reg); + return -1; + } + } + else if (reg > 31 || reg < 0) + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, reg); + return -1; + } + + return reg; +} + +static int +csky_get_freg_val (char *str, int *len) +{ + int reg = 0; + char *s = NULL; + if ((str[0] == 'v' || str[0] == 'f') && (str[1] == 'r')) + { + /* It is fpu register. */ + s = &str[2]; + while (ISDIGIT (*s)) + { + reg = reg * 10 + (*s) - '0'; + s++; + } + if (reg > 31) + return -1; + } + else + return -1; + *len = s - str; + return reg; +} + +static bfd_boolean +is_reglist_legal (char **oper) +{ + int reg1 = -1; + int reg2 = -1; + int len = 0; + reg1 = csky_get_reg_val (*oper, &len); + *oper += len; + + if (reg1 == -1 || (IS_CSKY_V1 (mach_flag) && (reg1 == 0 || reg1 == 15))) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The first reg must not be r0/r15"); + return FALSE; + } + + if (**oper != '-') + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The operand format must be rx-ry"); + return FALSE; + } + *oper += 1; + + reg2 = csky_get_reg_val (*oper, &len); + *oper += len; + + if (reg2 == -1 || (IS_CSKY_V1 (mach_flag) && reg1 == 15)) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The operand format must be r15 in C-SKY V1"); + return FALSE; + } + if (IS_CSKY_V2 (mach_flag)) + { + if (reg2 < reg1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The operand format must be rx-ry (rx < ry)"); + return FALSE; + } + reg2 = reg2 - reg1; + reg1 <<= 5; + reg1 |= reg2; + } + csky_insn.val[csky_insn.idx++] = reg1; + return TRUE; +} + +static bfd_boolean +is_freglist_legal (char **oper) +{ + int reg1 = -1; + int reg2 = -1; + int len = 0; + reg1 = csky_get_freg_val (*oper, &len); + *oper += len; + + if (reg1 == -1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The fpu register format is not recognized."); + return FALSE; + } + + if (**oper != '-') + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The operand format must be vrx-vry/frx-fry."); + return FALSE; + } + *oper += 1; + + reg2 = csky_get_freg_val (*oper, &len); + *oper += len; + + if (reg2 == -1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The fpu register format is not recognized."); + return FALSE; + } + if (reg2 < reg1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The operand format must be rx-ry(rx < ry)"); + return FALSE; + } + reg2 = reg2 - reg1; + reg2 <<= 4; + reg1 |= reg2; + csky_insn.val[csky_insn.idx++] = reg1; + return TRUE; +} + +static bfd_boolean +is_reglist_dash_comma_legal (char **oper, struct operand *oprnd) +{ + int reg1 = -1; + int reg2 = -1; + int len = 0; + int list = 0; + int flag = 0; + int temp = 0; + while (**oper != '\n' && **oper != '\0') + { + reg1 = csky_get_reg_val (*oper, &len); + if (reg1 == -1) + { + SET_ERROR_NUMBER (ERROR_REG_LIST, NULL); + return FALSE; + } + flag |= (1 << reg1); + *oper += len; + if (**oper == '-') + { + *oper += 1; + reg2 = csky_get_reg_val (*oper, &len); + if (reg2 == -1) + { + SET_ERROR_NUMBER (ERROR_REG_LIST, NULL); + return FALSE; + } + *oper += len; + if (reg1 > reg2) + { + SET_ERROR_NUMBER (ERROR_REG_LIST, NULL); + return FALSE; + } + while (reg2 >= reg1) + { + flag |= (1 << reg2); + reg2--; + } + } + if (**oper == ',') + *oper += 1; + } + /* The reglist: r4-r11, r15, r16-r17, r28. */ +#define REGLIST_BITS 0x10038ff0 + if (flag & ~(REGLIST_BITS)) + { + SET_ERROR_NUMBER (ERROR_REG_LIST, NULL); + return FALSE; + } + /* Check r4-r11. */ + int i = 4; + while (i <= 11) + { + if (flag & (1 << i)) + temp = i - 4 + 1; + i++; + } + list |= temp; + + /* Check r15. */ + if (flag & (1 << 15)) + list |= (1 << 4); + + /* Check r16-r17. */ + i = 16; + temp = 0; + while (i <= 17) + { + if (flag & (1 << i)) + temp = i - 16 + 1; + i++; + } + list |= (temp << 5); + + /* Check r28. */ + if (flag & (1 << 28)) + list |= (1 << 8); + if (oprnd->mask == OPRND_MASK_0_4 && (list & ~OPRND_MASK_0_4)) + { + SET_ERROR_NUMBER (ERROR_REG_LIST, NULL); + return FALSE; + } + csky_insn.val[csky_insn.idx++] = list; + return TRUE; +} + +static bfd_boolean +is_reg_lshift_illegal (char **oper, int is_float) +{ + int value; + int len; + int reg; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, "The register must be r0-r31."); + return FALSE; + } + + *oper += len; + if ((*oper)[0] != '<' || (*oper)[1] != '<') + { + SET_ERROR_NUMBER (ERROR_UNDEFINE, + "Operand format error; should be (rx, ry << n)"); + return FALSE; + } + *oper += 2; + + expressionS e; + char *new_oper = parse_exp (*oper, &e); + if (e.X_op == O_constant) + { + *oper = new_oper; + /* The immediate must be in [0, 3]. */ + if (e.X_add_number < 0 || e.X_add_number > 3) + { + SET_ERROR_NUMBER (ERROR_IMM_OVERFLOW, NULL); + return FALSE; + } + } + else + { + SET_ERROR_NUMBER (ERROR_EXP_CONSTANT, NULL); + return FALSE; + } + if (is_float) + value = (reg << 2) | e.X_add_number; + else + value = (reg << 5) | (1 << e.X_add_number); + csky_insn.val[csky_insn.idx++] = value; + + return TRUE; +} + +static bfd_boolean +is_imm_over_range (char **oper, int min, int max, int ext) +{ + expressionS e; + bfd_boolean ret = FALSE; + char *new_oper = parse_exp (*oper, &e); + if (e.X_op == O_constant) + { + ret = TRUE; + *oper = new_oper; + if ((int)e.X_add_number != ext + && (e.X_add_number < min || e.X_add_number > max)) + { + ret = FALSE; + SET_ERROR_NUMBER (ERROR_IMM_OVERFLOW, NULL); + } + csky_insn.val[csky_insn.idx++] = e.X_add_number; + } + + return ret; +} + +static bfd_boolean +is_oimm_over_range (char **oper, int min, int max) +{ + expressionS e; + bfd_boolean ret = FALSE; + char *new_oper = parse_exp (*oper, &e); + if (e.X_op == O_constant) + { + ret = TRUE; + *oper = new_oper; + if (e.X_add_number < min || e.X_add_number > max) + { + ret = FALSE; + SET_ERROR_NUMBER (ERROR_IMM_OVERFLOW, NULL); + } + csky_insn.val[csky_insn.idx++] = e.X_add_number - 1; + } + + return ret; +} + +static bfd_boolean +is_psr_bit (char **oper) +{ + const struct psrbit *bits; + int i = 0; + + if (IS_CSKY_V1 (mach_flag)) + bits = cskyv1_psr_bits; + else + bits = cskyv2_psr_bits; + + while (bits[i].name != NULL) + { + if (bits[i].isa && !(bits[i].isa & isa_flag)) + { + i++; + continue; + } + if (strncasecmp (*oper, bits[i].name, strlen (bits[i].name)) == 0) + { + *oper += strlen (bits[i].name); + csky_insn.val[csky_insn.idx] |= bits[i].value; + return TRUE; + } + i++; + } + SET_ERROR_NUMBER (ERROR_OPCODE_PSRBIT, NULL); + return FALSE; +} + +static bfd_boolean +parse_type_cpidx (char** oper) +{ + char *s = *oper; + int idx; + if (s[0] == 'c' && s[1] == 'p') + { + if (ISDIGIT (s[2]) && ISDIGIT (s[3]) && ! ISDIGIT (s[4])) + { + idx = (s[2] - '0') * 10 + s[3] - '0'; + *oper += 4; + } + else if (ISDIGIT (s[2]) && !ISDIGIT (s[3])) + { + idx = s[2] - '0'; + *oper += 3; + } + else + return FALSE; + } + else + { + expressionS e; + *oper = parse_exp (*oper, &e); + if (e.X_op != O_constant) + { + /* Can not recognize the operand. */ + return FALSE; + } + idx = e.X_add_number; + } + + csky_insn.val[csky_insn.idx++] = idx; + + return TRUE; +} + +static bfd_boolean +parse_type_cpreg (char** oper) +{ + const char **regs = csky_cp_reg; + int i; + int len; + + for (i = 0; i < (int)(sizeof (csky_cp_reg) / sizeof (char *)); i++) + { + len = strlen (regs[i]); + if (memcmp (*oper, regs[i], len) == 0 && !ISDIGIT (*(*oper + len))) + { + *oper += len; + csky_insn.val[csky_insn.idx++] = i; + return TRUE; + } + } + SET_ERROR_NUMBER (ERROR_CPREG_ILLEGAL, *oper); + return FALSE; +} + +static bfd_boolean +parse_type_cpcreg (char** oper) +{ + const char **regs; + int i; + int len; + regs = csky_cp_creg; + for (i = 0; i < (int)(sizeof (csky_cp_creg) / sizeof (char *)); i++) + { + len = strlen (regs[i]); + if (memcmp (*oper, regs[i], len) == 0 && !ISDIGIT (*(*oper + len))) + { + *oper += len; + csky_insn.val[csky_insn.idx++] = i; + return TRUE; + } + } + SET_ERROR_NUMBER (ERROR_CPREG_ILLEGAL, *oper); + return FALSE; +} + +static bfd_boolean +parse_type_areg (char** oper) +{ + int i = 0; + int len = 0; + i = csky_get_reg_val (*oper, &len); + if (i == -1) + { + SET_ERROR_NUMBER (ERROR_GREG_ILLEGAL, NULL); + return FALSE; + } + *oper += len; + csky_insn.val[csky_insn.idx++] = i; + + return TRUE; +} + +static bfd_boolean +parse_type_freg (char** oper, int even) +{ + int reg; + int len; + reg = csky_get_freg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The fpu register format is not recognized."); + return FALSE; + } + *oper += len; + csky_insn.opcode_end = *oper; + if (even && reg & 0x1) + { + SET_ERROR_NUMBER (ERROR_EXP_EVEN_FREG, NULL); + return FALSE; + } + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; +} + +static bfd_boolean +parse_ldst_imm (char **oper, struct csky_opcode_info *op ATTRIBUTE_UNUSED, + struct operand *oprnd) +{ + unsigned int mask = oprnd->mask; + int max = 1; + int shift = 0; + + shift = oprnd->shift; + + while (mask) + { + if (mask & 1) + max <<= 1; + mask >>= 1; + } + max = max << shift; + + if (**oper == '\0' || **oper == ')') + { + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + } + + expressionS e; + *oper = parse_exp (*oper, &e); + if (e.X_op != O_constant) + /* Not a constant. */ + return FALSE; + else if (e.X_add_number < 0 || e.X_add_number >= max) + { + /* Out of range. */ + SET_ERROR_NUMBER (ERROR_IMM_OVERFLOW, NULL); + return FALSE; + } + if ((e.X_add_number % (1 << shift)) != 0) + { + /* Not aligned. */ + SET_ERROR_NUMBER (ERROR_OFFSET_UNALIGNED, ((unsigned long)1 << shift)); + return FALSE; + } + + csky_insn.val[csky_insn.idx++] = e.X_add_number >> shift; + + return TRUE; + +} + +static unsigned int +csky_count_operands (char *str) +{ + char *oper_end = str; + unsigned int oprnd_num; + int bracket_cnt = 0; + + if (is_end_of_line[(unsigned char) *oper_end]) + oprnd_num = 0; + else + oprnd_num = 1; + + /* Count how many operands. */ + if (oprnd_num) + while (!is_end_of_line[(unsigned char) *oper_end]) + { + if (*oper_end == '(' || *oper_end == '<') + { + bracket_cnt++; + oper_end++; + continue; + } + if (*oper_end == ')' || *oper_end == '>') + { + bracket_cnt--; + oper_end++; + continue; + } + if (!bracket_cnt && *oper_end == ',') + oprnd_num++; + oper_end++; + } + return oprnd_num; +} + +/* End of the operand parsing helper functions. */ + +/* Parse the opcode part of an instruction. Fill in the csky_insn + state and return true on success, false otherwise. */ + +static bfd_boolean +parse_opcode (char *str) +{ +#define IS_OPCODE32F(a) (*(a - 2) == '3' && *(a - 1) == '2') +#define IS_OPCODE16F(a) (*(a - 2) == '1' && *(a - 1) == '6') + + /* TRUE if this opcode has a suffix, like 'lrw.h'. */ + unsigned int has_suffix = FALSE; + unsigned int nlen = 0; + char *opcode_end; + char name[OPCODE_MAX_LEN + 1]; + char macro_name[OPCODE_MAX_LEN + 1]; + + /* Remove space ahead of string. */ + while (ISSPACE (*str)) + str++; + opcode_end = str; + + /* Find the opcode end. */ + while (nlen < OPCODE_MAX_LEN + && !is_end_of_line [(unsigned char) *opcode_end] + && *opcode_end != ' ') + { + /* Is csky force 32 or 16 instruction? */ + if (IS_CSKY_V2 (mach_flag) + && *opcode_end == '.' && has_suffix == FALSE) + { + has_suffix = TRUE; + if (IS_OPCODE32F (opcode_end)) + { + csky_insn.flag_force = INSN_OPCODE32F; + nlen -= 2; + } + else if (IS_OPCODE16F (opcode_end)) + { + csky_insn.flag_force = INSN_OPCODE16F; + nlen -= 2; + } + } + name[nlen] = *opcode_end; + nlen++; + opcode_end++; + } + + /* Is csky force 32 or 16 instruction? */ + if (has_suffix == FALSE) + { + if (IS_CSKY_V2 (mach_flag) && IS_OPCODE32F (opcode_end)) + { + csky_insn.flag_force = INSN_OPCODE32F; + nlen -= 2; + } + else if (IS_OPCODE16F (opcode_end)) + { + csky_insn.flag_force = INSN_OPCODE16F; + nlen -= 2; + } + } + name[nlen] = '\0'; + + /* Generate macro_name for finding hash in macro hash_table. */ + if (has_suffix == TRUE) + nlen += 2; + strncpy (macro_name, str, nlen); + macro_name[nlen] = '\0'; + + /* Get csky_insn.opcode_end. */ + while (ISSPACE (*opcode_end)) + opcode_end++; + csky_insn.opcode_end = opcode_end; + + /* Count the operands. */ + csky_insn.number = csky_count_operands (opcode_end); + + /* Find hash by name in csky_macros_hash and csky_opcodes_hash. */ + csky_insn.macro = (struct csky_macro_info *) hash_find (csky_macros_hash, + macro_name); + csky_insn.opcode = (struct csky_opcode *) hash_find (csky_opcodes_hash, + name); + + if (csky_insn.macro == NULL && csky_insn.opcode == NULL) + return FALSE; + return TRUE; +} + +/* Main dispatch routine to parse operand OPRND for opcode OP from string + *OPER. */ + +static bfd_boolean +get_operand_value (struct csky_opcode_info *op, + char **oper, struct operand *oprnd) +{ + struct soperand *soprnd = NULL; + if (oprnd->mask == HAS_SUB_OPERAND) + { + /* It has sub operand, it must be like: + (oprnd1, oprnd2) + or + <oprnd1, oprnd2> + We will check the format here. */ + soprnd = (struct soperand *) oprnd; + char lc = 0; + char rc = 0; + char *s = *oper; + int bracket_cnt = 0; + if (oprnd->type == OPRND_TYPE_BRACKET) + { + lc = '('; + rc = ')'; + } + else if (oprnd->type == OPRND_TYPE_ABRACKET) + { + lc = '<'; + rc = '>'; + } + + if (**oper == lc) + { + *oper += 1; + s += 1; + } + else + { + SET_ERROR_NUMBER ((oprnd->type == OPRND_TYPE_BRACKET + ? ERROR_MISSING_LBRACKET + : ERROR_MISSING_LANGLE_BRACKETS), NULL); + return FALSE; + } + + /* If the oprnd2 is an immediate, it can not be parsed + that end with ')'/'>'. Modify ')'/'>' to '\0'. */ + while ((*s != rc || bracket_cnt != 0) && (*s != '\n' && *s != '\0')) + { + if (*s == lc) + bracket_cnt++; + else if (*s == rc) + bracket_cnt--; + s++; + } + + if (*s == rc) + *s = '\0'; + else + { + SET_ERROR_NUMBER ((oprnd->type == OPRND_TYPE_BRACKET + ? ERROR_MISSING_RBRACKET + : ERROR_MISSING_RANGLE_BRACKETS), NULL); + return FALSE; + } + + if (get_operand_value (op, oper, &soprnd->subs[0]) == FALSE) + { + *s = rc; + return FALSE; + } + if (**oper == ',') + *oper += 1; + if (get_operand_value (op, oper, &soprnd->subs[1]) == FALSE) + { + *s = rc; + return FALSE; + } + + *s = rc; + *oper += 1; + return TRUE; + } + + switch (oprnd->type) + { + /* TODO: add opcode type here, log errors in the function. + If REGLIST, then j = csky_insn.number - 1. + If there is needed to parse expressions, it will be + handled here. */ + case OPRND_TYPE_CTRLREG: + /* some parse. */ + return parse_type_ctrlreg (oper); + case OPRND_TYPE_AREG: + return parse_type_areg (oper); + case OPRND_TYPE_FREG: + case OPRND_TYPE_VREG: + return parse_type_freg (oper, 0); + case OPRND_TYPE_FEREG: + return parse_type_freg (oper, 1); + case OPRND_TYPE_CPCREG: + return parse_type_cpcreg (oper); + case OPRND_TYPE_CPREG: + return parse_type_cpreg (oper); + case OPRND_TYPE_CPIDX: + return parse_type_cpidx (oper); + case OPRND_TYPE_GREG0_7: + case OPRND_TYPE_GREG0_15: + { + int len; + long reg; + reg = csky_get_reg_val (*oper, &len); + + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_GREG_ILLEGAL, NULL); + return FALSE; + } + else if ((oprnd->type == OPRND_TYPE_GREG0_7 && reg > 7) + || (oprnd->type == OPRND_TYPE_GREG0_15 && reg > 15)) + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, reg); + return FALSE; + } + *oper += len; + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; + } + case OPRND_TYPE_REGnsplr: + { + int len; + long reg; + reg = csky_get_reg_val (*oper, &len); + + if (reg == -1 + || (IS_CSKY_V1 (mach_flag) + && (reg == V1_REG_SP || reg == V1_REG_LR))) + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, reg); + return FALSE; + } + csky_insn.val[csky_insn.idx++] = reg; + *oper += len; + return TRUE;; + } + case OPRND_TYPE_REGnr4_r7: + { + int len; + int reg; + if (**oper == '(') + *oper += 1; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1 || (reg <= 7 && reg >= 4)) + return FALSE; + + csky_insn.val[csky_insn.idx++] = reg; + *oper += len; + + if (**oper == ')') + *oper += 1; + return TRUE;; + } + case OPRND_TYPE_REGr4_r7: + if (memcmp (*oper, "r4-r7", sizeof ("r4-r7") - 1) == 0) + { + *oper += sizeof ("r4-r7") - 1; + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + } + SET_ERROR_NUMBER (ERROR_OPCODE_ILLEGAL, NULL); + return FALSE; + case OPRND_TYPE_IMM_LDST: + return parse_ldst_imm (oper, op, oprnd); + case OPRND_TYPE_IMM_FLDST: + return parse_ldst_imm (oper, op, oprnd); + case OPRND_TYPE_IMM1b: + return is_imm_over_range (oper, 0, 1, -1); + case OPRND_TYPE_IMM2b: + return is_imm_over_range (oper, 0, 3, -1); + case OPRND_TYPE_IMM2b_JMPIX: + /* ck802j support jmpix16, but not support jmpix32. */ + if (IS_CSKY_ARCH_802 (mach_flag) + && (op->opcode & 0xffff0000) != 0) + { + SET_ERROR_NUMBER (ERROR_OPCODE_ILLEGAL, NULL); + return FALSE; + } + *oper = parse_exp (*oper, &csky_insn.e1); + if (csky_insn.e1.X_op == O_constant) + { + csky_insn.opcode_end = *oper; + if (csky_insn.e1.X_add_number & 0x7) + { + SET_ERROR_NUMBER (ERROR_JMPIX_OVER_RANGE, NULL); + return FALSE; + } + csky_insn.val[csky_insn.idx++] + = (csky_insn.e1.X_add_number >> 3) - 2; + } + return TRUE; + case OPRND_TYPE_IMM4b: + return is_imm_over_range (oper, 0, 15, -1); + break; + case OPRND_TYPE_IMM5b: + return is_imm_over_range (oper, 0, 31, -1); + /* This type for "bgeni" in csky v1 ISA. */ + case OPRND_TYPE_IMM5b_7_31: + if (is_imm_over_range (oper, 0, 31, -1)) + { + int val = csky_insn.val[csky_insn.idx - 1]; + /* immediate values of 0 -> 6 translate to movi. */ + if (val <= 6) + { + const char *name = "movi"; + csky_insn.opcode = (struct csky_opcode *) + hash_find (csky_opcodes_hash, name); + csky_insn.val[csky_insn.idx - 1] = 1 << val; + } + return TRUE; + } + else + return FALSE; + + case OPRND_TYPE_IMM5b_1_31: + return is_imm_over_range (oper, 1, 31, -1); + case OPRND_TYPE_IMM5b_POWER: + if (is_imm_over_range (oper, 1, ~(1 << 31), 1 << 31)) + { + int log; + int val = csky_insn.val[csky_insn.idx - 1]; + log = csky_log_2 (val); + csky_insn.val[csky_insn.idx - 1] = log; + return (log == -1 ? FALSE : TRUE); + } + else + return FALSE; + + /* This type for "mgeni" in csky v1 ISA. */ + case OPRND_TYPE_IMM5b_7_31_POWER: + if (is_imm_over_range (oper, 1, ~(1 << 31), 1 << 31)) + { + int log; + int val = csky_insn.val[csky_insn.idx - 1]; + log = csky_log_2 (val); + /* Immediate values of 0 -> 6 translate to movi. */ + if (log <= 6) + { + const char *name = "movi"; + csky_insn.opcode = (struct csky_opcode *) + hash_find (csky_opcodes_hash, name); + as_warn (_("translating mgeni to movi")); + } + else + csky_insn.val[csky_insn.idx - 1] = log; + return (log == -1 ? FALSE : TRUE); + } + else + return FALSE; + + case OPRND_TYPE_IMM5b_RORI: + { + unsigned max_shift = IS_CSKY_V1 (mach_flag) ? 31 : 32; + + if (is_imm_over_range (oper, 1, max_shift, -1)) + { + int i = csky_insn.idx - 1; + csky_insn.val[i] = 32 - csky_insn.val[i]; + return TRUE; + } + else + return FALSE; + } + + case OPRND_TYPE_IMM5b_BMASKI: + /* For csky v1 bmask inst. */ + + if (!is_imm_over_range (oper, 8, 31, 0)) + { + unsigned int mask_val = csky_insn.val[csky_insn.idx - 1]; + if (mask_val > 0 && mask_val < 8) + { + const char *op_movi = "movi"; + csky_insn.opcode = (struct csky_opcode *) + hash_find (csky_opcodes_hash, op_movi); + if (csky_insn.opcode == NULL) + return FALSE; + csky_insn.val[csky_insn.idx - 1] = (1 << mask_val) - 1; + return TRUE; + } + } + return TRUE; + + case OPRND_TYPE_IMM8b_BMASKI: + /* For csky v2 bmask, which will transfer to 16bits movi. */ + if (is_imm_over_range (oper, 1, 8, -1)) + { + unsigned int mask_val = csky_insn.val[csky_insn.idx - 1]; + csky_insn.val[csky_insn.idx - 1] = (1 << mask_val) - 1; + return TRUE; + } + return FALSE; + case OPRND_TYPE_OIMM4b: + return is_oimm_over_range (oper, 1, 16); + case OPRND_TYPE_OIMM5b: + return is_oimm_over_range (oper, 1, 32); + case OPRND_TYPE_OIMM5b_IDLY: + if (is_imm_over_range (oper, 0, 32, -1)) + { + /* imm5b for idly n: 0<=n<4, imm5b=3; 4<=n<=32, imm5b=n-1. */ + unsigned long imm = csky_insn.val[csky_insn.idx - 1]; + if (imm < 4) + { + csky_show_error (WARNING_IDLY, 0, (void *)imm, NULL); + imm = 3; + } + else imm--; + csky_insn.val[csky_insn.idx - 1] = imm; + return TRUE; + } + else + return FALSE; + + /* For csky v2 bmask inst. */ + case OPRND_TYPE_OIMM5b_BMASKI: + if (!is_oimm_over_range (oper, 17, 32)) + { + int mask_val = csky_insn.val[csky_insn.idx - 1]; + if (mask_val + 1 == 0) + return TRUE; + if (mask_val > 0 && mask_val < 16) + { + const char *op_movi = "movi"; + csky_insn.opcode = (struct csky_opcode *) + hash_find (csky_opcodes_hash, op_movi); + if (csky_insn.opcode == NULL) + return FALSE; + csky_insn.val[csky_insn.idx - 1] = (1 << (mask_val + 1)) - 1; + return TRUE; + } + } + return TRUE; + case OPRND_TYPE_IMM7b: + return is_imm_over_range (oper, 0, 127, -1); + case OPRND_TYPE_IMM8b: + return is_imm_over_range (oper, 0, 255, -1); + case OPRND_TYPE_IMM12b: + return is_imm_over_range (oper, 0, 4095, -1); + case OPRND_TYPE_IMM15b: + return is_imm_over_range (oper, 0, 0xfffff, -1); + case OPRND_TYPE_IMM16b: + return is_imm_over_range (oper, 0, 65535, -1); + case OPRND_TYPE_OIMM16b: + return is_oimm_over_range (oper, 1, 65536); + case OPRND_TYPE_IMM32b: + { + expressionS e; + char *new_oper = parse_exp (*oper, &e); + if (e.X_op == O_constant) + { + *oper = new_oper; + csky_insn.val[csky_insn.idx++] = e.X_add_number; + return TRUE; + } + return FALSE; + } + case OPRND_TYPE_IMM16b_MOVIH: + case OPRND_TYPE_IMM16b_ORI: + { + bfd_reloc_code_real_type r = BFD_RELOC_NONE; + int len; + char *curr = *oper; + char * save = input_line_pointer; + /* get the reloc type, and set "@GOTxxx" as ' ' */ + while (**oper != '@' && **oper != '\0') + *oper += 1; + if (**oper != '\0') + { + input_line_pointer = *oper; + lex_got (&r, &len); + while (*(*oper + len + 1) != '\0') + { + **oper = *(*oper + len + 1); + *(*oper + len + 1) = '\0'; + *oper += 1; + } + **oper = '\0'; + } + input_line_pointer = save; + *oper = parse_exp (curr, &csky_insn.e1); + return TRUE; + } + case OPRND_TYPE_PSR_BITS_LIST: + { + int ret = TRUE; + if (csky_insn.number == 0) + ret = FALSE; + else + { + csky_insn.val[csky_insn.idx] = 0; + if (is_psr_bit (oper) != FALSE) + while (**oper == ',') + { + *oper += 1; + if (is_psr_bit (oper) == FALSE) + { + ret = FALSE; + break; + } + } + else + ret = FALSE; + if (ret == TRUE && IS_CSKY_V1 (mach_flag) + && csky_insn.val[csky_insn.idx] > 8) + ret = FALSE; + } + if (!ret) + SET_ERROR_NUMBER (ERROR_OPERANDS_ILLEGAL, csky_insn.opcode_end); + return ret; + } + case OPRND_TYPE_RM: + { + /* FPU round mode. */ + static const char *round_mode[] = + { + "rm_nearest", + "rm_zero", + "rm_posinf", + "rm_neginf", + NULL + }; + int i; + for (i = 0; round_mode[i]; i++) + if (strncasecmp (*oper, round_mode[i], strlen (round_mode[i])) == 0) + { + *oper += strlen (round_mode[i]); + csky_insn.val[csky_insn.idx++] = i; + return TRUE; + } + return FALSE; + } + + case OPRND_TYPE_REGLIST_COMMA: + case OPRND_TYPE_BRACKET: + /* TODO: using sub operand union. */ + case OPRND_TYPE_ABRACKET: + /* TODO: using sub operand union. */ + case OPRND_TYPE_REGLIST_DASH: + return is_reglist_legal (oper); + case OPRND_TYPE_FREGLIST_DASH: + return is_freglist_legal (oper); + case OPRND_TYPE_AREG_WITH_BRACKET: + { + int len; + int reg; + if (**oper != '(') + { + SET_ERROR_NUMBER (ERROR_MISSING_LBRACKET, NULL); + return FALSE; + } + *oper += 1; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_EXP_GREG, NULL); + return FALSE; + } + *oper += len; + if (**oper != ')') + { + SET_ERROR_NUMBER (ERROR_MISSING_RBRACKET, NULL); + return FALSE; + } + *oper += 1; + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; + } + case OPRND_TYPE_REGsp: + return is_reg_sp (oper); + case OPRND_TYPE_REGbsp: + return is_reg_sp_with_bracket (oper); + /* For jmpi. */ + case OPRND_TYPE_OFF8b: + case OPRND_TYPE_OFF16b: + *oper = parse_rt (*oper, 1, &csky_insn.e1, -1); + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + case OPRND_TYPE_LABEL_WITH_BRACKET: + case OPRND_TYPE_CONSTANT: + case OPRND_TYPE_ELRW_CONSTANT: + if (**oper == '[') + csky_insn.val[csky_insn.idx++] = 0; + else + csky_insn.val[csky_insn.idx++] = NEED_OUTPUT_LITERAL; + *oper = parse_rt (*oper, 0, &csky_insn.e1, -1); + return TRUE; + case OPRND_TYPE_FCONSTANT: + *oper = parse_rtf (*oper, 0, &csky_insn.e1); + return TRUE; + + case OPRND_TYPE_SFLOAT: + case OPRND_TYPE_DFLOAT: + /* For fmovis and fmovid, which accept a constant float with + a limited range. */ + { + uint64_t dbnum; + int imm4, imm8; + + *oper = parse_fexp (*oper, &csky_insn.e1, 1, &dbnum); + if (csky_insn.e1.X_op == O_absent) + return FALSE; + + /* Convert the representation from IEEE double to the 13-bit + encoding used internally for fmovis and fmovid. */ + imm4 = 11 - (((dbnum & 0x7ff0000000000000ULL) >> 52) - 1023); + /* Check float range. */ + if ((dbnum & 0x00000fffffffffffULL) || imm4 < 0 || imm4 > 15) + { + csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL); + return FALSE; + } + imm8 = (dbnum & 0x000ff00000000000ULL) >> 44; + csky_insn.e1.X_add_number + = (((imm8 & 0xf) << 4) + | ((imm8 & 0xf0) << 17) + | ((imm4 & 0xf) << 16) + | ((dbnum & 0x8000000000000000ULL) >> 43)); + return TRUE; + } + + /* For grs v2. */ + case OPRND_TYPE_IMM_OFF18b: + *oper = parse_exp (*oper, &csky_insn.e1); + return TRUE; + + case OPRND_TYPE_BLOOP_OFF4b: + *oper = parse_exp (*oper, &csky_insn.e2); + if (csky_insn.e2.X_op == O_symbol) + { + csky_insn.opcode_end = *oper; + return TRUE; + } + else + return FALSE; + + case OPRND_TYPE_BLOOP_OFF12b: + case OPRND_TYPE_OFF10b: + case OPRND_TYPE_OFF11b: + case OPRND_TYPE_OFF16b_LSL1: + case OPRND_TYPE_OFF26b: + *oper = parse_exp (*oper, &csky_insn.e1); + if (csky_insn.e1.X_op == O_symbol) + { + csky_insn.opcode_end = *oper; + return TRUE; + } + else + return FALSE; + /* For xtrb0(1)(2)(3) and div in csky v1 ISA. */ + case OPRND_TYPE_REG_r1a: + { + int reg = 0; + int len = 0; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The first operand must be register r1."); + return FALSE; + } + if (reg != 1) + mov_r1_after = TRUE; + *oper += len; + csky_insn.opcode_end = *oper; + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; + } + case OPRND_TYPE_REG_r1b: + { + int reg = 0; + int len = 0; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The second operand must be register r1."); + return FALSE; + } + if (reg != 1) + { + unsigned int mov_insn = CSKYV1_INST_MOV_R1_RX; + mov_insn |= reg << 4; + mov_r1_before = TRUE; + csky_insn.output = frag_more (2); + dwarf2_emit_insn (0); + md_number_to_chars (csky_insn.output, mov_insn, 2); + } + *oper += len; + csky_insn.opcode_end = *oper; + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; + } + case OPRND_TYPE_DUMMY_REG: + { + int reg = 0; + int len = 0; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_GREG_ILLEGAL, NULL); + return FALSE; + } + if (reg != csky_insn.val[0]) + { + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The second register must be the same as the first."); + return FALSE; + } + *oper += len; + csky_insn.opcode_end = *oper; + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; + } + case OPRND_TYPE_2IN1_DUMMY: + { + int reg = 0; + int len = 0; + int max = 0; + int min = 0; + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + SET_ERROR_NUMBER (ERROR_GREG_ILLEGAL, NULL); + return FALSE; + } + /* dummy reg's real type should be same with first operand. */ + if (op->oprnd.oprnds[0].type == OPRND_TYPE_GREG0_15) + max = 15; + else if (op->oprnd.oprnds[0].type == OPRND_TYPE_GREG0_7) + max = 7; + else + return FALSE; + if (reg < min || reg > max) + return FALSE; + csky_insn.val[csky_insn.idx++] = reg; + /* if it is the last operands. */ + if (csky_insn.idx > 2) + { + /* For "insn rz, rx, ry", if rx or ry is equal to rz, + we can output the insn like "insn rz, rx". */ + if (csky_insn.val[0] == csky_insn.val[1]) + csky_insn.val[1] = 0; + else if (csky_insn.val[0] == csky_insn.val[2]) + csky_insn.val[2] = 0; + else + return FALSE; + } + *oper += len; + csky_insn.opcode_end = *oper; + return TRUE; + } + case OPRND_TYPE_DUP_GREG0_7: + case OPRND_TYPE_DUP_GREG0_15: + case OPRND_TYPE_DUP_AREG: + { + long reg = 0; + int len = 0; + long max_reg; + unsigned int shift_num; + if (oprnd->type == OPRND_TYPE_DUP_GREG0_7) + { + max_reg = 7; + shift_num = 3; + } + else if (oprnd->type == OPRND_TYPE_DUP_GREG0_15) + { + max_reg = 15; + shift_num = 4; + } + else + { + max_reg = 31; + shift_num = 5; + } + reg = csky_get_reg_val (*oper, &len); + if (reg == -1) + { + if (max_reg == 31) + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The register must be r0-r31"); + else + SET_ERROR_NUMBER (ERROR_REG_FORMAT, + "The register must be r0-r15"); + return FALSE; + } + if (reg > max_reg) + { + SET_ERROR_NUMBER (ERROR_REG_OVER_RANGE, reg); + return FALSE; + } + reg |= reg << shift_num; + *oper += len; + csky_insn.opcode_end = *oper; + csky_insn.val[csky_insn.idx++] = reg; + return TRUE; + } + case OPRND_TYPE_CONST1: + *oper = parse_exp (*oper, &csky_insn.e1); + if (csky_insn.e1.X_op == O_constant) + { + csky_insn.opcode_end = *oper; + if (csky_insn.e1.X_add_number != 1) + return FALSE; + csky_insn.val[csky_insn.idx++] = 1; + return TRUE; + } + return FALSE; + case OPRND_TYPE_UNCOND10b: + case OPRND_TYPE_UNCOND16b: + *oper = parse_exp (*oper, &csky_insn.e1); + if (csky_insn.e1.X_op == O_constant) + return FALSE; + input_line_pointer = *oper; + csky_insn.opcode_end = *oper; + csky_insn.relax.max = UNCD_DISP16_LEN; + csky_insn.relax.var = UNCD_DISP10_LEN; + csky_insn.relax.subtype = UNCD_DISP10; + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + case OPRND_TYPE_COND10b: + case OPRND_TYPE_COND16b: + *oper = parse_exp (*oper, &csky_insn.e1); + if (csky_insn.e1.X_op == O_constant) + return FALSE; + input_line_pointer = *oper; + csky_insn.opcode_end = *oper; + /* CK801 doesn't have 32-bit bt/bf insns; relax to a short + jump around a 32-bit unconditional branch instead. */ + if (IS_CSKY_ARCH_801 (mach_flag)) + { + csky_insn.relax.max = SCOND_DISP16_LEN; + csky_insn.relax.var = SCOND_DISP10_LEN; + csky_insn.relax.subtype = SCOND_DISP10; + } + else + { + csky_insn.relax.max = COND_DISP16_LEN; + csky_insn.relax.var = COND_DISP10_LEN; + csky_insn.relax.subtype = COND_DISP10; + } + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + case OPRND_TYPE_JCOMPZ: + *oper = parse_exp (*oper, &csky_insn.e1); + if (csky_insn.e1.X_op == O_constant) + return FALSE; + input_line_pointer = *oper; + csky_insn.opcode_end = *oper; + csky_insn.relax.max = JCOMPZ_DISP32_LEN; + csky_insn.relax.var = JCOMPZ_DISP16_LEN; + csky_insn.relax.subtype = JCOMPZ_DISP16; + csky_insn.max = JCOMPZ_DISP32_LEN; + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + case OPRND_TYPE_JBTF: + *oper = parse_exp (*oper, &csky_insn.e1); + input_line_pointer = *oper; + csky_insn.opcode_end = *oper; + csky_insn.relax.max = csky_relax_table[C (COND_JUMP_S, DISP32)].rlx_length; + csky_insn.relax.var = csky_relax_table[C (COND_JUMP_S, DISP12)].rlx_length; + csky_insn.relax.subtype = C (COND_JUMP_S, 0); + csky_insn.val[csky_insn.idx++] = 0; + csky_insn.max = C32_LEN_S + 2; + return TRUE; + case OPRND_TYPE_JBR: + *oper = parse_exp (*oper, &csky_insn.e1); + input_line_pointer = *oper; + csky_insn.opcode_end = *oper; + csky_insn.relax.max = csky_relax_table[C (UNCD_JUMP_S, DISP32)].rlx_length; + csky_insn.relax.var = csky_relax_table[C (UNCD_JUMP_S, DISP12)].rlx_length; + csky_insn.relax.subtype = C (UNCD_JUMP_S, 0); + csky_insn.val[csky_insn.idx++] = 0; + csky_insn.max = U32_LEN_S + 2; + return TRUE; + case OPRND_TYPE_JBSR: + if (do_force2bsr) + *oper = parse_exp (*oper, &csky_insn.e1); + else + *oper = parse_rt (*oper, 1, &csky_insn.e1, -1); + input_line_pointer = *oper; + csky_insn.opcode_end = *oper; + csky_insn.val[csky_insn.idx++] = 0; + return TRUE; + case OPRND_TYPE_REGLIST_DASH_COMMA: + return is_reglist_dash_comma_legal (oper, oprnd); + + case OPRND_TYPE_MSB2SIZE: + case OPRND_TYPE_LSB2SIZE: + { + expressionS e; + char *new_oper = parse_exp (*oper, &e); + if (e.X_op == O_constant) + { + *oper = new_oper; + if (e.X_add_number > 31) + { + SET_ERROR_NUMBER (ERROR_IMM_OVERFLOW, NULL); + return FALSE; + } + csky_insn.val[csky_insn.idx++] = e.X_add_number; + if (oprnd->type == OPRND_TYPE_LSB2SIZE) + { + if (csky_insn.val[csky_insn.idx - 1] > csky_insn.val[csky_insn.idx - 2]) + { + SET_ERROR_NUMBER (ERROR_IMM_OVERFLOW, NULL); + return FALSE; + } + csky_insn.val[csky_insn.idx - 2] -= e.X_add_number; + } + return TRUE; + } + return FALSE; + } + case OPRND_TYPE_AREG_WITH_LSHIFT: + return is_reg_lshift_illegal (oper, 0); + case OPRND_TYPE_AREG_WITH_LSHIFT_FPU: + return is_reg_lshift_illegal (oper, 1); + case OPRND_TYPE_FREG_WITH_INDEX: + if (parse_type_freg (oper, 0)) + { + if (**oper == '[') + { + (*oper)++; + if (is_imm_over_range (oper, 0, 0xf, -1)) + { + if (**oper == ']') + { + unsigned int idx = --csky_insn.idx; + unsigned int val = csky_insn.val[idx]; + (*oper)++; + csky_insn.val[idx - 1] |= val << 4; + return TRUE; + } + else + SET_ERROR_NUMBER (ERROR_MISSING_RSQUARE_BRACKETS, NULL); + } + } + else + SET_ERROR_NUMBER (ERROR_MISSING_LSQUARE_BRACKETS, NULL); + } + return FALSE; + + default: + break; + /* error code. */ + } + return FALSE; +} + +/* Subroutine of parse_operands. */ + +static bfd_boolean +parse_operands_op (char *str, struct csky_opcode_info *op) +{ + int i; + int j; + char *oper = str; + int flag_pass; + + for (i = 0; i < OP_TABLE_NUM && op[i].operand_num != -2; i++) + { + flag_pass = TRUE; + csky_insn.idx = 0; + oper = str; + /* if operand_num = -1, it is a insn with a REGLIST type operand.i. */ + if (!(op[i].operand_num == csky_insn.number + || (op[i].operand_num == -1 && csky_insn.number != 0))) + { + /* The smaller err_num is more serious. */ + SET_ERROR_NUMBER (ERROR_OPERANDS_NUMBER, op[i].operand_num); + flag_pass = FALSE; + continue; + } + + for (j = 0; j < csky_insn.number; j++) + { + while (ISSPACE (*oper)) + oper++; + flag_pass = get_operand_value (&op[i], &oper, + &op[i].oprnd.oprnds[j]); + if (flag_pass == FALSE) + break; + while (ISSPACE (*oper)) + oper++; + /* Skip the ','. */ + if (j < csky_insn.number - 1 && op[i].operand_num != -1) + { + if (*oper == ',') + oper++; + else + { + SET_ERROR_NUMBER (ERROR_MISSING_COMMA, NULL); + flag_pass = FALSE; + break; + } + } + else if (!is_end_of_line[(unsigned char) *oper]) + { + SET_ERROR_NUMBER (ERROR_BAD_END, NULL); + flag_pass = FALSE; + break; + } + else + break; + } + /* Parse operands in one table end. */ + + if (flag_pass == TRUE) + { + /* Parse operands success, set opcode_idx. */ + csky_insn.opcode_idx = i; + return TRUE; + } + else + error_state.opnum = j + 1; + } + /* Parse operands in ALL tables end. */ + return FALSE; +} + +/* Parse the operands according to operand type. */ + +static bfd_boolean +parse_operands (char *str) +{ + char *oper = str; + + /* Parse operands according to flag_force. */ + if (csky_insn.flag_force == INSN_OPCODE16F + && (csky_insn.opcode->isa_flag16 & isa_flag) != 0) + { + if (parse_operands_op (oper, csky_insn.opcode->op16) == TRUE) + { + csky_insn.isize = 2; + return TRUE; + } + return FALSE; + } + else if (csky_insn.flag_force == INSN_OPCODE32F + && (csky_insn.opcode->isa_flag32 & isa_flag) != 0) + { + if (parse_operands_op (oper, csky_insn.opcode->op32) == TRUE) + { + csky_insn.isize = 4; + return TRUE; + } + return FALSE; + } + else + { + if ((csky_insn.opcode->isa_flag16 & isa_flag) != 0 + && parse_operands_op (oper, csky_insn.opcode->op16) == TRUE) + { + csky_insn.isize = 2; + return TRUE; + } + if ((csky_insn.opcode->isa_flag32 & isa_flag) != 0 + && parse_operands_op (oper, csky_insn.opcode->op32) == TRUE) + { + csky_insn.isize = 4; + return TRUE; + } + return FALSE; + } +} + +static bfd_boolean +csky_generate_frags (void) +{ + /* frag more relax reloc. */ + if (csky_insn.flag_force == INSN_OPCODE16F + || !IS_SUPPORT_OPCODE32 (csky_insn.opcode)) + { + csky_insn.output = frag_more (csky_insn.isize); + if (csky_insn.opcode->reloc16) + { + /* 16 bits opcode force, should generate fixup. */ + reloc_howto_type *howto; + howto = bfd_reloc_type_lookup (stdoutput, + csky_insn.opcode->reloc16); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 2, &csky_insn.e1, howto->pc_relative, + csky_insn.opcode->reloc16); + } + } + else if (csky_insn.flag_force == INSN_OPCODE32F) + { + csky_insn.output = frag_more (csky_insn.isize); + if (csky_insn.opcode->reloc32) + { + reloc_howto_type *howto; + howto = bfd_reloc_type_lookup (stdoutput, + csky_insn.opcode->reloc32); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, howto->pc_relative, + csky_insn.opcode->reloc32); + } + } + else if (csky_insn.opcode->relax) + /* Generate the relax information. */ + csky_insn.output = frag_var (rs_machine_dependent, + csky_insn.relax.max, + csky_insn.relax.var, + csky_insn.relax.subtype, + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, 0); + else + { + csky_insn.output = frag_more (csky_insn.isize); + if (csky_insn.opcode->reloc16 && csky_insn.isize == 2) + { + reloc_howto_type *howto; + howto = bfd_reloc_type_lookup (stdoutput, + csky_insn.opcode->reloc16); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 2, &csky_insn.e1, howto->pc_relative, + csky_insn.opcode->reloc16); + } + else if (csky_insn.opcode->reloc32 && csky_insn.isize == 4) + { + reloc_howto_type *howto; + howto = bfd_reloc_type_lookup (stdoutput, + csky_insn.opcode->reloc32); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, howto->pc_relative, + csky_insn.opcode->reloc32); + } + } + return TRUE; +} + +/* Return the bits of VAL shifted according to MASK. The bits of MASK + need not be contiguous. */ + +static int +generate_masked_value (int mask, int val) +{ + int ret = 0; + int bit; + + for (bit = 1; mask; bit = bit << 1) + if (mask & bit) + { + if (val & 0x1) + ret |= bit; + val = val >> 1; + mask &= ~bit; + } + return ret; +} + +/* Return the result of masking operand number OPRND_IDX into the + instruction word according to the information in OPRND. */ + +static int +generate_masked_operand (struct operand *oprnd, int *oprnd_idx) +{ + struct soperand *soprnd = NULL; + int mask; + int val; + if ((unsigned int)oprnd->mask == HAS_SUB_OPERAND) + { + soprnd = (struct soperand *) oprnd; + generate_masked_operand (&soprnd->subs[0], oprnd_idx); + generate_masked_operand (&soprnd->subs[1], oprnd_idx); + return 0; + } + mask = oprnd->mask; + val = csky_insn.val[*oprnd_idx]; + (*oprnd_idx)++; + val = generate_masked_value (mask, val); + csky_insn.inst |= val; + + return 0; +} + +static bfd_boolean +csky_generate_insn (void) +{ + int i = 0; + struct csky_opcode_info *opinfo = NULL; + + if (csky_insn.isize == 4) + opinfo = &csky_insn.opcode->op32[csky_insn.opcode_idx]; + else if (csky_insn.isize == 2) + opinfo = &csky_insn.opcode->op16[csky_insn.opcode_idx]; + + int sidx = 0; + csky_insn.inst = opinfo->opcode; + if (opinfo->operand_num == -1) + { + generate_masked_operand (&opinfo->oprnd.oprnds[i], &sidx); + return 0; + } + else + for (i = 0; i < opinfo->operand_num; i++) + generate_masked_operand (&opinfo->oprnd.oprnds[i], &sidx); + return 0; +} + +/* Main entry point for assembling a single instruction. */ + +void +md_assemble (char *str) +{ + bfd_boolean must_check_literals = TRUE; + csky_insn.isize = 0; + csky_insn.idx = 0; + csky_insn.max = 0; + csky_insn.flag_force = INSN_OPCODE; + csky_insn.macro = NULL; + csky_insn.opcode = NULL; + memset (csky_insn.val, 0, sizeof (int) * MAX_OPRND_NUM); + /* Initialize err_num. */ + error_state.err_num = ERROR_NONE; + mov_r1_before = FALSE; + mov_r1_after = FALSE; + + mapping_state (MAP_TEXT); + /* Tie dwarf2 debug info to every insn if set option --gdwarf2. */ + dwarf2_emit_insn (0); + while (ISSPACE (* str)) + str++; + /* Get opcode from str. */ + if (parse_opcode (str) == FALSE) + { + csky_show_error (ERROR_OPCODE_ILLEGAL, 0, NULL, NULL); + return; + } + + /* If it is a macro instruction, handle it. */ + if (csky_insn.macro != NULL) + { + if (csky_insn.number == csky_insn.macro->oprnd_num) + { + csky_insn.macro->handle_func (); + return; + } + else if (error_state.err_num > ERROR_OPERANDS_NUMBER) + SET_ERROR_NUMBER (ERROR_OPERANDS_NUMBER, csky_insn.macro->oprnd_num); + } + + if (csky_insn.opcode == NULL) + { + SET_ERROR_NUMBER (ERROR_OPCODE_ILLEGAL, NULL); + csky_show_error (error_state.err_num, error_state.opnum, + (void *)error_state.arg1, (void *)error_state.arg1); + return; + } + + /* Parse the operands according to operand type. */ + if (parse_operands (csky_insn.opcode_end) == FALSE) + { + csky_show_error (error_state.err_num, error_state.opnum, + (void *)error_state.arg1, (void *)error_state.arg1); + return; + } + + /* if this insn has work in opcode table, then do it. */ + if (csky_insn.opcode->work != NULL) + must_check_literals = csky_insn.opcode->work (); + else + { + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + } + + /* Adjust for xtrb0/xtrb1/xtrb2/xtrb3/divs/divu in csky v1 ISA. */ + if (mov_r1_after == TRUE) + { + unsigned int mov_insn = CSKYV1_INST_MOV_RX_R1; + mov_insn |= csky_insn.val[0]; + mov_r1_before = TRUE; + csky_insn.output = frag_more (2); + dwarf2_emit_insn (0); + md_number_to_chars (csky_insn.output, mov_insn, 2); + csky_insn.isize += 2; + } + if (mov_r1_before == TRUE) + csky_insn.isize += 2; + + /* Check literal. */ + if (must_check_literals) + { + if (csky_insn.max == 0) + check_literals (csky_insn.opcode->transfer, csky_insn.isize); + else + check_literals (csky_insn.opcode->transfer, csky_insn.max); + } + + insn_reloc = BFD_RELOC_NONE; +} + +/* Attempt to handle option with value C, returning non-zero on success. */ + +int +md_parse_option (int c, const char *arg) +{ + switch (c) + { + case 0: + break; + case OPTION_MARCH: + parse_arch (arg); + break; + case OPTION_MCPU: + parse_cpu (arg); + break; + default: + return 0; + } + return 1; +} + +/* Convert a machine dependent frag. */ +#define PAD_LITERAL_LENGTH 6 +#define opposite_of_stored_comp(insn) (insn ^ 0x04000000) +#define opposite_of_stored_compz(insn) (insn ^ 0x00200000) +#define make_insn(total_length, opcode, operand, operand_length) \ + do { \ + if (total_length > 0) \ + { \ + csky_write_insn (buf, \ + opcode | (operand & ((1 << operand_length) - 1)), \ + total_length); \ + buf += total_length; \ + fragp->fr_fix += total_length; \ + } \ + } while (0) + +#define make_literal(fragp, literal_offset) \ + do { \ + make_insn (literal_offset, PAD_FILL_CONTENT, 0, 0); \ + fix_new (fragp, fragp->fr_fix, 4, fragp->fr_symbol, \ + fragp->fr_offset, 0, BFD_RELOC_CKCORE_ADDR32); \ + make_insn (4, 0, 0, 0); \ + make_insn (2 - literal_offset, PAD_FILL_CONTENT, 0, 0); \ + } while (0) + +void +md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp) +{ + offsetT disp; + char *buf = fragp->fr_fix + fragp->fr_literal; + + gas_assert (fragp->fr_symbol); + if (IS_EXTERNAL_SYM (fragp->fr_symbol, asec)) + disp = 0; + else + disp = (S_GET_VALUE (fragp->fr_symbol) + + fragp->fr_offset + - fragp->fr_address + - fragp->fr_fix); + + switch (fragp->fr_subtype) + { + /* generate new insn. */ + case C (COND_JUMP, DISP12): + case C (UNCD_JUMP, DISP12): + case C (COND_JUMP_PIC, DISP12): + case C (UNCD_JUMP_PIC, DISP12): + { +#define CSKY_V1_B_MASK 0xf8 + unsigned char t0; + disp -= 2; + if (disp & 1) + { + /* Error. odd displacement at %x, next_inst-2. */ + ; + } + disp >>= 1; + + if (!target_big_endian) + { + t0 = buf[1] & CSKY_V1_B_MASK; + md_number_to_chars (buf, disp, 2); + buf[1] = (buf[1] & ~CSKY_V1_B_MASK) | t0; + } + else + { + t0 = buf[0] & CSKY_V1_B_MASK; + md_number_to_chars (buf, disp, 2); + buf[0] = (buf[0] & ~CSKY_V1_B_MASK) | t0; + } + fragp->fr_fix += 2; + break; + } + case C (COND_JUMP, DISP32): + case C (COND_JUMP, UNDEF_WORD_DISP): + { + /* A conditional branch wont fit into 12 bits: + b!cond 1f + jmpi 0f + .align 2 + 0: .long disp + 1: + */ + int first_inst = fragp->fr_fix + fragp->fr_address; + int is_unaligned = (first_inst & 3); + + if (!target_big_endian) + { + /* b!cond instruction. */ + buf[1] ^= 0x08; + /* jmpi instruction. */ + buf[2] = CSKYV1_INST_JMPI & 0xff; + buf[3] = CSKYV1_INST_JMPI >> 8; + } + else + { + /* b!cond instruction. */ + buf[0] ^= 0x08; + /* jmpi instruction. */ + buf[2] = CSKYV1_INST_JMPI >> 8; + buf[3] = CSKYV1_INST_JMPI & 0xff; + } + + if (is_unaligned) + { + if (!target_big_endian) + { + /* bt/bf: jump to pc + 2 + (4 << 1). */ + buf[0] = 4; + /* jmpi: jump to MEM (pc + 2 + (1 << 2)). */ + buf[2] = 1; + } + else + { + /* bt/bf: jump to pc + 2 + (4 << 1). */ + buf[1] = 4; + /* jmpi: jump to MEM (pc + 2 + (1 << 2)). */ + buf[3] = 1; + } + /* Aligned 4 bytes. */ + buf[4] = 0; + buf[5] = 0; + /* .long */ + buf[6] = 0; + buf[7] = 0; + buf[8] = 0; + buf[9] = 0; + + /* Make reloc for the long disp. */ + fix_new (fragp, fragp->fr_fix + 6, 4, + fragp->fr_symbol, fragp->fr_offset, 0, BFD_RELOC_32); + fragp->fr_fix += C32_LEN; + } + else + { + if (!target_big_endian) + { + /* bt/bf: jump to pc + 2 + (3 << 1). */ + buf[0] = 3; + /* jmpi: jump to MEM (pc + 2 + (0 << 2)). */ + buf[2] = 0; + } + else + { + /* bt/bf: jump to pc + 2 + (3 << 1). */ + buf[1] = 3; + /* jmpi: jump to MEM (pc + 2 + (0 << 2)). */ + buf[3] = 0; + } + /* .long */ + buf[4] = 0; + buf[5] = 0; + buf[6] = 0; + buf[7] = 0; + + /* Make reloc for the long disp. */ + fix_new (fragp, fragp->fr_fix + 4, 4, + fragp->fr_symbol, fragp->fr_offset, 0, BFD_RELOC_32); + fragp->fr_fix += C32_LEN; + + /* Frag is actually shorter (see the other side of this ifdef) + but gas isn't prepared for that. We have to re-adjust + the branch displacement so that it goes beyond the + full length of the fragment, not just what we actually + filled in. */ + if (!target_big_endian) + buf[0] = 4; + else + buf[1] = 4; + } + } + break; + + case C (COND_JUMP_PIC, DISP32): + case C (COND_JUMP_PIC, UNDEF_WORD_DISP): + { +#define BYTE_1(a) (target_big_endian ? ((a) & 0xff) : ((a) >> 8)) +#define BYTE_0(a) (target_big_endian ? ((a) >> 8) : ((a) & 0xff)) + /* b!cond 1f + subi sp, 8 + stw r15, (sp, 0) + bsr .L0 + .L0: + lrw r1, 0f + add r1, r15 + addi sp, 8 + jmp r1 + .align 2 + 0: .long (tar_addr - pc) + 1: + */ + int first_inst = fragp->fr_fix + fragp->fr_address; + int is_unaligned = (first_inst & 3); + disp -= 8; + /* Toggle T/F bit. */ + if (! target_big_endian) + buf[1] ^= 0x08; + else + buf[0] ^= 0x08; + buf[2] = BYTE_0 (CSKYV1_INST_SUBI | (7 << 4)); /* subi r0, 8. */ + buf[3] = BYTE_1 (CSKYV1_INST_SUBI | (7 << 4)); + buf[4] = BYTE_0 (CSKYV1_INST_STW | (15 << 8)); /* stw r15, r0. */ + buf[5] = BYTE_1 (CSKYV1_INST_STW | (15 << 8)); + buf[6] = BYTE_0 (CSKYV1_INST_BSR); /* bsr pc + 2. */ + buf[7] = BYTE_1 (CSKYV1_INST_BSR); + buf[8] = BYTE_0 (CSKYV1_INST_LRW | (1 << 8)); /* lrw r1, (tar_addr - pc). */ + buf[9] = BYTE_1 (CSKYV1_INST_LRW | (1 << 8)); + buf[10] = BYTE_0 (CSKYV1_INST_ADDU | (15 << 4) | 1); /* add r1, r15. */ + buf[11] = BYTE_1 (CSKYV1_INST_ADDU | (15 << 4) | 1); + buf[12] = BYTE_0 (CSKYV1_INST_LDW | (15 << 8)); /* ldw r15, r0. */ + buf[13] = BYTE_1 (CSKYV1_INST_LDW | (15 << 8)); + buf[14] = BYTE_0 (CSKYV1_INST_ADDI | (7 << 4)); /* addi r0, 8. */ + buf[15] = BYTE_1 (CSKYV1_INST_ADDI | (7 << 4)); + buf[16] = BYTE_0 (CSKYV1_INST_JMP | 1); /* jmp r1. */ + buf[17] = BYTE_1 (CSKYV1_INST_JMP | 1); + + if (!is_unaligned) + { + if (!target_big_endian) + { + buf[0] = 11; + buf[8] = 3; + buf[20] = disp & 0xff; + buf[21] = (disp >> 8) & 0xff; + buf[22] = (disp >> 16) & 0xff; + buf[23] = (disp >> 24) & 0xff; + } + else /* if !target_big_endian. */ + { + buf[1] = 11; + buf[9] = 3; + buf[20] = (disp >> 24) & 0xff; + buf[21] = (disp >> 16) & 0xff; + buf[22] = (disp >> 8) & 0xff; + buf[23] = disp & 0xff; + } + buf[18] = 0; /* alignment. */ + buf[19] = 0; + fragp->fr_fix += C32_LEN_PIC; + } + else /* if !is_unaligned. */ + { + if (!target_big_endian) + { + buf[0] = 11; + buf[8] = 2; + buf[18] = disp & 0xff; + buf[19] = (disp >> 8) & 0xff; + buf[20] = (disp >> 16) & 0xff; + buf[21] = (disp >> 24) & 0xff; + } + else /* if !target_big_endian. */ + { + buf[1] = 11; + buf[9] = 2; + buf[18] = (disp >> 24) & 0xff; + buf[19] = (disp >> 16) & 0xff; + buf[20] = (disp >> 8) & 0xff; + buf[21] = disp & 0xff; + } + fragp->fr_fix += C32_LEN_PIC; + + } /* end if is_unaligned. */ + } /* end case C (COND_JUMP_PIC, DISP32)/C (COND_JUMP_PIC, UNDEF_WORD_DISP). */ + break; + case C (UNCD_JUMP, DISP32): + case C (UNCD_JUMP, UNDEF_WORD_DISP): + { + /* jmpi 0f + .align 2 + 0: .long disp. */ + int first_inst = fragp->fr_fix + fragp->fr_address; + int is_unaligned = (first_inst & 3); + /* Build jmpi. */ + buf[0] = BYTE_0 (CSKYV1_INST_JMPI); + buf[1] = BYTE_1 (CSKYV1_INST_JMPI); + if (!is_unaligned) + { + if (!target_big_endian) + buf[0] = 1; + else + buf[1] = 1; + /* Alignment. */ + buf[2] = 0; + buf[3] = 0; + /* .long */ + buf[4] = 0; + buf[5] = 0; + buf[6] = 0; + buf[7] = 0; + fix_new (fragp, fragp->fr_fix + 4, 4, + fragp->fr_symbol, fragp->fr_offset, 0, BFD_RELOC_32); + fragp->fr_fix += U32_LEN; + } + else /* if is_unaligned. */ + { + if (!target_big_endian) + buf[0] = 0; + else + buf[1] = 0; + /* .long */ + buf[2] = 0; + buf[3] = 0; + buf[4] = 0; + buf[5] = 0; + fix_new (fragp, fragp->fr_fix + 2, 4, + fragp->fr_symbol, fragp->fr_offset, 0, BFD_RELOC_32); + fragp->fr_fix += U32_LEN; + + } + } + break; + case C (UNCD_JUMP_PIC, DISP32): + case C (UNCD_JUMP_PIC, UNDEF_WORD_DISP): + { + /* subi sp, 8 + stw r15, (sp) + bsr .L0 + .L0: + lrw r1, 0f + add r1, r15 + ldw r15, (sp) + addi sp, 8 + jmp r1 + .align 2 + 0: .long (tar_add - pc) + 1: + */ + /* If the b!cond is 4 byte aligned, the literal which would + go at x+4 will also be aligned. */ + int first_inst = fragp->fr_fix + fragp->fr_address; + int is_unaligned = (first_inst & 3); + disp -= 6; + + buf[0] = BYTE_0 (CSKYV1_INST_SUBI | (7 << 4)); /* subi r0, 8. */ + buf[1] = BYTE_1 (CSKYV1_INST_SUBI | (7 << 4)); + buf[2] = BYTE_0 (CSKYV1_INST_STW | (15 << 8)); /* stw r15, r0. */ + buf[3] = BYTE_1 (CSKYV1_INST_STW | (15 << 8)); + buf[4] = BYTE_0 (CSKYV1_INST_BSR); /* bsr pc + 2. */ + buf[5] = BYTE_1 (CSKYV1_INST_BSR); + buf[6] = BYTE_0 (CSKYV1_INST_LRW | (1 << 8)); /* lrw r1, (tar_addr - pc). */ + buf[7] = BYTE_1 (CSKYV1_INST_LRW | (1 << 8)); + buf[8] = BYTE_0 (CSKYV1_INST_ADDU | (15 << 4) | 1); /* add r1, r15. */ + buf[9] = BYTE_1 (CSKYV1_INST_ADDU | (15 << 4) | 1); + buf[10] = BYTE_0 (CSKYV1_INST_LDW | (15 << 8)); /* ldw r15, r0. */ + buf[11] = BYTE_1 (CSKYV1_INST_LDW | (15 << 8)); + buf[12] = BYTE_0 (CSKYV1_INST_ADDI | (7 << 4)); /* addi r0, 8. */ + buf[13] = BYTE_1 (CSKYV1_INST_ADDI | (7 << 4)); + buf[14] = BYTE_0 (CSKYV1_INST_JMP | 1); /* jmp r1. */ + buf[15] = BYTE_1 (CSKYV1_INST_JMP | 1); + + if (is_unaligned) + { + if (!target_big_endian) + { + buf[6] = 3; + buf[18] = disp & 0xff; + buf[19] = (disp >> 8) & 0xff; + buf[20] = (disp >> 16) & 0xff; + buf[21] = (disp >> 24) & 0xff; + } + else + { + buf[7] = 3; + buf[18] = (disp >> 24) & 0xff; + buf[19] = (disp >> 16) & 0xff; + buf[20] = (disp >> 8) & 0xff; + buf[21] = disp & 0xff; + } + buf[16] = 0; + buf[17] = 0; + fragp->fr_fix += U32_LEN_PIC; + } + else + { + if (!target_big_endian) + { + buf[6] = 2; + buf[16] = disp & 0xff; + buf[17] = (disp >> 8) & 0xff; + buf[18] = (disp >> 16) & 0xff; + buf[19] = (disp >> 24) & 0xff; + } + else + { + buf[7] = 2; + buf[16] = (disp >> 24) & 0xff; + buf[17] = (disp >> 16) & 0xff; + buf[18] = (disp >> 8) & 0xff; + buf[19] = disp & 0xff; + } + fragp->fr_fix += U32_LEN_PIC; + } + } + break; + case COND_DISP10: + case SCOND_DISP10: + case UNCD_DISP10: + case JCOND_DISP10: + case JUNCD_DISP10: + { + unsigned int inst = csky_read_insn (buf, 2); + inst |= (disp >> 1) & ((1 << 10) - 1); + csky_write_insn (buf, inst, 2); + fragp->fr_fix += 2; + break; + } + case SCOND_DISP16: + { + unsigned int inst = csky_read_insn (buf, 2); + + if (inst == CSKYV2_INST_BT16) + inst = CSKYV2_INST_BF16; + else + inst = CSKYV2_INST_BT16; + make_insn (2, inst, (2 + 4) >> 1, 10); + if (IS_EXTERNAL_SYM (fragp->fr_symbol, asec)) + fix_new (fragp, fragp->fr_fix, 4, + fragp->fr_symbol, fragp->fr_offset, 1, + BFD_RELOC_CKCORE_PCREL_IMM16BY2); + disp -= 2; + inst = CSKYV2_INST_BR32 | ((disp >> 1) & ((1 << 16) - 1)); + csky_write_insn (buf, inst, 4); + fragp->fr_fix += 4; + break; + } + case COND_DISP16: + case JCOND_DISP16: + { + unsigned int inst = csky_read_insn (buf, 2); + + if (inst == CSKYV2_INST_BT16) + inst = CSKYV2_INST_BT32; + else + inst = CSKYV2_INST_BF32; + if (IS_EXTERNAL_SYM (fragp->fr_symbol, asec)) + fix_new (fragp, fragp->fr_fix, 4, + fragp->fr_symbol, fragp->fr_offset, 1, + BFD_RELOC_CKCORE_PCREL_IMM16BY2); + inst |= (disp >> 1) & ((1 << 16) - 1); + csky_write_insn (buf, inst, 4); + fragp->fr_fix += 4; + break; + } + case LRW_DISP7: + { + unsigned int inst = csky_read_insn (buf, 2); + int imm; + imm = (disp + 2) >> 2; + inst |= (imm >> 5) << 8; + make_insn (2, inst, (imm & 0x1f), 5); + break; + } + case LRW2_DISP8: + { + unsigned int inst = csky_read_insn (buf, 2); + int imm = (disp + 2) >> 2; + if (imm >= 0x80) + { + inst &= 0xe0; + inst |= (~((imm >> 5) << 8)) & 0x300; + make_insn (2, inst, (~imm & 0x1f), 5); + } + else + { + inst |= (imm >> 5) << 8; + make_insn (2, inst, (imm & 0x1f), 5); + } + break; + } + case LRW_DISP16: + { + unsigned int inst = csky_read_insn (buf, 2); + inst = CSKYV2_INST_LRW32 | (((inst & 0xe0) >> 5) << 16); + if (IS_EXTERNAL_SYM (fragp->fr_symbol, asec)) + fix_new (fragp, fragp->fr_fix, 4, + fragp->fr_symbol, fragp->fr_offset, 1, + BFD_RELOC_CKCORE_PCREL_IMM16BY4); + make_insn (4, inst, ((disp + 2) >> 2), 16); + break; + } + case JCOMPZ_DISP16: + { + unsigned int inst = csky_read_insn (buf, 4); + make_insn (4, inst, disp >> 1, 16); + } + break; + case JCOMPZ_DISP32: + { + unsigned int inst = csky_read_insn (buf, 4); + int literal_offset; + make_insn (4, opposite_of_stored_compz (inst), + (4 + 4 + PAD_LITERAL_LENGTH) >> 1, 16); + literal_offset = ((fragp->fr_address + fragp->fr_fix) % 4 == 0 + ? 0 : 2); + make_insn (4, CSKYV2_INST_JMPI32, (4 + literal_offset + 2) >> 2, 10); + make_literal (fragp, literal_offset); + } + break; + case JUNCD_DISP16: + case UNCD_DISP16: + { + if (IS_EXTERNAL_SYM (fragp->fr_symbol, asec)) + fix_new (fragp, fragp->fr_fix, 4, + fragp->fr_symbol, fragp->fr_offset, 1, + BFD_RELOC_CKCORE_PCREL_IMM16BY2); + make_insn (4, CSKYV2_INST_BR32, disp >> 1, 16); + } + break; + case JCOND_DISP32: + { + /* 'jbt'/'jbf'-> <bf16/bt16>; jmpi32; [pad16]+literal32 */ + unsigned int inst = csky_read_insn (buf, 2); + int literal_offset; + + if (inst == CSKYV2_INST_BT16) + inst = CSKYV2_INST_BF16; + else + inst = CSKYV2_INST_BT16; + make_insn (2, inst, (2 + 4 + PAD_LITERAL_LENGTH) >> 1, 10); + literal_offset = ((fragp->fr_address + fragp->fr_fix) % 4 == 0 + ? 0 : 2); + make_insn (4, CSKYV2_INST_JMPI32, (4 + literal_offset + 2) >> 2, 10); + make_literal (fragp, literal_offset); + break; + } + case JUNCD_DISP32: + { + int literal_offset; + literal_offset = ((fragp->fr_address + fragp->fr_fix) % 4 == 0 + ? 0 : 2); + make_insn (4, CSKYV2_INST_JMPI32, (4 + literal_offset + 2) >> 2, 10); + make_literal (fragp, literal_offset); + } + break; + case RELAX_OVERFLOW: + csky_branch_report_error (fragp->fr_file, fragp->fr_line, + fragp->fr_symbol, disp); + break; + default: + abort (); + break; + } +} + +/* Round up a section size to the appropriate boundary. */ + +valueT +md_section_align (segT segment ATTRIBUTE_UNUSED, + valueT size) +{ + return size; +} + +/* MD interface: Symbol and relocation handling. */ + +void md_csky_end (void) +{ + dump_literals (0); +} + +/* Return the address within the segment that a PC-relative fixup is + relative to. */ + +long +md_pcrel_from_section (fixS * fixP, segT seg) +{ + /* If the symbol is undefined or defined in another section + we leave the add number alone for the linker to fix it later. */ + if (fixP->fx_addsy != (symbolS *) NULL + && (! S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != seg)) + return fixP->fx_size; + + /* The case where we are going to resolve things. */ + return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; +} + +/* csky_cons_fix_new is called via the expression parsing code when a + reloc is needed. We use this hook to get the correct .got reloc. */ + +void +csky_cons_fix_new (fragS *frag, + unsigned int off, + unsigned int len, + expressionS *exp, + bfd_reloc_code_real_type reloc) +{ + fixS *fixP; + + if (BFD_RELOC_CKCORE_GOTOFF == insn_reloc + || BFD_RELOC_CKCORE_GOTPC == insn_reloc + || BFD_RELOC_CKCORE_GOT32 == insn_reloc + || BFD_RELOC_CKCORE_PLT32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_LE32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_GD32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_LDM32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_LDO32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_IE32 == insn_reloc) + reloc = insn_reloc; + else + switch (len) + { + case 1: + reloc = BFD_RELOC_8; + break; + case 2: + reloc = BFD_RELOC_16; + break; + case 4: + reloc = BFD_RELOC_32; + break; + case 8: + reloc = BFD_RELOC_64; + break; + default: + as_bad (_("unsupported BFD relocation size %d"), len); + reloc = BFD_RELOC_32; + break; + } + fixP = fix_new_exp (frag, off, (int) len, exp, 0, reloc); + if (BFD_RELOC_CKCORE_TLS_IE32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_GD32 == insn_reloc + || BFD_RELOC_CKCORE_TLS_LDM32 == insn_reloc) + { + fixP->tc_fix_data.frag = literal_insn_offset->tls_addend.frag; + fixP->tc_fix_data.offset = literal_insn_offset->tls_addend.offset; + } +} + +/* See whether we need to force a relocation into the output file. + This is used to force out switch and PC relative relocations when + relaxing. */ + +int +csky_force_relocation (fixS * fix) +{ + if (fix->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fix->fx_r_type == BFD_RELOC_VTABLE_ENTRY + || fix->fx_r_type == BFD_RELOC_RVA + || fix->fx_r_type == BFD_RELOC_CKCORE_ADDR_HI16 + || fix->fx_r_type == BFD_RELOC_CKCORE_ADDR_LO16 + || fix->fx_r_type == BFD_RELOC_CKCORE_TOFFSET_LO16 + || fix->fx_r_type == BFD_RELOC_CKCORE_DOFFSET_LO16) + return 1; + + if (fix->fx_addsy == NULL) + return 0; + + if (do_use_branchstub + && fix->fx_r_type == BFD_RELOC_CKCORE_PCREL_IMM26BY2 + && (symbol_get_bfdsym (fix->fx_addsy)->flags & BSF_FUNCTION)) + return 1; + return S_FORCE_RELOC (fix->fx_addsy, fix->fx_subsy == NULL); +} + +/* Return true if the fix can be handled by GAS, false if it must + be passed through to the linker. */ + +bfd_boolean +csky_fix_adjustable (fixS * fixP) +{ + if (fixP->fx_addsy == NULL) + return 1; + + /* We need the symbol name for the VTABLE entries. */ + if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY + || fixP->fx_r_type == BFD_RELOC_CKCORE_PLT32 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOT32 + || fixP->fx_r_type == BFD_RELOC_CKCORE_PLT12 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOT12 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOT_HI16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOT_LO16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_PLT_HI16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_PLT_LO16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOTOFF + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOTOFF_HI16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOTOFF_LO16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_ADDR_HI16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_ADDR_LO16 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOT_IMM18BY4 + || fixP->fx_r_type == BFD_RELOC_CKCORE_PLT_IMM18BY4 + || fixP->fx_r_type == BFD_RELOC_CKCORE_GOTOFF_IMM18 + || fixP->fx_r_type == BFD_RELOC_CKCORE_TLS_LE32 + || fixP->fx_r_type == BFD_RELOC_CKCORE_TLS_IE32 + || fixP->fx_r_type == BFD_RELOC_CKCORE_TLS_GD32 + || fixP->fx_r_type == BFD_RELOC_CKCORE_TLS_LDM32 + || fixP->fx_r_type == BFD_RELOC_CKCORE_TLS_LDO32) + return 0; + + if (do_use_branchstub + && fixP->fx_r_type == BFD_RELOC_CKCORE_PCREL_IMM26BY2 + && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)) + return 0; + + return 1; +} + +void +md_apply_fix (fixS *fixP, + valueT *valP, + segT seg) +{ + reloc_howto_type *howto; + /* Note: use offsetT because it is signed, valueT is unsigned. */ + offsetT val = *valP; + char *buf = fixP->fx_frag->fr_literal + fixP->fx_where; + + /* if fx_done = 0, fixup will also be processed in + * tc_gen_reloc() after md_apply_fix(). */ + fixP->fx_done = 0; + + /* If the fix is relative to a symbol which is not defined, or not + in the same segment as the fix, we cannot resolve it here. */ + if (IS_CSKY_V1 (mach_flag) && fixP->fx_addsy != NULL + && (! S_IS_DEFINED (fixP->fx_addsy) + || S_GET_SEGMENT (fixP->fx_addsy) != seg)) + { + switch (fixP->fx_r_type) + { + /* Data fx_addnumber is greater than 16 bits, + so fx_addnumber is assigned zero. */ + case BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2: + *valP = 0; + break; + case BFD_RELOC_CKCORE_TLS_IE32: + case BFD_RELOC_CKCORE_TLS_LDM32: + case BFD_RELOC_CKCORE_TLS_GD32: + { + struct tls_addend *ta = &(fixP->tc_fix_data); + fixP->fx_offset = (fixP->fx_frag->fr_address + fixP->fx_where + - (ta->frag->fr_address + ta->offset)); + } + /* Fall through. */ + case BFD_RELOC_CKCORE_TLS_LE32: + case BFD_RELOC_CKCORE_TLS_LDO32: + S_SET_THREAD_LOCAL (fixP->fx_addsy); + break; + default: + break; + } +#ifdef OBJ_ELF + /* For ELF we can just return and let the reloc that will be generated + take care of everything. For COFF we still have to insert 'val' + into the insn since the addend field will be ignored. */ + return; +#endif + } + + /* We can handle these relocs. */ + switch (fixP->fx_r_type) + { + case BFD_RELOC_CKCORE_PCREL32: + break; + case BFD_RELOC_VTABLE_INHERIT: + fixP->fx_r_type = BFD_RELOC_CKCORE_GNU_VTINHERIT; + if (fixP->fx_addsy && !S_IS_DEFINED (fixP->fx_addsy) + && !S_IS_WEAK (fixP->fx_addsy)) + S_SET_WEAK (fixP->fx_addsy); + break; + case BFD_RELOC_VTABLE_ENTRY: + fixP->fx_r_type = BFD_RELOC_CKCORE_GNU_VTENTRY; + break; + case BFD_RELOC_CKCORE_GOT12: + case BFD_RELOC_CKCORE_PLT12: + case BFD_RELOC_CKCORE_ADDR_HI16: + case BFD_RELOC_CKCORE_ADDR_LO16: + case BFD_RELOC_CKCORE_TOFFSET_LO16: + case BFD_RELOC_CKCORE_DOFFSET_LO16: + case BFD_RELOC_CKCORE_GOT_HI16: + case BFD_RELOC_CKCORE_GOT_LO16: + case BFD_RELOC_CKCORE_PLT_HI16: + case BFD_RELOC_CKCORE_PLT_LO16: + case BFD_RELOC_CKCORE_GOTPC_HI16: + case BFD_RELOC_CKCORE_GOTPC_LO16: + case BFD_RELOC_CKCORE_GOTOFF_HI16: + case BFD_RELOC_CKCORE_GOTOFF_LO16: + case BFD_RELOC_CKCORE_DOFFSET_IMM18: + case BFD_RELOC_CKCORE_DOFFSET_IMM18BY2: + case BFD_RELOC_CKCORE_DOFFSET_IMM18BY4: + case BFD_RELOC_CKCORE_GOTOFF_IMM18: + case BFD_RELOC_CKCORE_GOT_IMM18BY4: + case BFD_RELOC_CKCORE_PLT_IMM18BY4: + break; + case BFD_RELOC_CKCORE_TLS_IE32: + case BFD_RELOC_CKCORE_TLS_LDM32: + case BFD_RELOC_CKCORE_TLS_GD32: + { + struct tls_addend *ta = &(fixP->tc_fix_data); + fixP->fx_offset = (fixP->fx_frag->fr_address + fixP->fx_where + - (ta->frag->fr_address + ta->offset)); + } + /* Fall through. */ + case BFD_RELOC_CKCORE_TLS_LE32: + case BFD_RELOC_CKCORE_TLS_LDO32: + S_SET_THREAD_LOCAL (fixP->fx_addsy); + break; + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_CKCORE_ADDR32; + /* Fall through. */ + case BFD_RELOC_16: + case BFD_RELOC_8: + if (fixP->fx_addsy == NULL) + { + if (fixP->fx_size == 4) + ; + else if (fixP->fx_size == 2 && val >= -32768 && val <= 32767) + ; + else if (fixP->fx_size == 1 && val >= -256 && val <= 255) + ; + else + abort (); + md_number_to_chars (buf, val, fixP->fx_size); + fixP->fx_done = 1; + } + break; + case BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2: + if (fixP->fx_addsy == 0 && val > -2 KB && val < 2 KB) + { + long nval = (val >> 1) & 0x7ff; + nval |= CSKYV1_INST_BSR; + csky_write_insn (buf, nval, 2); + fixP->fx_done = 1; + } + else + *valP = 0; + break; + case BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2: + if (fixP->fx_addsy == 0) + { + if (val >= -(1 << 26) && val < (1 << 26)) + { + unsigned int nval = ((val + fixP->fx_size) >> 1) & 0x3ffffff; + nval |= CSKYV2_INST_BSR32; + + csky_write_insn (buf, nval, 4); + } + /* If bsr32 cannot reach, + generate 'lrw r25,label;jsr r25' instead of 'jsri label'. */ + else if (IS_CSKY_ARCH_810 (mach_flag)) + { + howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); + valueT opcode = csky_read_insn (buf, 4); + opcode = (opcode & howto->dst_mask) | CSKYV2_INST_JSRI_TO_LRW; + csky_write_insn (buf, opcode, 4); + opcode = CSKYV2_INST_JSR_R26; + csky_write_insn (buf + 4, opcode, 4); + } + fixP->fx_done = 1; + } + break; + + default: + { + valueT opcode; + offsetT min, max; + unsigned int issigned = 0; + + if (fixP->fx_addsy) + break; + + howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); + if (howto == NULL) + { + if (fixP->fx_size == 4 + || (fixP->fx_size == 2 && val >= -32768 && val <= 32767) + || (fixP->fx_size == 1 && val >= -256 && val <= 255)) + { + md_number_to_chars (buf, val, fixP->fx_size); + fixP->fx_done = 1; + break; + } + else + abort (); + } + + if (IS_CSKY_V2 (mach_flag)) + val += fixP->fx_size; + + if (howto->rightshift == 2) + val += 2; + + val >>= howto->rightshift; + + switch (fixP->fx_r_type) + { + /* Offset is unsigned. */ + case BFD_RELOC_CKCORE_PCREL_IMM8BY4: + case BFD_RELOC_CKCORE_PCREL_IMM10BY4: + case BFD_RELOC_CKCORE_PCREL_IMM16BY4: + max = (offsetT) howto->dst_mask; + min = 0; + break; + /* lrw16. */ + case BFD_RELOC_CKCORE_PCREL_IMM7BY4: + if (do_extend_lrw) + max = (offsetT)((1 << (howto->bitsize + 1)) - 2); + else + max = (offsetT)((1 << howto->bitsize) - 1); + min = 0; + break; + /* flrws, flrwd: the offset bits are divided in two parts. */ + case BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4: + max = (offsetT)((1 << howto->bitsize) - 1); + min = 0; + break; + /* Offset is signed. */ + default: + max = (offsetT)(howto->dst_mask >> 1); + min = - max - 1; + issigned = 1; + } + if (val < min || val > max) + { + csky_branch_report_error (fixP->fx_file, fixP->fx_line, + fixP->fx_addsy, val); + return; + } + opcode = csky_read_insn (buf, fixP->fx_size); + /* Clear redundant bits brought from the last + operation if there is any. */ + if (do_extend_lrw && (opcode & 0xfc00) == CSKYV2_INST_LRW16) + val &= 0xff; + else + val &= issigned ? (offsetT)(howto->dst_mask) : max; + + if (fixP->fx_r_type == BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4) + val = (val & 0xf) << 12; + + if (fixP->fx_size == 2 && (opcode & 0xfc00) == CSKYV2_INST_LRW16) + { + /* 8 bit offset lrw16. */ + if (val >= 0x80) + csky_write_insn (buf, + ((~val & 0x1f) + | ((~val & 0x60) << 3) | (opcode & 0xe0)), + fixP->fx_size); + /* 7 bit offset lrw16. */ + else + csky_write_insn (buf, + (val & 0x1f) | ((val & 0x60) << 3) | opcode, + fixP->fx_size); + } + else if (fixP->fx_size == 4 + && (opcode & 0xfe1ffe00) == CSKYV2_INST_FLRW) + csky_write_insn (buf, + ((val & 0xf) << 4) | ((val & 0xf0) << 17) | opcode, + fixP->fx_size); + else + csky_write_insn (buf, val | opcode, fixP->fx_size); + fixP->fx_done = 1; + break; + } + } + fixP->fx_addnumber = val; +} + +/* Translate internal representation of relocation info to BFD target + format. */ + +arelent * +tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP) +{ + arelent *rel; + + rel = xmalloc (sizeof (arelent)); + rel->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); + *rel->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy); + rel->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); + rel->addend = fixP->fx_offset; + if (rel->howto == NULL) + { + as_bad_where (fixP->fx_file, fixP->fx_line, + _("cannot represent `%s' relocation in object file"), + bfd_get_reloc_code_name (fixP->fx_r_type)); + + /* Set howto to a garbage value so that we can keep going. */ + rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); + } + gas_assert (rel->howto != NULL); + rel->address = fixP->fx_frag->fr_address + fixP->fx_where; + return rel; +} + +/* Relax a fragment by scanning TC_GENERIC_RELAX_TABLE. */ + +long +csky_relax_frag (segT segment, fragS *fragP, long stretch) +{ + const relax_typeS *this_type; + const relax_typeS *start_type; + relax_substateT next_state; + relax_substateT this_state; + offsetT growth; + offsetT aim; + addressT target; + addressT address; + symbolS *symbolP; + const relax_typeS *table; + + target = fragP->fr_offset; + address = fragP->fr_address; + table = TC_GENERIC_RELAX_TABLE; + this_state = fragP->fr_subtype; + start_type = this_type = table + this_state; + symbolP = fragP->fr_symbol; + + if (symbolP) + { + fragS *sym_frag; + + sym_frag = symbol_get_frag (symbolP); + +#ifndef DIFF_EXPR_OK + know (sym_frag != NULL); +#endif + know (S_GET_SEGMENT (symbolP) != absolute_section + || sym_frag == &zero_address_frag); + target += S_GET_VALUE (symbolP); + + /* If SYM_FRAG has yet to be reached on this pass, assume it + will move by STRETCH just as we did, unless there is an + alignment frag between here and SYM_FRAG. An alignment may + well absorb any STRETCH, and we don't want to choose a larger + branch insn by overestimating the needed reach of this + branch. It isn't critical to calculate TARGET exactly; We + know we'll be doing another pass if STRETCH is non-zero. */ + + if (stretch != 0 + && sym_frag->relax_marker != fragP->relax_marker + && S_GET_SEGMENT (symbolP) == segment) + { + fragS *f; + + /* Adjust stretch for any alignment frag. Note that if have + been expanding the earlier code, the symbol may be + defined in what appears to be an earlier frag. FIXME: + This doesn't handle the fr_subtype field, which specifies + a maximum number of bytes to skip when doing an + alignment. */ + for (f = fragP; f != NULL && f != sym_frag; f = f->fr_next) + { + if (f->fr_type == rs_align || f->fr_type == rs_align_code) + { + if (stretch < 0) + stretch = -((-stretch) + & ~((1 << (int) f->fr_offset) - 1)); + else + stretch &= ~((1 << (int) f->fr_offset) - 1); + } + if (stretch == 0) + break; + } + if (f != 0) + target += stretch; + } + } + + aim = target - address - fragP->fr_fix; + + /* If the fragP->fr_symbol is extern symbol, aim should be 0. */ + if (fragP->fr_symbol && S_GET_SEGMENT (symbolP) != segment) + aim = 0; + + if (aim < 0) + { + /* Look backwards. */ + for (next_state = this_type->rlx_more; next_state;) + if (aim >= this_type->rlx_backward) + next_state = 0; + else + { + /* Grow to next state. */ + this_state = next_state; + this_type = table + this_state; + next_state = this_type->rlx_more; + } + } + else + { + /* Look forwards. */ + for (next_state = this_type->rlx_more; next_state;) + if (aim <= this_type->rlx_forward) + next_state = 0; + else + { + /* Grow to next state. */ + this_state = next_state; + this_type = table + this_state; + next_state = this_type->rlx_more; + } + } + + growth = this_type->rlx_length - start_type->rlx_length; + if (growth != 0) + fragP->fr_subtype = this_state; + return growth; +} + +int +md_estimate_size_before_relax (fragS * fragp, + segT segtype) +{ + switch (fragp->fr_subtype) + { + case COND_DISP10: + case COND_DISP16: + case SCOND_DISP10: + case SCOND_DISP16: + case UNCD_DISP10: + case UNCD_DISP16: + case JCOND_DISP10: + case JCOND_DISP16: + case JCOND_DISP32: + case JUNCD_DISP10: + case JUNCD_DISP16: + case JUNCD_DISP32: + case JCOMPZ_DISP16: + case JCOMPZ_DISP32: + case BSR_DISP26: + case LRW_DISP7: + case LRW2_DISP8: + case LRW_DISP16: + gas_assert (fragp->fr_symbol); + if (IS_EXTERNAL_SYM (fragp->fr_symbol, segtype)) + while (csky_relax_table[fragp->fr_subtype].rlx_more > RELAX_OVERFLOW) + fragp->fr_subtype = csky_relax_table[fragp->fr_subtype].rlx_more; + return csky_relax_table[fragp->fr_subtype].rlx_length; + + /* C-SKY V1 relaxes. */ + case C (UNCD_JUMP, UNDEF_DISP): + case C (UNCD_JUMP_PIC, UNDEF_DISP): + if (!fragp->fr_symbol) + fragp->fr_subtype = C (UNCD_JUMP_S, DISP12); + else if (S_GET_SEGMENT (fragp->fr_symbol) == segtype) + fragp->fr_subtype = C (UNCD_JUMP_S, DISP12); + else + fragp->fr_subtype = C (UNCD_JUMP_S, UNDEF_WORD_DISP); + break; + + case C (COND_JUMP, UNDEF_DISP): + case C (COND_JUMP_PIC, UNDEF_DISP): + if (fragp->fr_symbol + && S_GET_SEGMENT (fragp->fr_symbol) == segtype) + /* Got a symbol and it's defined in this segment, become byte + sized. Maybe it will fix up. */ + fragp->fr_subtype = C (COND_JUMP_S, DISP12); + else if (fragp->fr_symbol) + /* It's got a segment, but it's not ours, so it will always be + long. */ + fragp->fr_subtype = C (COND_JUMP_S, UNDEF_WORD_DISP); + else + /* We know the abs value. */ + fragp->fr_subtype = C (COND_JUMP_S, DISP12); + break; + + case C (UNCD_JUMP, DISP12): + case C (UNCD_JUMP, DISP32): + case C (UNCD_JUMP, UNDEF_WORD_DISP): + case C (COND_JUMP, DISP12): + case C (COND_JUMP, DISP32): + case C (COND_JUMP, UNDEF_WORD_DISP): + case C (UNCD_JUMP_PIC, DISP12): + case C (UNCD_JUMP_PIC, DISP32): + case C (UNCD_JUMP_PIC, UNDEF_WORD_DISP): + case C (COND_JUMP_PIC, DISP12): + case C (COND_JUMP_PIC, DISP32): + case C (COND_JUMP_PIC, UNDEF_WORD_DISP): + case RELAX_OVERFLOW: + break; + + default: + abort (); + } + return csky_relax_table[fragp->fr_subtype].rlx_length; +} + +/* Parse opcode like: "op oprnd1, oprnd2, oprnd3". */ + +static void +csky_macro_md_assemble (const char *op, + const char *oprnd1, + const char *oprnd2, + const char *oprnd3) +{ + char str[80]; + str[0] = '\0'; + strcat (str, op); + if (oprnd1 != NULL) + { + strcat (str, " "); + strcat (str, oprnd1); + if (oprnd2 != NULL) + { + strcat (str, ","); + strcat (str, oprnd2); + if (oprnd3 != NULL) + { + strcat (str, ","); + strcat (str, oprnd3); + } + } + } + md_assemble (str); + return; +} + +/* Get the string of operand. */ + +static int +csky_get_macro_operand (char *src_s, char *dst_s, char end_sym) +{ + int nlen = 0; + while (ISSPACE (*src_s)) + ++src_s; + while (*src_s != end_sym) + dst_s[nlen++] = *(src_s++); + dst_s[nlen] = '\0'; + return nlen; +} + +/* idly 4 -> idly4. */ + +static void +csky_idly (void) +{ + char *s = csky_insn.opcode_end; + if (!is_imm_over_range (&s, 4, 4, -1)) + { + as_bad (_("second operand must be 4")); + return; + } + csky_macro_md_assemble ("idly4", NULL, NULL, NULL); + return; +} + +/* rolc rd, 1 or roltc rd, 1 -> addc rd, rd. */ + +static void +csky_rolc (void) +{ + char reg[10]; + char *s = csky_insn.opcode_end; + + s += csky_get_macro_operand (s, reg, ','); + ++s; + + if (is_imm_over_range (&s, 1, 1, -1)) + { + csky_macro_md_assemble ("addc", reg, reg, NULL); + return; + } + else + as_bad (_("second operand must be 1")); +} + +/* sxtrb0(1)(2) r1, rx -> xtbr0(1)(2) r1,rx; sextb r1. */ + +static void +csky_sxtrb (void) +{ + char reg1[10]; + char reg2[10]; + + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, ','); + ++s; + csky_get_macro_operand (s, reg2, '\0'); + + csky_macro_md_assemble (csky_insn.macro->name + 1, reg1, reg2, NULL); + csky_macro_md_assemble ("sextb", reg1, NULL, NULL); + return; +} + +static void +csky_movtf (void) +{ + char reg1[10]; + char reg2[10]; + char reg3[10]; + + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, ','); + ++s; + + s += csky_get_macro_operand (s, reg2, ','); + ++s; + + s += csky_get_macro_operand (s, reg3, '\0'); + ++s; + csky_macro_md_assemble ("movt", reg1, reg2, NULL); + csky_macro_md_assemble ("movf", reg1, reg3, NULL); + return; +} + +static bfd_boolean +get_macro_reg_vals (int *reg1, int *reg2, int *reg3) +{ + int nlen; + char *s = csky_insn.opcode_end; + + *reg1 = csky_get_reg_val (s, &nlen); + s += nlen; + if (*s != ',') + { + csky_show_error (ERROR_MISSING_COMMA, 0, NULL, NULL); + return FALSE; + } + s++; + *reg2 = csky_get_reg_val (s, &nlen); + s += nlen; + if (*s != ',') + { + csky_show_error (ERROR_MISSING_COMMA, 0, NULL, NULL); + return FALSE; + } + s++; + *reg3 = csky_get_reg_val (s, &nlen); + s += nlen; + if (*s != '\0') + { + csky_show_error (ERROR_BAD_END, 0, NULL, NULL); + return FALSE; + } + if (*reg1 == -1 || *reg2 == -1 || *reg3 == -1) + { + as_bad (_("register number out of range")); + return FALSE; + } + if (*reg1 != *reg2) + { + as_bad (_("dest and source1 must be the same register")); + return FALSE; + } + if (*reg1 >= 15 || *reg3 >= 15) + { + as_bad (_("64-bit operator src/dst register must be less than 15")); + return FALSE; + } + return TRUE; +} + +/* addc64 rx, rx, ry -> cmplt rx, rx, addc rx, ry, addc rx+1, ry+1. */ + +static void +csky_addc64 (void) +{ + int reg1; + int reg2; + int reg3; + + if (!get_macro_reg_vals (®1, ®2, ®3)) + return; + csky_macro_md_assemble ("cmplt", + csky_general_reg[reg1], + csky_general_reg[reg1], + NULL); + csky_macro_md_assemble ("addc", + csky_general_reg[reg1 + (target_big_endian ? 1 : 0)], + csky_general_reg[reg3 + (target_big_endian ? 1 : 0)], + NULL); + csky_macro_md_assemble ("addc", + csky_general_reg[reg1 + (target_big_endian ? 0 : 1)], + csky_general_reg[reg3 + (target_big_endian ? 0 : 1)], + NULL); + return; +} + +/* subc64 rx, rx, ry -> cmphs rx, rx, subc rx, ry, subc rx+1, ry+1. */ + +static void +csky_subc64 (void) +{ + int reg1; + int reg2; + int reg3; + + if (!get_macro_reg_vals (®1, ®2, ®3)) + return; + csky_macro_md_assemble ("cmphs", + csky_general_reg[reg1], + csky_general_reg[reg1], + NULL); + csky_macro_md_assemble ("subc", + csky_general_reg[reg1 + (target_big_endian ? 1 : 0)], + csky_general_reg[reg3 + (target_big_endian ? 1 : 0)], + NULL); + csky_macro_md_assemble ("subc", + csky_general_reg[reg1 + (target_big_endian ? 0 : 1)], + csky_general_reg[reg3 + (target_big_endian ? 0 : 1)], + NULL); + return; +} + +/* or64 rx, rx, ry -> or rx, ry, or rx+1, ry+1. */ + +static void +csky_or64 (void) +{ + int reg1; + int reg2; + int reg3; + + if (!get_macro_reg_vals (®1, ®2, ®3)) + return; + csky_macro_md_assemble ("or", + csky_general_reg[reg1 + (target_big_endian ? 1 : 0)], + csky_general_reg[reg3 + (target_big_endian ? 1 : 0)], + NULL); + csky_macro_md_assemble ("or", + csky_general_reg[reg1 + (target_big_endian ? 0 : 1)], + csky_general_reg[reg3 + (target_big_endian ? 0 : 1)], + NULL); + return; +} + +/* xor64 rx, rx, ry -> xor rx, ry, xor rx+1, ry+1. */ + +static void +csky_xor64 (void) +{ + int reg1; + int reg2; + int reg3; + + if (!get_macro_reg_vals (®1, ®2, ®3)) + return; + csky_macro_md_assemble ("xor", + csky_general_reg[reg1 + (target_big_endian ? 1 : 0)], + csky_general_reg[reg3 + (target_big_endian ? 1 : 0)], + NULL); + csky_macro_md_assemble ("xor", + csky_general_reg[reg1 + (target_big_endian ? 0 : 1)], + csky_general_reg[reg3 + (target_big_endian ? 0 : 1)], + NULL); + return; +} + +/* The following are V2 macro instructions. */ + +/* neg rd -> not rd, rd; addi rd, 1. */ + +static void +csky_neg (void) +{ + char reg1[10]; + + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, '\0'); + ++s; + + csky_macro_md_assemble ("not", reg1, reg1, NULL); + csky_macro_md_assemble ("addi", reg1, "1", NULL); + return; +} + +/* rsubi rd, imm16 -> not rd; addi rd, imm16 + 1 */ + +static void +csky_rsubi (void) +{ + char reg1[10]; + char str_imm16[20]; + unsigned int imm16 = 0; + expressionS e; + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, ','); + ++s; + + s = parse_exp (s, &e); + if (e.X_op == O_constant) + imm16 = e.X_add_number; + else + csky_show_error (ERROR_IMM_ILLEGAL, 2, NULL, NULL); + + sprintf (str_imm16, "%d", imm16 + 1); + + csky_macro_md_assemble ("not", reg1, reg1, NULL); + csky_macro_md_assemble ("addi", reg1, str_imm16, NULL); + return; +} + +/* Such as: asrc rd -> asrc rd, rd, 1. */ + +static void +csky_arith (void) +{ + char reg1[10]; + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, '\0'); + ++s; + csky_macro_md_assemble (csky_insn.macro->name, reg1, reg1, "1"); + return; +} + +/* decne rd -> if ck802: subi rd, 1; cmpnei rd, 0. + else: decne rd, rd, 1 */ + +static void +csky_decne (void) +{ + char reg1[10]; + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, '\0'); + ++s; + if (IS_CSKY_ARCH_802 (mach_flag)) + { + csky_macro_md_assemble ("subi", reg1, "1", NULL); + csky_macro_md_assemble ("cmpnei", reg1, "0", NULL); + } + else + csky_macro_md_assemble ("decne", reg1, reg1, "1"); + return; +} + +/* If -mnolrw, lrw rd, imm -> movih rd, imm_hi16; ori rd, imm_lo16. */ + +static void +csky_lrw (void) +{ + char reg1[10]; + char imm[40]; + char imm_hi16[40]; + char imm_lo16[40]; + + char *s = csky_insn.opcode_end; + s += csky_get_macro_operand (s, reg1, ','); + ++s; + s += csky_get_macro_operand (s, imm, '\0'); + ++s; + + imm_hi16[0] = '\0'; + strcat (imm_hi16, "("); + strcat (imm_hi16, imm); + strcat (imm_hi16, ") >> 16"); + imm_lo16[0] = '\0'; + strcat (imm_lo16, "("); + strcat (imm_lo16, imm); + strcat (imm_lo16, ") & 0xffff"); + + csky_macro_md_assemble ("movih", reg1, imm_hi16, NULL); + csky_macro_md_assemble ("ori", reg1, reg1, imm_lo16); + + return; +} + +/* The following are worker functions for C-SKY v1. */ + +bfd_boolean +v1_work_lrw (void) +{ + int reg; + int output_literal = csky_insn.val[1]; + + reg = csky_insn.val[0]; + csky_insn.isize = 2; + csky_insn.output = frag_more (2); + if (csky_insn.e1.X_op == O_constant + && csky_insn.e1.X_add_number <= 0x7f + && csky_insn.e1.X_add_number >= 0) + /* lrw to movi. */ + csky_insn.inst = 0x6000 | reg | (csky_insn.e1.X_add_number << 4); + else + { + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + csky_insn.inst |= reg << 8; + if (output_literal) + { + int n = enter_literal (&csky_insn.e1, 0, 0, 0); + + /* Create a reference to pool entry. */ + csky_insn.e1.X_op = O_symbol; + csky_insn.e1.X_add_symbol = poolsym; + csky_insn.e1.X_add_number = n << 2; + } + + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + { + literal_insn_offset->tls_addend.frag = frag_now; + literal_insn_offset->tls_addend.offset + = (csky_insn.output + - literal_insn_offset->tls_addend.frag->fr_literal); + } + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, 2, + &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM8BY4); + } + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +bfd_boolean +v1_work_fpu_fo (void) +{ + int i = 0; + int inst; + int greg = -1; + char buff[50]; + struct csky_opcode_info *opinfo = NULL; + + if (csky_insn.isize == 4) + opinfo = &csky_insn.opcode->op32[csky_insn.opcode_idx]; + else if (csky_insn.isize == 2) + opinfo = &csky_insn.opcode->op16[csky_insn.opcode_idx]; + + /* Firstly, get general reg. */ + for (i = 0;i < opinfo->operand_num; i++) + if (opinfo->oprnd.oprnds[i].type == OPRND_TYPE_GREG0_15) + greg = csky_insn.val[i]; + gas_assert (greg != -1); + + /* Secondly, get float inst. */ + csky_generate_insn (); + inst = csky_insn.inst; + + /* Now get greg and inst, we can write instruction to floating unit. */ + sprintf (buff, "lrw %s,0x%x", csky_general_reg[greg], inst); + md_assemble (buff); + sprintf (buff, "cpwir %s", csky_general_reg[greg]); + md_assemble (buff); + + return FALSE; +} + +bfd_boolean +v1_work_fpu_fo_fc (void) +{ + int i = 0; + int inst; + int greg = -1; + char buff[50]; + struct csky_opcode_info *opinfo = NULL; + + if (csky_insn.isize == 4) + opinfo = &csky_insn.opcode->op32[csky_insn.opcode_idx]; + else if (csky_insn.isize == 2) + opinfo = &csky_insn.opcode->op16[csky_insn.opcode_idx]; + + /* Firstly, get general reg. */ + for (i = 0;i < opinfo->operand_num; i++) + if (opinfo->oprnd.oprnds[i].type == OPRND_TYPE_GREG0_15) + greg = csky_insn.val[i]; + gas_assert (greg != -1); + + /* Secondly, get float inst. */ + csky_generate_insn (); + inst = csky_insn.inst; + + /* Now get greg and inst, we can write instruction to floating unit. */ + sprintf (buff, "lrw %s,0x%x", csky_general_reg[greg], inst); + md_assemble (buff); + sprintf (buff, "cpwir %s", csky_general_reg[greg]); + md_assemble (buff); + sprintf (buff, "cprc"); + md_assemble (buff); + + return FALSE; +} + +bfd_boolean +v1_work_fpu_write (void) +{ + int greg; + int freg; + char buff[50]; + + greg = csky_insn.val[0]; + freg = csky_insn.val[1]; + + /* Now get greg and freg, we can write instruction to floating unit. */ + sprintf (buff, "cpwgr %s,%s", csky_general_reg[greg], csky_cp_reg[freg]); + md_assemble (buff); + + return FALSE; +} + +bfd_boolean +v1_work_fpu_read (void) +{ + int greg; + int freg; + char buff[50]; + + greg = csky_insn.val[0]; + freg = csky_insn.val[1]; + /* Now get greg and freg, we can write instruction to floating unit. */ + sprintf (buff, "cprgr %s,%s", csky_general_reg[greg], csky_cp_reg[freg]); + md_assemble (buff); + + return FALSE; +} + +bfd_boolean +v1_work_fpu_writed (void) +{ + int greg; + int freg; + char buff[50]; + + greg = csky_insn.val[0]; + freg = csky_insn.val[1]; + + if (greg & 0x1) + { + as_bad (_("even register number required")); + return FALSE; + } + /* Now get greg and freg, we can write instruction to floating unit. */ + if (target_big_endian) + sprintf (buff, "cpwgr %s,%s", + csky_general_reg[greg + 1], csky_cp_reg[freg]); + else + sprintf (buff, "cpwgr %s,%s", + csky_general_reg[greg], csky_cp_reg[freg]); + md_assemble (buff); + if (target_big_endian) + sprintf (buff, "cpwgr %s,%s", + csky_general_reg[greg], csky_cp_reg[freg + 1]); + else + sprintf (buff, "cpwgr %s,%s", + csky_general_reg[greg + 1], csky_cp_reg[freg + 1]); + md_assemble (buff); + + return FALSE; +} + +bfd_boolean +v1_work_fpu_readd (void) +{ + int greg; + int freg; + char buff[50]; + + greg = csky_insn.val[0]; + freg = csky_insn.val[1]; + + if (greg & 0x1) + { + as_bad (_("even register number required")); + return FALSE; + } + /* Now get greg and freg, we can write instruction to floating unit. */ + if (target_big_endian) + sprintf (buff, "cprgr %s,%s", + csky_general_reg[greg + 1], csky_cp_reg[freg]); + else + sprintf (buff, "cprgr %s,%s", + csky_general_reg[greg], csky_cp_reg[freg]); + md_assemble (buff); + if (target_big_endian) + sprintf (buff, "cprgr %s,%s", + csky_general_reg[greg], csky_cp_reg[freg + 1]); + else + sprintf (buff, "cprgr %s,%s", + csky_general_reg[greg + 1], csky_cp_reg[freg + 1]); + md_assemble (buff); + + return FALSE; +} + +/* The following are for csky pseudo handling. */ + +bfd_boolean +v1_work_jbsr (void) +{ + csky_insn.output = frag_more (2); + if (do_force2bsr) + /* Generate fixup BFD_RELOC_CKCORE_PCREL_IMM11BY2. */ + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 2, & csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM11BY2); + else + { + /* Using jsri instruction. */ + const char *name = "jsri"; + csky_insn.opcode = (struct csky_opcode *) + hash_find (csky_opcodes_hash, name); + csky_insn.opcode_idx = 0; + csky_insn.isize = 2; + + int n = enter_literal (&csky_insn.e1, 1, 0, 0); + + /* Create a reference to pool entry. */ + csky_insn.e1.X_op = O_symbol; + csky_insn.e1.X_add_symbol = poolsym; + csky_insn.e1.X_add_number = n << 2; + + /* Generate fixup BFD_RELOC_CKCORE_PCREL_IMM8BY4. */ + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 2, & csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM8BY4); + + if (csky_insn.e1.X_op != O_absent && do_jsri2bsr) + /* Generate fixup BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2. */ + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 2, & (litpool + (csky_insn.e1.X_add_number >> 2))->e, + 1, BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2); + } + csky_generate_insn (); + + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +/* The following are worker functions for csky v2 instruction handling. */ + +/* For nie/nir/ipush/ipop. */ + +bfd_boolean +v2_work_istack (void) +{ + if (!do_intr_stack) + { + csky_show_error (ERROR_OPCODE_ILLEGAL, 0, NULL, NULL); + return FALSE; + } + csky_insn.output = frag_more (csky_insn.isize); + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_btsti (void) +{ + if (!do_extend_lrw + && (csky_insn.flag_force == INSN_OPCODE16F + || IS_CSKY_ARCH_801 (mach_flag))) + { + csky_show_error (ERROR_OPCODE_ILLEGAL, 0, NULL, NULL); + return FALSE; + } + if (!do_extend_lrw && csky_insn.isize == 2) + csky_insn.isize = 4; + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_addi (void) +{ + csky_insn.isize = 2; + if (csky_insn.number == 2) + { + if (csky_insn.val[0] == 14 + && csky_insn.val[1] >= 0 && csky_insn.val[1] <= 0x1fc + && (csky_insn.val[1] & 0x3) == 0 + && csky_insn.flag_force != INSN_OPCODE32F) + { + /* addi sp, sp, imm. */ + csky_insn.inst = 0x1400 | ((csky_insn.val[1] >> 2) & 0x1f); + csky_insn.inst |= (csky_insn.val[1] << 1) & 0x300; + csky_insn.output = frag_more (2); + } + else if (csky_insn.val[0] < 8 + && csky_insn.val[1] >= 1 && csky_insn.val[1] <= 0x100 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x2000 | (csky_insn.val[0] << 8); + csky_insn.inst |= (csky_insn.val[1] - 1); + csky_insn.output = frag_more (2); + } + else if (csky_insn.val[1] >= 1 && csky_insn.val[1] <= 0x10000 + && csky_insn.flag_force != INSN_OPCODE16F + && !IS_CSKY_ARCH_801 (mach_flag)) + { + csky_insn.inst = 0xe4000000 | (csky_insn.val[0] << 21); + csky_insn.inst |= csky_insn.val[0] << 16; + csky_insn.inst |= (csky_insn.val[1] - 1); + csky_insn.isize = 4; + csky_insn.output = frag_more (4); + } + else + { + csky_show_error (ERROR_OPERANDS_ILLEGAL, 0, + csky_insn.opcode_end, NULL); + return FALSE; + } + } + else if (csky_insn.number == 3) + { + if (csky_insn.val[0] == 14 + && csky_insn.val[1] == 14 + && csky_insn.val[2] >= 0 && csky_insn.val[2] <= 0x1fc + && (csky_insn.val[2] & 0x3) == 0 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x1400 | ((csky_insn.val[2] >> 2) & 0x1f); + csky_insn.inst |= (csky_insn.val[2] << 1) & 0x300; + csky_insn.output = frag_more (2); + } + else if (csky_insn.val[0] < 8 + && csky_insn.val[1] == 14 + && csky_insn.val[2] >= 0 && csky_insn.val[2] <= 0x3fc + && (csky_insn.val[2] & 0x3) == 0 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x1800 | (csky_insn.val[0] << 8); + csky_insn.inst |= csky_insn.val[2] >> 2; + csky_insn.output = frag_more (2); + } + else if (csky_insn.val[0] < 8 + && csky_insn.val[0] == csky_insn.val[1] + && csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x100 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x2000 | (csky_insn.val[0] << 8); + csky_insn.inst |= (csky_insn.val[2] - 1); + csky_insn.output = frag_more (2); + } + else if (csky_insn.val[0] < 8 + && csky_insn.val[1] < 8 + && csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x8 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x5802 | (csky_insn.val[0] << 5); + csky_insn.inst |= csky_insn.val[1] << 8; + csky_insn.inst |= (csky_insn.val[2] - 1) << 2; + csky_insn.output = frag_more (2); + } + else if (csky_insn.val[1] == 28 + && csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x40000 + && csky_insn.flag_force != INSN_OPCODE16F + && !IS_CSKY_ARCH_801 (mach_flag)) + { + csky_insn.inst = 0xcc1c0000 | (csky_insn.val[0] << 21); + csky_insn.isize = 4; + csky_insn.output = frag_more (4); + if (insn_reloc == BFD_RELOC_CKCORE_GOTOFF) + { + fix_new_exp (frag_now, csky_insn.output-frag_now->fr_literal, + 4, &csky_insn.e1, 0, BFD_RELOC_CKCORE_GOTOFF_IMM18); + } + else + csky_insn.inst |= (csky_insn.val[2] - 1); + } + else if (csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x1000 + && csky_insn.flag_force != INSN_OPCODE16F + && !IS_CSKY_ARCH_801 (mach_flag)) + { + csky_insn.inst = 0xe4000000 | (csky_insn.val[0] << 21); + csky_insn.inst |= csky_insn.val[1] << 16; + csky_insn.inst |= (csky_insn.val[2] - 1); + csky_insn.isize = 4; + csky_insn.output = frag_more (4); + } + else + { + csky_show_error (ERROR_OPERANDS_ILLEGAL, 0, + (char *)csky_insn.opcode_end, NULL); + return FALSE; + } + } + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +bfd_boolean +v2_work_subi (void) +{ + csky_insn.isize = 2; + if (csky_insn.number == 2) + { + if (csky_insn.val[0] == 14 + && csky_insn.val[1] >= 0 && csky_insn.val[2] <= 0x1fc + && (csky_insn.val[1] & 0x3) == 0 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x1420 | ((csky_insn.val[1] >> 2) & 0x1f); + csky_insn.inst |= (csky_insn.val[1] << 1) & 0x300; + } + else if (csky_insn.val[0] < 8 + && csky_insn.val[1] >= 1 && csky_insn.val[1] <= 0x100 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x2800 | (csky_insn.val[0] << 8); + csky_insn.inst |= (csky_insn.val[1] - 1); + } + else if (csky_insn.val[1] >= 1 && csky_insn.val[1] <= 0x10000 + && csky_insn.flag_force != INSN_OPCODE16F + && !IS_CSKY_ARCH_801 (mach_flag)) + { + csky_insn.inst = 0xe4001000 | (csky_insn.val[0] << 21); + csky_insn.inst |= csky_insn.val[0] << 16; + csky_insn.inst |= (csky_insn.val[1] - 1); + csky_insn.isize = 4; + } + else + { + csky_show_error (ERROR_OPERANDS_ILLEGAL, 0, + (char *)csky_insn.opcode_end, NULL); + return FALSE; + } + } + else if (csky_insn.number == 3) + { + if (csky_insn.val[0] == 14 + && csky_insn.val[1] == 14 + && csky_insn.val[2] >= 0 && csky_insn.val[2] <= 0x1fc + && (csky_insn.val[2] & 0x3) == 0 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x1420 | ((csky_insn.val[2] >> 2) & 0x1f); + csky_insn.inst |= (csky_insn.val[2] << 1) & 0x300; + } + + else if (csky_insn.val[0] < 8 + && csky_insn.val[0] == csky_insn.val[1] + && csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x100 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x2800 | (csky_insn.val[0] << 8); + csky_insn.inst |= (csky_insn.val[2] - 1); + } + else if (csky_insn.val[0] < 8 + && csky_insn.val[1] < 8 + && csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x8 + && csky_insn.flag_force != INSN_OPCODE32F) + { + csky_insn.inst = 0x5803 | (csky_insn.val[0] << 5); + csky_insn.inst |= csky_insn.val[1] << 8; + csky_insn.inst |= (csky_insn.val[2] - 1) << 2; + } + else if (csky_insn.val[2] >= 1 && csky_insn.val[2] <= 0x1000 + && csky_insn.flag_force != INSN_OPCODE16F + && !IS_CSKY_ARCH_801 (mach_flag)) + { + csky_insn.inst = 0xe4001000 | (csky_insn.val[0] << 21); + csky_insn.inst |= csky_insn.val[1] << 16; + csky_insn.inst |= (csky_insn.val[2] - 1); + csky_insn.isize = 4; + } + else + { + csky_show_error (ERROR_OPERANDS_ILLEGAL, 0, + (char *)csky_insn.opcode_end, NULL); + return FALSE; + } + } + csky_insn.output = frag_more (csky_insn.isize); + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +bfd_boolean +v2_work_add_sub (void) +{ + if (csky_insn.number == 3 + && (csky_insn.val[0] == csky_insn.val[1] + || csky_insn.val[0] == csky_insn.val[2]) + && csky_insn.val[0] <= 15 + && csky_insn.val[1] <= 15 + && csky_insn.val[2] <= 15) + { + if (!strstr (csky_insn.opcode->mnemonic, "sub") + || csky_insn.val[0] == csky_insn.val[1]) + { + csky_insn.opcode_idx = 0; + csky_insn.isize = 2; + if (csky_insn.val[0] == csky_insn.val[1]) + csky_insn.val[1] = csky_insn.val[2]; + + csky_insn.number = 2; + + } + } + if (csky_insn.isize == 4 + && IS_CSKY_ARCH_801 (mach_flag)) + { + if (csky_insn.number == 3) + { + if (csky_insn.val[0] > 7) + csky_show_error (ERROR_REG_OVER_RANGE, 1, + (void *)(long)csky_insn.val[0], NULL); + if (csky_insn.val[1] > 7) + csky_show_error (ERROR_REG_OVER_RANGE, 2, + (void *)(long)csky_insn.val[1], NULL); + if (csky_insn.val[2] > 7) + csky_show_error (ERROR_REG_OVER_RANGE, 3, + (void *)(long)csky_insn.val[2], NULL); + } + else + { + if (csky_insn.val[0] > 15) + csky_show_error (ERROR_REG_OVER_RANGE, 1, + (void *)(long)csky_insn.val[0], NULL); + if (csky_insn.val[1] > 15) + csky_show_error (ERROR_REG_OVER_RANGE, 2, + (void *)(long)csky_insn.val[1], NULL); + } + return FALSE; + } + /* sub rz, rx. */ + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_rotlc (void) +{ + const char *name = "addc"; + csky_insn.opcode + = (struct csky_opcode *) hash_find (csky_opcodes_hash, name); + csky_insn.opcode_idx = 0; + if (csky_insn.isize == 2) + { + /* addc rz, rx. */ + csky_insn.number = 2; + csky_insn.val[1] = csky_insn.val[0]; + } + else + { + csky_insn.number = 3; + /* addc rz, rx, ry. */ + csky_insn.val[1] = csky_insn.val[0]; + csky_insn.val[2] = csky_insn.val[0]; + } + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_bgeni (void) +{ + const char *name = NULL; + int imm = csky_insn.val[1]; + int val = 1 << imm; + if (imm < 16) + name = "movi"; + else + { + name = "movih"; + val >>= 16; + } + csky_insn.opcode + = (struct csky_opcode *) hash_find (csky_opcodes_hash, name); + csky_insn.opcode_idx = 0; + csky_insn.val[1] = val; + + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_not (void) +{ + const char *name = "nor"; + csky_insn.opcode + = (struct csky_opcode *) hash_find (csky_opcodes_hash, name); + csky_insn.opcode_idx = 0; + if (csky_insn.number == 1) + { + csky_insn.val[1] = csky_insn.val[0]; + if (csky_insn.val[0] < 16) + { + /* 16 bits nor rz, rz. */ + csky_insn.number = 2; + csky_insn.isize = 2; + } + else + { + csky_insn.val[2] = csky_insn.val[0]; + csky_insn.number = 3; + csky_insn.isize = 4; + } + } + if (csky_insn.number == 2) + { + if (csky_insn.val[0] == csky_insn.val[1] + && csky_insn.val[0] < 16) + { + /* 16 bits nor rz, rz. */ + csky_insn.number = 2; + csky_insn.isize = 2; + } + else + { + csky_insn.val[2] = csky_insn.val[1]; + csky_insn.number = 3; + csky_insn.isize = 4; + } + } + + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_jbtf (void) +{ + if (csky_insn.e1.X_add_symbol == NULL || csky_insn.e1.X_op == O_constant) + { + csky_show_error (ERROR_UNDEFINE, 0, (void *)"operand is invalid", NULL); + return FALSE; + } + + if (IS_CSKY_ARCH_801 (mach_flag)) + { + /* CK801 doesn't have 32-bit bt/bf insns or a jump insn with a + range larger than SCOND_DISP16. Relax to a short jump around + an unconditional branch, and give up if that overflows too. */ + csky_insn.output = frag_var (rs_machine_dependent, + SCOND_DISP16_LEN, + SCOND_DISP10_LEN, + SCOND_DISP10, + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, + 0); + csky_insn.isize = 2; + csky_insn.max = SCOND_DISP16_LEN; + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + } + else if (do_long_jump && !IS_CSKY_ARCH_802 (mach_flag)) + { + /* Generate relax with jcondition. + Note that CK802 doesn't support the JMPI instruction so + we cannot relax to a jump with a 32-bit offset. */ + csky_insn.output = frag_var (rs_machine_dependent, + JCOND_DISP32_LEN, + JCOND_DISP10_LEN, + JCOND_DISP10, + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, + 0); + csky_insn.isize = 2; + csky_insn.max = JCOND_DISP32_LEN; + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + } + else + { + /* Generate relax with condition. */ + csky_insn.output = frag_var (rs_machine_dependent, + COND_DISP16_LEN, + COND_DISP10_LEN, + COND_DISP10, + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, + 0); + csky_insn.isize = 2; + csky_insn.max = COND_DISP16_LEN; + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + } + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +bfd_boolean +v2_work_jbr (void) +{ + if (csky_insn.e1.X_add_symbol == NULL || csky_insn.e1.X_op == O_constant) + { + csky_show_error (ERROR_UNDEFINE, 0, (void *)"operand is invalid", NULL); + return FALSE; + } + + if (do_long_jump + && !IS_CSKY_ARCH_801 (mach_flag) + && !IS_CSKY_ARCH_802 (mach_flag)) + { + csky_insn.output = frag_var (rs_machine_dependent, + JUNCD_DISP32_LEN, + JUNCD_DISP10_LEN, + JUNCD_DISP10, + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, + 0); + + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + csky_insn.max = JUNCD_DISP32_LEN; + csky_insn.isize = 2; + } + else + { + /* Generate relax with condition. */ + csky_insn.output = frag_var (rs_machine_dependent, + UNCD_DISP16_LEN, + UNCD_DISP10_LEN, + UNCD_DISP10, + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, + 0); + csky_insn.isize = 2; + csky_insn.max = UNCD_DISP16_LEN; + csky_insn.inst = csky_insn.opcode->op16[0].opcode; + + } + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +#define SIZE_V2_MOVI16(x) ((addressT)x <= 0xff) +#define SIZE_V2_MOVI32(x) ((addressT)x <= 0xffff) +#define SIZE_V2_MOVIH(x) ((addressT)x <= 0xffffffff && (((addressT)x & 0xffff) == 0)) + +bfd_boolean +v2_work_lrw (void) +{ + int reg = csky_insn.val[0]; + int output_literal = csky_insn.val[1]; + int is_done = 0; + + /* If the second operand is O_constant, We can use movi/movih + instead of lrw. */ + if (csky_insn.e1.X_op == O_constant) + { + /* 801 only has movi16. */ + if (SIZE_V2_MOVI16 (csky_insn.e1.X_add_number) && reg < 8) + { + /* movi16 instead. */ + csky_insn.output = frag_more (2); + csky_insn.inst = (CSKYV2_INST_MOVI16 | (reg << 8) + | (csky_insn.e1.X_add_number)); + csky_insn.isize = 2; + is_done = 1; + } + else if (SIZE_V2_MOVI32 (csky_insn.e1.X_add_number) + && !IS_CSKY_ARCH_801 (mach_flag)) + { + /* movi32 instead. */ + csky_insn.output = frag_more (4); + csky_insn.inst = (CSKYV2_INST_MOVI32 | (reg << 16) + | (csky_insn.e1.X_add_number)); + csky_insn.isize = 4; + is_done = 1; + } + else if (SIZE_V2_MOVIH (csky_insn.e1.X_add_number) + && !IS_CSKY_ARCH_801 (mach_flag)) + { + /* movih instead. */ + csky_insn.output = frag_more (4); + csky_insn.inst = (CSKYV2_INST_MOVIH | (reg << 16) + | ((csky_insn.e1.X_add_number >> 16) & 0xffff)); + csky_insn.isize = 4; + is_done = 1; + } + } + + if (is_done) + { + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; + } + + if (output_literal) + { + int n = enter_literal (&csky_insn.e1, 0, 0, 0); + /* Create a reference to pool entry. */ + csky_insn.e1.X_op = O_symbol; + csky_insn.e1.X_add_symbol = poolsym; + csky_insn.e1.X_add_number = n << 2; + } + /* If 16bit force. */ + if (csky_insn.flag_force == INSN_OPCODE16F) + { + /* Generate fixup. */ + if (reg > 7) + { + csky_show_error (ERROR_UNDEFINE, 0, + (void *)"The register is out of range.", NULL); + return FALSE; + } + csky_insn.isize = 2; + csky_insn.output = frag_more (2); + + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + { + literal_insn_offset->tls_addend.frag = frag_now; + literal_insn_offset->tls_addend.offset + = csky_insn.output - frag_now->fr_literal; + } + csky_insn.inst = csky_insn.opcode->op16[0].opcode | (reg << 5); + csky_insn.max = 4; + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 2, &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM7BY4); + } + else if (csky_insn.flag_force == INSN_OPCODE32F) + { + csky_insn.isize = 4; + csky_insn.output = frag_more (4); + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + { + literal_insn_offset->tls_addend.frag = frag_now; + literal_insn_offset->tls_addend.offset + = csky_insn.output - frag_now->fr_literal; + } + csky_insn.inst = csky_insn.opcode->op32[0].opcode | (reg << 16); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM16BY4); + } + else if (!is_done) + { + if (reg < 8) + { + csky_insn.isize = 2; + + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + literal_insn_offset->tls_addend.frag = frag_now; + + csky_insn.output = frag_var (rs_machine_dependent, + LRW_DISP16_LEN, + LRW_DISP7_LEN, + (do_extend_lrw + ? LRW2_DISP8 : LRW_DISP7), + csky_insn.e1.X_add_symbol, + csky_insn.e1.X_add_number, 0); + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + { + if (literal_insn_offset->tls_addend.frag->fr_next != frag_now) + literal_insn_offset->tls_addend.frag + = literal_insn_offset->tls_addend.frag->fr_next; + literal_insn_offset->tls_addend.offset + = (csky_insn.output + - literal_insn_offset->tls_addend.frag->fr_literal); + } + csky_insn.inst = csky_insn.opcode->op16[0].opcode | (reg << 5); + csky_insn.max = LRW_DISP16_LEN; + csky_insn.isize = 2; + } + else + { + csky_insn.isize = 4; + csky_insn.output = frag_more (4); + if (insn_reloc == BFD_RELOC_CKCORE_TLS_GD32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_LDM32 + || insn_reloc == BFD_RELOC_CKCORE_TLS_IE32) + { + literal_insn_offset->tls_addend.frag = frag_now; + literal_insn_offset->tls_addend.offset + = csky_insn.output - frag_now->fr_literal; + } + csky_insn.inst = csky_insn.opcode->op32[0].opcode | (reg << 16); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM16BY4); + } + } + + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_lrsrsw (void) +{ + int reg = csky_insn.val[0]; + csky_insn.output = frag_more (4); + csky_insn.inst = csky_insn.opcode->op32[0].opcode | (reg << 21); + csky_insn.isize = 4; + + switch (insn_reloc) + { + case BFD_RELOC_CKCORE_GOT32: + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 0, BFD_RELOC_CKCORE_GOT_IMM18BY4); + break; + case BFD_RELOC_CKCORE_PLT32: + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 0, BFD_RELOC_CKCORE_PLT_IMM18BY4); + break; + default: + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 1, BFD_RELOC_CKCORE_DOFFSET_IMM18BY4); + break; + } + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +v2_work_jbsr (void) +{ + if (do_force2bsr + || IS_CSKY_ARCH_801 (mach_flag) + || IS_CSKY_ARCH_802 (mach_flag)) + { + csky_insn.output = frag_more (4); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM26BY2); + csky_insn.isize = 4; + csky_insn.inst = CSKYV2_INST_BSR32; + } + else + { + int n = enter_literal (&csky_insn.e1, 0, 0, 0); + csky_insn.output = frag_more (4); + csky_insn.e1.X_op = O_symbol; + csky_insn.e1.X_add_symbol = poolsym; + csky_insn.e1.X_add_number = n << 2; + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 1, BFD_RELOC_CKCORE_PCREL_IMM16BY4); + if (do_jsri2bsr || IS_CSKY_ARCH_810 (mach_flag)) + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, + &(litpool + (csky_insn.e1.X_add_number >> 2))->e, + 1, + BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2); + csky_insn.inst = CSKYV2_INST_JSRI32; + csky_insn.isize = 4; + if (IS_CSKY_ARCH_810 (mach_flag)) + { + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + csky_insn.output = frag_more (4); + dwarf2_emit_insn (0); + /* Insert "mov r0, r0". */ + csky_insn.inst = CSKYV2_INST_MOV_R0_R0; + csky_insn.max = 8; + } + } + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +bfd_boolean +v2_work_jsri (void) +{ + /* dump literal. */ + int n = enter_literal (&csky_insn.e1, 1, 0, 0); + csky_insn.e1.X_op = O_symbol; + csky_insn.e1.X_add_symbol = poolsym; + csky_insn.e1.X_add_number = n << 2; + + /* Generate relax or reloc if necessary. */ + csky_generate_frags (); + /* Generate the insn by mask. */ + csky_generate_insn (); + /* Write inst to frag. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + /* Control 810 not to generate jsri. */ + if (IS_CSKY_ARCH_810 (mach_flag)) + { + /* Look at adding the R_PCREL_JSRIMM26BY2. + For 'jbsr .L1', this reloc type's symbol + is bound to '.L1', isn't bound to literal pool. */ + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &(litpool + (csky_insn.e1.X_add_number >> 2))->e, 1, + BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2); + csky_insn.output = frag_more (4); + dwarf2_emit_insn (0); + /* The opcode of "mov32 r0,r0". */ + csky_insn.inst = CSKYV2_INST_MOV_R0_R0; + /* The effect of this value is to check literal. */ + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + csky_insn.max = 8; + } + return TRUE; +} + +bfd_boolean +v2_work_movih (void) +{ + int rz = csky_insn.val[0]; + csky_insn.output = frag_more (4); + csky_insn.inst = csky_insn.opcode->op32[0].opcode | (rz << 16); + if (csky_insn.e1.X_op == O_constant) + { + if (csky_insn.e1.X_unsigned == 1 && csky_insn.e1.X_add_number > 0xffff) + { + csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL); + return FALSE; + } + else if (csky_insn.e1.X_unsigned == 0 && csky_insn.e1.X_add_number < 0) + { + csky_show_error (ERROR_IMM_OVERFLOW, 2, NULL, NULL); + return FALSE; + } + else + csky_insn.inst |= (csky_insn.e1.X_add_number & 0xffff); + } + else if (csky_insn.e1.X_op == O_right_shift + || (csky_insn.e1.X_op == O_symbol && insn_reloc != BFD_RELOC_NONE)) + { + if (csky_insn.e1.X_op_symbol != 0 + && csky_insn.e1.X_op_symbol->sy_value.X_op == O_constant + && 16 == csky_insn.e1.X_op_symbol->sy_value.X_add_number) + { + csky_insn.e1.X_op = O_symbol; + if (insn_reloc == BFD_RELOC_CKCORE_GOT32) + insn_reloc = BFD_RELOC_CKCORE_GOT_HI16; + else if (insn_reloc == BFD_RELOC_CKCORE_PLT32) + insn_reloc = BFD_RELOC_CKCORE_PLT_HI16; + else if (insn_reloc == BFD_RELOC_CKCORE_GOTPC) + insn_reloc = BFD_RELOC_CKCORE_GOTPC_HI16; + else if (insn_reloc == BFD_RELOC_CKCORE_GOTOFF) + insn_reloc = BFD_RELOC_CKCORE_GOTOFF_HI16; + else + insn_reloc = BFD_RELOC_CKCORE_ADDR_HI16; + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 0, insn_reloc); + } + else + { + void *arg = (void *)"the second operand must be \"SYMBOL >> 16\""; + csky_show_error (ERROR_UNDEFINE, 0, arg, NULL); + return FALSE; + } + } + csky_insn.isize = 4; + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + + return TRUE; +} + +bfd_boolean +v2_work_ori (void) +{ + int rz = csky_insn.val[0]; + int rx = csky_insn.val[1]; + csky_insn.output = frag_more (4); + csky_insn.inst = csky_insn.opcode->op32[0].opcode | (rz << 21) | (rx << 16); + if (csky_insn.e1.X_op == O_constant) + { + if (csky_insn.e1.X_add_number <= 0xffff + && csky_insn.e1.X_add_number >= 0) + csky_insn.inst |= csky_insn.e1.X_add_number; + else + { + csky_show_error (ERROR_IMM_OVERFLOW, 3, NULL, NULL); + return FALSE; + } + } + else if (csky_insn.e1.X_op == O_bit_and) + { + if (csky_insn.e1.X_op_symbol->sy_value.X_op == O_constant + && 0xffff == csky_insn.e1.X_op_symbol->sy_value.X_add_number) + { + csky_insn.e1.X_op = O_symbol; + if (insn_reloc == BFD_RELOC_CKCORE_GOT32) + insn_reloc = BFD_RELOC_CKCORE_GOT_LO16; + else if (insn_reloc == BFD_RELOC_CKCORE_PLT32) + insn_reloc = BFD_RELOC_CKCORE_PLT_LO16; + else if (insn_reloc == BFD_RELOC_CKCORE_GOTPC) + insn_reloc = BFD_RELOC_CKCORE_GOTPC_LO16; + else if (insn_reloc == BFD_RELOC_CKCORE_GOTOFF) + insn_reloc = BFD_RELOC_CKCORE_GOTOFF_LO16; + else + insn_reloc = BFD_RELOC_CKCORE_ADDR_LO16; + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 0, insn_reloc); + } + else + { + void *arg = (void *)"the third operand must be \"SYMBOL & 0xffff\""; + csky_show_error (ERROR_UNDEFINE, 0, arg, NULL); + return FALSE; + } + } + csky_insn.isize = 4; + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +/* Helper function to encode a single/double floating point constant + into the instruction word for fmovis and fmovid instructions. + The constant is in its IEEE single/double precision representation + and is repacked into the internal 13-bit representation for these + instructions with a diagnostic for overflow. Note that there is no + rounding when converting to the smaller format, just an error if there + is excess precision or the number is too small/large to be represented. */ + +bfd_boolean +float_work_fmovi (void) +{ + int rx = csky_insn.val[0]; + + /* We already converted the float constant to the internal 13-bit + representation so we just need to OR it in here. */ + csky_insn.inst = csky_insn.opcode->op32[0].opcode | rx; + csky_insn.inst |= (uint32_t) csky_insn.e1.X_add_number; + + csky_insn.output = frag_more (4); + csky_insn.isize = 4; + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + +bfd_boolean +dsp_work_bloop (void) +{ + int reg = csky_insn.val[0]; + csky_insn.output = frag_more (4); + csky_insn.inst = csky_insn.opcode->op32[0].opcode | (reg << 16); + csky_insn.isize = 4; + + if (csky_insn.e1.X_op == O_symbol + && csky_insn.e2.X_op == O_symbol) + { + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e1, 1, + BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4); + fix_new_exp (frag_now, csky_insn.output - frag_now->fr_literal, + 4, &csky_insn.e2, 1, + BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4); + } + + csky_write_insn (csky_insn.output, csky_insn.inst, csky_insn.isize); + return TRUE; +} + + +/* The following are for assembler directive handling. */ + +/* Helper function to adjust constant pool counts when we emit a + data directive in the text section. FUNC is one of the standard + gas functions to handle these directives, like "stringer" for the + .string directive, and ARG is the argument to FUNC. csky_pool_count + essentially wraps the call with the constant pool magic. */ + +static void +csky_pool_count (void (*func) (int), int arg) +{ + const fragS *curr_frag = frag_now; + offsetT added = -frag_now_fix_octets (); + + (*func) (arg); + + while (curr_frag != frag_now) + { + added += curr_frag->fr_fix; + curr_frag = curr_frag->fr_next; + } + + added += frag_now_fix_octets (); + poolspan += added; +} + +/* Support the .literals directive. */ +static void +csky_s_literals (int ignore ATTRIBUTE_UNUSED) +{ + dump_literals (0); + demand_empty_rest_of_line (); +} + +/* Support the .string, etc directives. */ +static void +csky_stringer (int append_zero) +{ + if (now_seg == text_section) + csky_pool_count (stringer, append_zero); + else + stringer (append_zero); + + /* We call check_literals here in case a large number of strings are + being placed into the text section with a sequence of stringer + directives. In theory we could be upsetting something if these + strings are actually in an indexed table instead of referenced by + individual labels. Let us hope that that never happens. */ + check_literals (2, 0); +} + +/* Support integer-mode constructors like .word, .byte, etc. */ + +static void +csky_cons (int nbytes) +{ + mapping_state (MAP_DATA); + if (nbytes == 4) /* @GOT. */ + { + do + { + bfd_reloc_code_real_type reloc; + expressionS exp; + + reloc = BFD_RELOC_NONE; + expression (&exp); + lex_got (&reloc, NULL); + + if (exp.X_op == O_symbol && reloc != BFD_RELOC_NONE) + { + reloc_howto_type *howto + = bfd_reloc_type_lookup (stdoutput, reloc); + int size = bfd_get_reloc_size (howto); + + if (size > nbytes) + as_bad (ngettext ("%s relocations do not fit in %d byte", + "%s relocations do not fit in %d bytes", + nbytes), + howto->name, nbytes); + else + { + register char *p = frag_more ((int) nbytes); + int offset = nbytes - size; + + fix_new_exp (frag_now, + p - frag_now->fr_literal + offset, + size, &exp, 0, reloc); + } + } + else + emit_expr (&exp, (unsigned int) nbytes); + if (now_seg == text_section) + poolspan += nbytes; + } + while (*input_line_pointer++ == ','); + + /* Put terminator back into stream. */ + input_line_pointer --; + demand_empty_rest_of_line (); + + return; + } + + if (now_seg == text_section) + csky_pool_count (cons, nbytes); + else + cons (nbytes); + + /* In theory we ought to call check_literals (2,0) here in case + we need to dump the literal table. We cannot do this however, + as the directives that we are intercepting may be being used + to build a switch table, and we must not interfere with its + contents. Instead we cross our fingers and pray... */ +} + +/* Support floating-mode constant directives like .float and .double. */ + +static void +csky_float_cons (int float_type) +{ + mapping_state (MAP_DATA); + if (now_seg == text_section) + csky_pool_count (float_cons, float_type); + else + float_cons (float_type); + + /* See the comment in csky_cons () about calling check_literals. + It is unlikely that a switch table will be constructed using + floating point values, but it is still likely that an indexed + table of floating point constants is being created by these + directives, so again we must not interfere with their placement. */ +} + +/* Support the .fill directive. */ + +static void +csky_fill (int ignore) +{ + if (now_seg == text_section) + csky_pool_count (s_fill, ignore); + else + s_fill (ignore); + + check_literals (2, 0); +} + +/* Handle the section changing pseudo-ops. These call through to the + normal implementations, but they dump the literal pool first. */ + +static void +csky_s_text (int ignore) +{ + dump_literals (0); + +#ifdef OBJ_ELF + obj_elf_text (ignore); +#else + s_text (ignore); +#endif +} + +static void +csky_s_data (int ignore) +{ + dump_literals (0); + +#ifdef OBJ_ELF + obj_elf_data (ignore); +#else + s_data (ignore); +#endif +} + +static void +csky_s_section (int ignore) +{ + /* Scan forwards to find the name of the section. If the section + being switched to is ".line" then this is a DWARF1 debug section + which is arbitrarily placed inside generated code. In this case + do not dump the literal pool because it is a) inefficient and + b) would require the generation of extra code to jump around the + pool. */ + char * ilp = input_line_pointer; + + while (*ilp != 0 && ISSPACE (*ilp)) + ++ ilp; + + if (strncmp (ilp, ".line", 5) == 0 + && (ISSPACE (ilp[5]) || *ilp == '\n' || *ilp == '\r')) + ; + else + dump_literals (0); + +#ifdef OBJ_ELF + obj_elf_section (ignore); +#endif +#ifdef OBJ_COFF + obj_coff_section (ignore); +#endif +} + +static void +csky_s_bss (int needs_align) +{ + dump_literals (0); + s_lcomm_bytes (needs_align); +} + +#ifdef OBJ_ELF +static void +csky_s_comm (int needs_align) +{ + dump_literals (0); + obj_elf_common (needs_align); +} +#endif + +/* Handle the .no_literal_dump directive. */ + +static void +csky_noliteraldump (int ignore ATTRIBUTE_UNUSED) +{ + do_noliteraldump = 1; + int insn_num = get_absolute_expression (); + /* The insn after '.no_literal_dump insn_num' is insn1, + Don't dump literal pool between insn1 and insn(insn_num+1) + The insn cannot be the insn generate literal, like lrw & jsri. */ + check_literals (0, insn_num * 2); +} + +/* Handle the .align directive. + We must check literals before doing alignment. For example, if + '.align n', add (2^n-1) to poolspan and check literals. */ + +static void +csky_s_align_ptwo (int arg) +{ + /* Get the .align's first absolute number. */ + char * temp_pointer = input_line_pointer; + int align = get_absolute_expression (); + check_literals (0, (1 << align) - 1); + input_line_pointer = temp_pointer; + + /* Do alignment. */ + s_align_ptwo (arg); +} + +/* Handle the .stack_size directive. */ + +static void +csky_stack_size (int arg ATTRIBUTE_UNUSED) +{ + expressionS exp; + stack_size_entry *sse + = (stack_size_entry *) xcalloc (1, sizeof (stack_size_entry)); + + expression (&exp); + if (exp.X_op == O_symbol) + sse->function = exp.X_add_symbol; + else + { + as_bad (_("the first operand must be a symbol")); + ignore_rest_of_line (); + free (sse); + return; + } + + SKIP_WHITESPACE (); + if (*input_line_pointer != ',') + { + as_bad (_("missing stack size")); + ignore_rest_of_line (); + free (sse); + return; + } + + ++input_line_pointer; + expression (&exp); + if (exp.X_op == O_constant) + { + if (exp.X_add_number < 0 || exp.X_add_number > (offsetT)0xffffffff) + { + + as_bad (_("value not in range [0, 0xffffffff]")); + ignore_rest_of_line (); + free (sse); + return; + } + else + sse->stack_size = exp.X_add_number; + } + else + { + as_bad (_("operand must be a constant")); + ignore_rest_of_line (); + free (sse); + return; + } + + if (*last_stack_size_data != NULL) + last_stack_size_data = &((*last_stack_size_data)->next); + + *last_stack_size_data = sse; +} + +/* This table describes all the machine specific pseudo-ops the assembler + has to support. The fields are: + pseudo-op name without dot + function to call to execute this pseudo-op + Integer arg to pass to the function. */ + +const pseudo_typeS md_pseudo_table[] = +{ + { "export", s_globl, 0 }, + { "import", s_ignore, 0 }, + { "literals", csky_s_literals, 0 }, + { "page", listing_eject, 0 }, + + /* The following are to intercept the placement of data into the text + section (eg addresses for a switch table), so that the space they + occupy can be taken into account when deciding whether or not to + dump the current literal pool. + XXX - currently we do not cope with the .space and .dcb.d directives. */ + { "ascii", csky_stringer, 8 + 0 }, + { "asciz", csky_stringer, 8 + 1 }, + { "byte", csky_cons, 1 }, + { "dc", csky_cons, 2 }, + { "dc.b", csky_cons, 1 }, + { "dc.d", csky_float_cons, 'd'}, + { "dc.l", csky_cons, 4 }, + { "dc.s", csky_float_cons, 'f'}, + { "dc.w", csky_cons, 2 }, + { "dc.x", csky_float_cons, 'x'}, + { "double", csky_float_cons, 'd'}, + { "float", csky_float_cons, 'f'}, + { "hword", csky_cons, 2 }, + { "int", csky_cons, 4 }, + { "long", csky_cons, 4 }, + { "octa", csky_cons, 16 }, + { "quad", csky_cons, 8 }, + { "short", csky_cons, 2 }, + { "single", csky_float_cons, 'f'}, + { "string", csky_stringer, 8 + 1 }, + { "word", csky_cons, 4 }, + { "fill", csky_fill, 0 }, + + /* Allow for the effect of section changes. */ + { "text", csky_s_text, 0 }, + { "data", csky_s_data, 0 }, + { "bss", csky_s_bss, 1 }, +#ifdef OBJ_ELF + { "comm", csky_s_comm, 0 }, +#endif + { "section", csky_s_section, 0 }, + { "section.s", csky_s_section, 0 }, + { "sect", csky_s_section, 0 }, + { "sect.s", csky_s_section, 0 }, + /* When ".no_literal_dump N" is in front of insn1, + and instruction sequence is: + insn1 + insn2 + ...... + insnN+1 + it means literals will not dump between insn1 and insnN+1 + The insn cannot itself generate literal, like lrw & jsri. */ + { "no_literal_dump", csky_noliteraldump, 0 }, + { "align", csky_s_align_ptwo, 0 }, + { "stack_size", csky_stack_size, 0 }, + {0, 0, 0} +}; + +/* Implement tc_cfi_frame_initial_instructions. */ + +void +csky_cfi_frame_initial_instructions (void) +{ + int sp_reg = IS_CSKY_V1 (mach_flag) ? 0 : 14; + cfi_add_CFA_def_cfa_register (sp_reg); +} + +/* Implement tc_regname_to_dw2regnum. */ + +int +tc_csky_regname_to_dw2regnum (char *regname) +{ + int reg_num = -1; + int len; + + /* FIXME the reg should be parsed according to + the abi version. */ + reg_num = csky_get_reg_val (regname, &len); + return reg_num; +} diff --git a/gas/config/tc-csky.h b/gas/config/tc-csky.h new file mode 100644 index 0000000..4ea0c03 --- /dev/null +++ b/gas/config/tc-csky.h @@ -0,0 +1,107 @@ +/* tc-csky.h -- Header file for tc-csky.c + Copyright (C) 1989-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef TC_CSKY +#define TC_CSKY 1 + +#define WORKING_DOT_WORD + +#define TARGET_ARCH bfd_arch_csky + +#define LISTING_HEADER "CSKY GAS" + +#ifdef OBJ_ELF +#define TARGET_FORMAT elf32_csky_target_format () +#endif + +#define TARGET_BYTES_BIG_ENDIAN 0 + +#define MD_PCREL_FROM_SECTION(F,S) md_pcrel_from_section (F, S) + +#define TC_GENERIC_RELAX_TABLE csky_relax_table + +#define md_end md_csky_end +#define md_relax_frag csky_relax_frag +#define DOUBLESLASH_LINE_COMMENTS +#define LOCAL_LABELS_FB 1 +#define PAD_LITERAL_LENGTH 6 +#define PAD_FILL_CONTENT 0x1c00 + +/* Reloc API. */ +#define EXTERN_FORCE_RELOC 1 +#define TC_CONS_FIX_NEW csky_cons_fix_new +#define TC_FORCE_RELOCATION(fix) csky_force_relocation (fix) +#define tc_fix_adjustable(FIX) csky_fix_adjustable (FIX) +#define TC_SEGMENT_INFO_TYPE csky_segment_info_type + +/* Dwarf API. */ +#define DWARF2_LINE_MIN_INSN_LENGTH 2 +#define DWARF2_ADDR_SIZE(bfd) 4 +#define DWARF2_FDE_RELOC_SIZE 4 +#define TARGET_USE_CFIPOP 1 +#define tc_cfi_frame_initial_instructions csky_cfi_frame_initial_instructions +#define tc_regname_to_dw2regnum tc_csky_regname_to_dw2regnum +#define DWARF2_DEFAULT_RETURN_COLUMN 15 +#define DWARF2_CIE_DATA_ALIGNMENT (-4) + +typedef enum +{ + MAP_UNDEFINED = 0, + MAP_DATA, + MAP_TEXT, +} map_state; + +typedef struct +{ + map_state current_state; +} csky_segment_info_type; + +struct tls_addend +{ + fragS *frag; + offsetT offset; +}; + +#define TC_FIX_TYPE struct tls_addend +#define TC_INIT_FIX_DATA(FIX) \ + { (FIX)->tc_fix_data.frag = NULL; (FIX)->tc_fix_data.offset = 0; } + +#include "write.h" +extern const relax_typeS csky_relax_table []; + +extern void md_csky_end (void); +extern long md_pcrel_from_section (fixS *, segT); +extern void csky_cons_fix_new (fragS *, + unsigned int off, + unsigned int len, + expressionS *, + bfd_reloc_code_real_type); +extern int csky_force_relocation (fixS *); +extern bfd_boolean csky_fix_adjustable (fixS *); +extern void csky_cfi_frame_initial_instructions (void); +extern int tc_csky_regname_to_dw2regnum (char *); +extern long csky_relax_frag (segT, fragS *, long); + +#ifdef OBJ_ELF +const char * elf32_csky_target_format (void); +#endif + +#endif diff --git a/gas/config/te-csky_abiv1.h b/gas/config/te-csky_abiv1.h new file mode 100644 index 0000000..5185abc --- /dev/null +++ b/gas/config/te-csky_abiv1.h @@ -0,0 +1,24 @@ +/* Environment definitions for C-SKY ABIV2 bare-metal targets. + Copyright (C) 2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GAS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "obj-format.h" + +#define _CSKY_ABI 1 diff --git a/gas/config/te-csky_abiv1_linux.h b/gas/config/te-csky_abiv1_linux.h new file mode 100644 index 0000000..1999bf7 --- /dev/null +++ b/gas/config/te-csky_abiv1_linux.h @@ -0,0 +1,24 @@ +/* Environment definitions for C-SKY ABIV1 Linux targets. + Copyright (C) 2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GAS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "obj-format.h" + +#define _CSKY_ABI 1 diff --git a/gas/config/te-csky_abiv2.h b/gas/config/te-csky_abiv2.h new file mode 100644 index 0000000..c0b649d --- /dev/null +++ b/gas/config/te-csky_abiv2.h @@ -0,0 +1,26 @@ +/* Environment definitions for C-SKY ABIV2 bare-metal targets. + Copyright (C) 2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GAS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#define INCLUDE_BRANCH_STUB + +#include "obj-format.h" + +#define _CSKY_ABI 2 diff --git a/gas/config/te-csky_abiv2_linux.h b/gas/config/te-csky_abiv2_linux.h new file mode 100644 index 0000000..06854f3 --- /dev/null +++ b/gas/config/te-csky_abiv2_linux.h @@ -0,0 +1,24 @@ +/* Environment definitions for C-SKY ABIV2 Linux targets. + Copyright (C) 2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, + or (at your option) any later version. + + GAS is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "obj-format.h" + +#define _CSKY_ABI 2 diff --git a/gas/configure.tgt b/gas/configure.tgt index 6df7dea..d1b0535 100644 --- a/gas/configure.tgt +++ b/gas/configure.tgt @@ -173,6 +173,11 @@ case ${generic_target} in crx-*-elf*) fmt=elf ;; + csky-*-elf*abiv1) fmt=elf em=csky_abiv1 ;; + csky-*-elf*) fmt=elf em=csky_abiv2 ;; + csky-*-linux*abiv1) fmt=elf em=csky_abiv1_linux ;; + csky-*-linux*) fmt=elf em=csky_abiv2_linux ;; + d10v-*-*) fmt=elf ;; d30v-*-*) fmt=elf ;; dlx-*-*) fmt=elf ;; @@ -431,7 +436,7 @@ case ${generic_target} in esac case ${cpu_type} in - aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | riscv | sparc | z80 | z8k) + aarch64 | alpha | arm | csky | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | riscv | sparc | z80 | z8k) bfd_gas=yes ;; esac diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am index b3d4fa7..210f2e4 100644 --- a/gas/doc/Makefile.am +++ b/gas/doc/Makefile.am @@ -54,6 +54,7 @@ CPU_DOCS = \ c-bfin.texi \ c-cr16.texi \ c-cris.texi \ + c-csky.texi \ c-d10v.texi \ c-epiphany.texi \ c-h8300.texi \ diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in index b745b7e..765e6b0 100644 --- a/gas/doc/Makefile.in +++ b/gas/doc/Makefile.in @@ -409,6 +409,7 @@ CPU_DOCS = \ c-bfin.texi \ c-cr16.texi \ c-cris.texi \ + c-csky.texi \ c-d10v.texi \ c-epiphany.texi \ c-h8300.texi \ diff --git a/gas/doc/all.texi b/gas/doc/all.texi index 2b8af69..ef103de 100644 --- a/gas/doc/all.texi +++ b/gas/doc/all.texi @@ -32,6 +32,7 @@ @set Blackfin @set CR16 @set CRIS +@set CSKY @set D10V @set D30V @set EPIPHANY diff --git a/gas/doc/as.texi b/gas/doc/as.texi index aea5e71..be84bf2 100644 --- a/gas/doc/as.texi +++ b/gas/doc/as.texi @@ -306,6 +306,26 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @c Deprecated -- deliberately not documented. @c [@b{-h}] [@b{-H}] @end ifset +@ifset CSKY + +@emph{Target C-SKY options:} + [@b{-march=@var{arch}}] [@b{-mcpu=@var{cpu}}] + [@b{-EL}] [@b{-mlittle-endian}] [@b{-EB}] [@b{-mbig-endian}] + [@b{-fpic}] [@b{-pic}] + [@b{-mljump}] [@b{-mno-ljump}] + [@b{-force2bsr}] [@b{-mforce2bsr}] [@b{-no-force2bsr}] [@b{-mno-force2bsr}] + [@b{-jsri2bsr}] [@b{-mjsri2bsr}] [@b{-no-jsri2bsr }] [@b{-mno-jsri2bsr}] + [@b{-mnolrw }] [@b{-mno-lrw}] + [@b{-melrw}] [@b{-mno-elrw}] + [@b{-mlaf }] [@b{-mliterals-after-func}] + [@b{-mno-laf}] [@b{-mno-literals-after-func}] + [@b{-mlabr}] [@b{-mliterals-after-br}] + [@b{-mno-labr}] [@b{-mnoliterals-after-br}] + [@b{-mistack}] [@b{-mno-istack}] + [@b{-mhard-float}] [@b{-mmp}] [@b{-mcp}] [@b{-mcache}] + [@b{-msecurity}] [@b{-mtrust}] + [@b{-mdsp}] [@b{-medsp}] [@b{-mvdsp}] +@end ifset @ifset D10V @emph{Target D10V options:} @@ -979,6 +999,25 @@ the Blackfin processor family. See the info pages for documentation of the CRIS-specific options. @end ifset +@ifset CSKY + +@ifclear man +@xref{C-SKY Options}, for the options available when @value{AS} is +configured for the C-SKY processor family. +@end ifclear + +@ifset man +@c man begin OPTIONS +The following options are available when @value{AS} is configured for +the C-SKY processor family. +@c man end +@c man begin INCLUDE +@include c-csky.texi +@c ended inside the included file +@end ifset + +@end ifset + @ifset D10V The following options are available when @value{AS} is configured for a D10V processor. @@ -7548,6 +7587,9 @@ subject, see the hardware manufacturer's manual. @ifset CRIS * CRIS-Dependent:: CRIS Dependent Features @end ifset +@ifset CSKY +* C-SKY-Dependent:: C-SKY Dependent Features +@end ifset @ifset D10V * D10V-Dependent:: D10V Dependent Features @end ifset @@ -7731,6 +7773,10 @@ subject, see the hardware manufacturer's manual. @include c-cris.texi @end ifset +@ifset CSKY +@include c-csky.texi +@end ifset + @ifset Renesas-all @ifclear GENERIC @node Machine Dependencies diff --git a/gas/doc/c-csky.texi b/gas/doc/c-csky.texi new file mode 100644 index 0000000..5087de9 --- /dev/null +++ b/gas/doc/c-csky.texi @@ -0,0 +1,195 @@ +@c Copyright (C) 2012-2018 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end +@ifset GENERIC +@page +@node C-SKY-Dependent +@chapter C-SKY Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter C-SKY Dependent Features +@end ifclear + +@cindex C-SKY support +@menu +* C-SKY Options:: Options +* C-SKY Syntax:: Syntax +@end menu + +@node C-SKY Options +@section Options +@cindex C-SKY options +@cindex options for C-SKY + +@c man begin OPTIONS +@table @gcctabopt + +@cindex @code{march} command-line option, C-SKY +@item -march=@var{archname} +Assemble for architecture @var{archname}. The @option{--help} option +lists valid values for @var{archname}. + +@cindex @code{mcpu} command-line option, C-SKY +@item -mcpu=@var{cpuname} +Assemble for architecture @var{cpuname}. The @option{--help} option +lists valid values for @var{cpuname}. + +@cindex @code{EL} command-line option, C-SKY +@cindex @code{mlittle-endian} command-line option, C-SKY +@item -EL +@itemx -mlittle-endian +Generate little-endian output. + +@cindex @code{EB} command-line option, C-SKY +@cindex @code{mbig-endian} command-line option, C-SKY +@item -EB +@itemx -mbig-endian +Generate big-endian output. + +@cindex @code{fpic} command-line option, C-SKY +@cindex @code{pic} command-line option, C-SKY +@item -fpic +@itemx -pic +Generate position-independent code. + +@cindex @code{mljump} command-line option, C-SKY +@cindex @code{mno-ljump} command-line option, C-SKY +@item -mljump +@itemx -mno-ljump +Enable/disable transformation of the short branch instructions +@code{jbf}, @code{jbt}, and @code{jbr} to @code{jmpi}. +This option is for V2 processors only. +It is ignored on CK801 and CK802 targets, which do not support the @code{jmpi} +instruction, and is enabled by default for other processors. + +@cindex @code{mbranch-stub} command-line option, C-SKY +@cindex @code{mno-branch-stub} command-line option, C-SKY +@item -mbranch-stub +@itemx -mno-branch-stub +Pass through @code{R_CKCORE_PCREL_IMM26BY2} relocations for @code{bsr} +instructions to the linker. + +This option is only available for bare-metal C-SKY V2 ELF targets, +where it is enabled by default. It cannot be used in code that will be +dynamically linked against shared libraries. + +@cindex @code{force2bsr} command-line option, C-SKY +@cindex @code{mforce2bsr} command-line option, C-SKY +@cindex @code{no-force2bsr} command-line option, C-SKY +@cindex @code{mno-force2bsr} command-line option, C-SKY +@item -force2bsr +@itemx -mforce2bsr +@itemx -no-force2bsr +@itemx -mno-force2bsr +Enable/disable transformation of @code{jbsr} instructions to @code{bsr}. +This option is always enabled (and @option{-mno-force2bsr} is ignored) +for CK801/CK802 targets. It is also always enabled when +@option{-mbranch-stub} is in effect. + +@cindex @code{jsri2bsr} command-line option, C-SKY +@cindex @code{mjsri2bsr} command-line option, C-SKY +@cindex @code{no-jsri2bsr} command-line option, C-SKY +@cindex @code{mno-jsri2bsr} command-line option, C-SKY +@item -jsri2bsr +@itemx -mjsri2bsr +@itemx -no-jsri2bsr +@itemx -mno-jsri2bsr +Enable/disable transformation of @code{jsri} instructions to @code{bsr}. +This option is enabled by default. + +@cindex @code{mnolrw} command-line option, C-SKY +@cindex @code{mno-lrw} command-line option, C-SKY +@item -mnolrw +@itemx -mno-lrw +Enable/disable transformation of @code{lrw} instructions into a +@code{movih}/@code{ori} pair. + +@cindex @code{melrw} command-line option, C-SKY +@cindex @code{mno-elrw} command-line option, C-SKY +@item -melrw +@itemx -mno-elrw +Enable/disable extended @code{lrw} instructions. +This option is enabled by default for CK800-series processors. + +@cindex @code{mlaf} command-line option, C-SKY +@cindex @code{mliterals-after-func} command-line option, C-SKY +@cindex @code{mno-laf} command-line option, C-SKY +@cindex @code{mno-literals-after-func} command-line option, C-SKY +@item -mlaf +@itemx -mliterals-after-func +@itemx -mno-laf +@itemx -mno-literals-after-func +Enable/disable placement of literal pools after each function. + +@cindex @code{mlabr} command-line option, C-SKY +@cindex @code{mliterals-after-br} command-line option, C-SKY +@cindex @code{mno-labr} command-line option, C-SKY +@cindex @code{mnoliterals-after-br} command-line option, C-SKY +@item -mlabr +@itemx -mliterals-after-br +@itemx -mno-labr +@itemx -mnoliterals-after-br +Enable/disable placement of literal pools after unconditional branches. +This option is enabled by default. + +@cindex @code{mistack} command-line option, C-SKY +@cindex @code{mno-istack} command-line option, C-SKY +@item -mistack +@itemx -mno-istack +Enable/disable interrupt stack instructions. This option is enabled by +default on CK801, CK802, and CK802 processors. + +@end table + +The following options explicitly enable certain optional instructions. +These features are also enabled implicitly by using @code{-mcpu=} to specify +a processor that supports it. + +@table @gcctabopt +@cindex @code{mhard-float} command-line option, C-SKY +@item -mhard-float +Enable hard float instructions. + +@cindex @code{mmp} command-line option, C-SKY +@item -mmp +Enable multiprocessor instructions. + +@cindex @code{mcp} command-line option, C-SKY +@item -mcp +Enable coprocessor instructions. + +@cindex @code{mcache} command-line option, C-SKY +@item -mcache +Enable cache prefetch instruction. + +@cindex @code{msecurity} command-line option, C-SKY +@item -msecurity +Enable C-SKY security instructions. + +@cindex @code{mtrust} command-line option, C-SKY +@item -mtrust +Enable C-SKY trust instructions. + +@cindex @code{mdsp} command-line option, C-SKY +@item -mdsp +Enable DSP instructions. + +@cindex @code{medsp} command-line option, C-SKY +@item -medsp +Enable enhanced DSP instructions. + +@cindex @code{mvdsp} command-line option, C-SKY +@item -mvdsp +Enable vector DSP instructions. + +@end table +@c man end + +@node C-SKY Syntax +@section Syntax + +@code{@value{AS}} implements the standard C-SKY assembler syntax +documented in the +@cite{C-SKY V2 CPU Applications Binary Interface Standards Manual}. diff --git a/gas/testsuite/gas/csky/801_relax.d b/gas/testsuite/gas/csky/801_relax.d new file mode 100644 index 0000000..1677fb1 --- /dev/null +++ b/gas/testsuite/gas/csky/801_relax.d @@ -0,0 +1,14 @@ +#name: csky - 801_relax +#as: -march=ck801 +#objdump: -d + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*2:\s*0803\s*bt\s*0x8\s*.* +\s*4:\s*e800025c\s*br\s*0x4bc\s*.* +#... +\s*4bc:\s*0c03\s*bf\s*0x4c2\s*.* +\s*4be:\s*e800fda2\s*br\s*0x2\s*.* +#... diff --git a/gas/testsuite/gas/csky/801_relax.s b/gas/testsuite/gas/csky/801_relax.s new file mode 100644 index 0000000..56a7421 --- /dev/null +++ b/gas/testsuite/gas/csky/801_relax.s @@ -0,0 +1,16 @@ +# Test ck801 jbf/jbt branch relaxation. + + addu a1, a2, a3 +.L1: + jbf .L2 + addu a3, a2, a1 + + .rept 600 + nop + .endr + + + addu a1, a2, a3 +.L2: + jbt .L1 + addu a3, a2, a1 diff --git a/gas/testsuite/gas/csky/802j.d b/gas/testsuite/gas/csky/802j.d new file mode 100644 index 0000000..af7c857 --- /dev/null +++ b/gas/testsuite/gas/csky/802j.d @@ -0,0 +1,13 @@ +# name: csky - 802j +#as: -mcpu=ck802j -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*1463\s*ipop +\s*[0-9a-f]*:\s*1462\s*ipush +\s*[0-9a-f]*:\s*1460\s*nie +\s*[0-9a-f]*:\s*1461\s*nir +\s*[0-9a-f]*:\s*3ae0\s*jmpix\s*r2,\s*16.* diff --git a/gas/testsuite/gas/csky/802j.s b/gas/testsuite/gas/csky/802j.s new file mode 100644 index 0000000..852cd2c --- /dev/null +++ b/gas/testsuite/gas/csky/802j.s @@ -0,0 +1,7 @@ +.text +all: + ipop + ipush + nie + nir + jmpix r2, 16 diff --git a/gas/testsuite/gas/csky/all.d b/gas/testsuite/gas/csky/all.d new file mode 100644 index 0000000..c5da5b0 --- /dev/null +++ b/gas/testsuite/gas/csky/all.d @@ -0,0 +1,150 @@ +# name: csky - all +#as: -mcpu=ck610e -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*0000\s*bkpt +\s*[0-9a-f]*:\s*0001\s*sync +\s*[0-9a-f]*:\s*0002\s*rte +\s*[0-9a-f]*:\s*0002\s*rte +\s*[0-9a-f]*:\s*0003\s*rfi +\s*[0-9a-f]*:\s*0004\s*stop +\s*[0-9a-f]*:\s*0005\s*wait +\s*[0-9a-f]*:\s*0006\s*doze +\s*[0-9a-f]*:\s*0007\s*idly4 +\s*[0-9a-f]*:\s*000b\s*trap\s*3 +\s*[0-9a-f]*:\s*0021\s*mvc\s*r1 +\s*[0-9a-f]*:\s*0032\s*mvcv\s*r2 +\s*[0-9a-f]*:\s*0042\s*ldq\s*r4-r7, \(r2\) +\s*[0-9a-f]*:\s*0052\s*stq\s*r4-r7, \(r2\) +\s*[0-9a-f]*:\s*0061\s*ldm\s*r1-r15, \(sp\) +\s*[0-9a-f]*:\s*0082\s*dect\s*r2, r2, 1 +\s*[0-9a-f]*:\s*0092\s*decf\s*r2, r2, 1 +\s*[0-9a-f]*:\s*00a2\s*inct\s*r2, r2, 1 +\s*[0-9a-f]*:\s*00b2\s*incf\s*r2, r2, 1 +\s*[0-9a-f]*:\s*00c1\s*jmp\s*r1 +\s*[0-9a-f]*:\s*00d1\s*jsr\s*r1 +\s*[0-9a-f]*:\s*00eb\s*ff1\s*r11, r11 +\s*[0-9a-f]*:\s*00f1\s*brev\s*r1, r1 +\s*[0-9a-f]*:\s*0102\s*xtrb3\s*r1, r2 +\s*[0-9a-f]*:\s*0112\s*xtrb2\s*r1, r2 +\s*[0-9a-f]*:\s*0122\s*xtrb1\s*r1, r2 +\s*[0-9a-f]*:\s*0132\s*xtrb0\s*r1, r2 +\s*[0-9a-f]*:\s*0132\s*xtrb0\s*r1, r2 +\s*[0-9a-f]*:\s*0132\s*xtrb0\s*r1, r2 +\s*[0-9a-f]*:\s*1213\s*mov\s*r3, r1 +\s*[0-9a-f]*:\s*0142\s*zextb\s*r2, r2 +\s*[0-9a-f]*:\s*0152\s*sextb\s*r2, r2 +\s*[0-9a-f]*:\s*0162\s*zexth\s*r2, r2 +\s*[0-9a-f]*:\s*0172\s*sexth\s*r2, r2 +\s*[0-9a-f]*:\s*0182\s*declt\s*r2, r2, 1 +\s*[0-9a-f]*:\s*01b1\s*decne\s*r1, r1, 1 +\s*[0-9a-f]*:\s*01a1\s*decgt\s*r1, r1, 1 +\s*[0-9a-f]*:\s*01c1\s*clrt\s*r1 +\s*[0-9a-f]*:\s*01d1\s*clrf\s*r1 +\s*[0-9a-f]*:\s*01e3\s*abs\s*r3, r3 +\s*[0-9a-f]*:\s*01fc\s*not\s*r12, r12 +\s*[0-9a-f]*:\s*0221\s*movt\s*r1, r2 +\s*[0-9a-f]*:\s*0343\s*mult\s*r3, r3, r4 +\s*[0-9a-f]*:\s*0587\s*subu\s*r7, r7, r8 +\s*[0-9a-f]*:\s*0587\s*subu\s*r7, r7, r8 +\s*[0-9a-f]*:\s*06a9\s*addc\s*r9, r9, r10 +\s*[0-9a-f]*:\s*07cb\s*subc\s*r11, r11, r12 +\s*[0-9a-f]*:\s*0adc\s*movf\s*r12, r13 +\s*[0-9a-f]*:\s*0bdc\s*lsr\s*r12, r12, r13 +\s*[0-9a-f]*:\s*0ced\s*cmphs\s*r13, r14 +\s*[0-9a-f]*:\s*0ded\s*cmplt\s*r13, r14 +\s*[0-9a-f]*:\s*0eed\s*tst\s*r13, r14 +\s*[0-9a-f]*:\s*0fed\s*cmpne\s*r13, r14 +\s*[0-9a-f]*:\s*11f7\s*psrclr\s*ie, fe, ee +\s*[0-9a-f]*:\s*1253\s*mov\s*r3, r5 +\s*[0-9a-f]*:\s*1332\s*bgenr\s*r2, r3 +\s*[0-9a-f]*:\s*1643\s*and\s*r3, r3, r4 +\s*[0-9a-f]*:\s*1543\s*ixw\s*r3, r3, r4 +\s*[0-9a-f]*:\s*1a43\s*asr\s*r3, r3, r4 +\s*[0-9a-f]*:\s*1c43\s*addu\s*r3, r3, r4 +\s*[0-9a-f]*:\s*1d32\s*ixh\s*r2, r2, r3 +\s*[0-9a-f]*:\s*1f43\s*andn\s*r3, r3, r4 +\s*[0-9a-f]*:\s*21f3\s*addi\s*r3, r3, 32 +\s*[0-9a-f]*:\s*23f3\s*cmplti\s*r3, 32 +\s*[0-9a-f]*:\s*2413\s*subi\s*r3, r3, 2 +\s*[0-9a-f]*:\s*2823\s*rsubi\s*r3, r3, 2 +\s*[0-9a-f]*:\s*2a33\s*cmpnei\s*r3, 3 +\s*[0-9a-f]*:\s*2c83\s*bmaski\s*r3, 8 +\s*[0-9a-f]*:\s*2c13\s*divu\s*r3, r3, r1 +\s*[0-9a-f]*:\s*2c22\s*mflos\s*r2 +\s*[0-9a-f]*:\s*2c32\s*mfhis\s*r2 +\s*[0-9a-f]*:\s*2c42\s*mtlo\s*r2 +\s*[0-9a-f]*:\s*2c52\s*mthi\s*r2 +\s*[0-9a-f]*:\s*2c62\s*mflo\s*r2 +\s*[0-9a-f]*:\s*2c72\s*mfhi\s*r2 +\s*[0-9a-f]*:\s*2e33\s*andi\s*r3, r3, 3 +\s*[0-9a-f]*:\s*3033\s*bclri\s*r3, r3, 3 +\s*[0-9a-f]*:\s*3293\s*bgeni\s*r3, 9 +\s*[0-9a-f]*:\s*6403\s*movi\s*r3, 64 +\s*[0-9a-f]*:\s*3213\s*divs\s*r3, r3, r1 +\s*[0-9a-f]*:\s*1221\s*mov\s*r1, r2 +\s*[0-9a-f]*:\s*3213\s*divs\s*r3, r3, r1 +\s*[0-9a-f]*:\s*3493\s*bseti\s*r3, r3, 9 +\s*[0-9a-f]*:\s*3693\s*btsti\s*r3, 9 +\s*[0-9a-f]*:\s*3803\s*xsr\s*r3, r3, 1 +\s*[0-9a-f]*:\s*3823\s*rotli\s*r3, r3, 2 +\s*[0-9a-f]*:\s*3a03\s*asrc\s*r3, r3, 1 +\s*[0-9a-f]*:\s*3a31\s*asri\s*r1, r1, 3 +\s*[0-9a-f]*:\s*67f7\s*movi\s*r7, 127 +\s*[0-9a-f]*:\s*8200\s*ld.w\s*r2,\s*\(r0,\s*0x0\) +\s*[0-9a-f]*:\s*8210\s*ld.w\s*r2,\s*\(r0,\s*0x4\) +\s*[0-9a-f]*:\s*8220\s*ld.w\s*r2,\s*\(r0,\s*0x8\) +\s*[0-9a-f]*:\s*9200\s*st.w\s*r2,\s*\(r0,\s*0x0\) +\s*[0-9a-f]*:\s*9210\s*st.w\s*r2,\s*\(r0,\s*0x4\) +\s*[0-9a-f]*:\s*9220\s*st.w\s*r2,\s*\(r0,\s*0x8\) +\s*[0-9a-f]*:\s*c210\s*ld.h\s*r2,\s*\(r0,\s*0x2\) +\s*[0-9a-f]*:\s*c220\s*ld.h\s*r2,\s*\(r0,\s*0x4\) +\s*[0-9a-f]*:\s*d210\s*st.h\s*r2,\s*\(r0,\s*0x2\) +\s*[0-9a-f]*:\s*d220\s*st.h\s*r2,\s*\(r0,\s*0x4\) +\s*[0-9a-f]*:\s*a200\s*ld.b\s*r2,\s*\(r0,\s*0x0\) +\s*[0-9a-f]*:\s*a210\s*ld.b\s*r2,\s*\(r0,\s*0x1\) +\s*[0-9a-f]*:\s*b200\s*st.b\s*r2,\s*\(r0,\s*0x0\) +\s*[0-9a-f]*:\s*b210\s*st.b\s*r2,\s*\(r0,\s*0x1\) +\s*[0-9a-f]*:\s*e798\s*bt\s*0x0.* +\s*[0-9a-f]*:\s*ef97\s*bf\s*0x0.* +\s*[0-9a-f]*:\s*f796\s*br\s*0x0.* +\s*[0-9a-f]*:\s*0c00\s*cmphs\s*r0, r0 +\s*[0-9a-f]*:\s*0f00\s*cmpne\s*r0, r0 +\s*[0-9a-f]*:\s*2205\s*cmplti\s*r5, 1 +\s*[0-9a-f]*:\s*2263\s*cmplti\s*r3, 7 +\s*[0-9a-f]*:\s*2807\s*rsubi\s*r7, r7, 0 +\s*[0-9a-f]*:\s*2a06\s*cmpnei\s*r6, 0 +\s*[0-9a-f]*:\s*37f0\s*btsti\s*r0, 31 +\s*[0-9a-f]*:\s*31f3\s*bclri\s*r3, r3, 31 +\s*[0-9a-f]*:\s*6404\s*movi\s*r4, 64 +\s*[0-9a-f]*:\s*3274\s*bgeni\s*r4, 7 +\s*[0-9a-f]*:\s*3501\s*bseti\s*r1, r1, 16 +\s*[0-9a-f]*:\s*3644\s*btsti\s*r4, 4 +\s*[0-9a-f]*:\s*38c6\s*rotli\s*r6, r6, 12 +\s*[0-9a-f]*:\s*39f2\s*rotli\s*r2, r2, 31 +\s*[0-9a-f]*:\s*1200\s*mov\s*r0, r0 +\s*[0-9a-f]*:\s*0007\s*idly4 +\s*[0-9a-f]*:\s*0644\s*addc\s*r4, r4, r4 +\s*[0-9a-f]*:\s*0655\s*addc\s*r5, r5, r5 +\s*[0-9a-f]*:\s*0132\s*xtrb0\s*r1, r2 +\s*[0-9a-f]*:\s*0151\s*sextb\s*r1, r1 +\s*[0-9a-f]*:\s*0123\s*xtrb1\s*r1, r3 +\s*[0-9a-f]*:\s*0151\s*sextb\s*r1, r1 +\s*[0-9a-f]*:\s*0114\s*xtrb2\s*r1, r4 +\s*[0-9a-f]*:\s*0151\s*sextb\s*r1, r1 +\s*[0-9a-f]*:\s*0221\s*movt\s*r1, r2 +\s*[0-9a-f]*:\s*0a31\s*movf\s*r1, r3 +\s*[0-9a-f]*:\s*0d22\s*cmplt\s*r2, r2 +\s*[0-9a-f]*:\s*0672\s*addc\s*r2, r2, r7 +\s*[0-9a-f]*:\s*0683\s*addc\s*r3, r3, r8 +\s*[0-9a-f]*:\s*0c44\s*cmphs\s*r4, r4 +\s*[0-9a-f]*:\s*0764\s*subc\s*r4, r4, r6 +\s*[0-9a-f]*:\s*0775\s*subc\s*r5, r5, r7 +\s*[0-9a-f]*:\s*1e26\s*or\s*r6, r6, r2 +\s*[0-9a-f]*:\s*1e37\s*or\s*r7, r7, r3 +\s*[0-9a-f]*:\s*1715\s*xor\s*r5, r5, r1 +\s*[0-9a-f]*:\s*1726\s*xor\s*r6, r6, r2 diff --git a/gas/testsuite/gas/csky/all.s b/gas/testsuite/gas/csky/all.s new file mode 100644 index 0000000..a21bd47 --- /dev/null +++ b/gas/testsuite/gas/csky/all.s @@ -0,0 +1,132 @@ +.text +all: + bkpt + sync + rte + rfe + rfi + stop + wait + doze + idly4 + trap 3 + mvc r1 + mvcv r2 + ldq r4-r7, (r2) + stq r4-r7, (r2) + ldm r1-r15, (r0) + dect r2 + decf r2 + inct r2 + incf r2 + jmp r1 + jsr r1 + ff1 r11 + brev r1 + xtrb3 r2 + xtrb2 r2 + xtrb1 r2 + xtrb0 r2 + xtrb0 r1, r2 + xtrb0 r3, r2 + zextb r2 + sextb r2 + zexth r2 + sexth r2 + declt r2 + decne r1 + decgt r1 + clrt r1 + clrf r1 + abs r3 + not r12 + movt r1, r2 + mult r3, r4 + sub r7, r8 + subu r7, r8 + addc r9, r10 + subc r11, r12 + movf r12, r13 + lsr r12, r13 + cmphs r13, r14 + cmplt r13, r14 + tst r13, r14 + cmpne r13, r14 + psrclr ee, ie, fe + mov r3, r5 + bgenr r2, r3 + and r3, r4 + ixw r3, r4 + asr r3, r4 + addu r3, r4 + ixh r2, r3 + andn r3, r4 + addi r3, 32 + cmplti r3, 32 + subi r3, 2 + rsubi r3, 2 + cmpnei r3, 3 + bmaski r3, 8 + divu r3, r1 + mflos r2 + mfhis r2 + mtlo r2 + mthi r2 + mflo r2 + mfhi r2 + andi r3, 3 + bclri r3, 3 + bgeni r3, 9 + bgeni r3, 6 + divs r3, r1 + divs r3, r2 + bseti r3, 9 + btsti r3, 9 + xsr r3 + rotli r3, 2 + asrc r3 + asri r1, 3 + movi r7, 127 + ld r2, (r0, 0) + ldw r2, (r0, 4) + ld.w r2, (r0, 8) + st r2, (r0, 0) + stw r2, (r0, 4) + st.w r2, (r0, 8) + ldh r2, (r0, 2) + ld.h r2, (r0, 4) + sth r2, (r0, 2) + st.h r2, (r0, 4) + ldb r2, (r0, 0) + ld.b r2, (r0, 1) + stb r2, (r0, 0) + st.b r2, (r0, 1) + bt all + bf all + br all + setc + clrc + tstle r5 + cmplei r3, 6 + neg r7 + tstne r6 + tstlt r0 + mclri r3, 0x80000000 + mgeni r4, 0x40 + mgeni r4, 0x80 + mseti r1, 0x10000 + mtsti r4, 16 + rori r6, 20 + rotri r2, 1 + nop + idly 4 + rolc r4, 1 + rotlc r5, 1 + sxtrb0 r1, r2 + sxtrb1 r1, r3 + sxtrb2 r1, r4 + movtf r1, r2, r3 + addc64 r2, r2, r7 + subc64 r4, r4, r6 + or64 r6, r6, r2 + xor64 r5, r5, r1 diff --git a/gas/testsuite/gas/csky/bsr1.d b/gas/testsuite/gas/csky/bsr1.d new file mode 100644 index 0000000..91ba60d --- /dev/null +++ b/gas/testsuite/gas/csky/bsr1.d @@ -0,0 +1,12 @@ +# name: bsr1 - csky +#as: -mcpu=ck610 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*ffff\s*bsr\s*0x0\s*\/\/\s*0\s*\<lable\> +\s*[0-9a-f]:\s*f7fe\s*br\s*0x0\s*\/\/\s*0\s*\<lable*\> +\s*[0-9a-f]:\s*e7fd\s*bt\s*0x0\s*\/\/\s*0\s*\<lable*\> +\s*[0-9a-f]:\s*effc\s*bf\s*0x0\s*\/\/\s*0\s*\<lable*\> diff --git a/gas/testsuite/gas/csky/bsr1.s b/gas/testsuite/gas/csky/bsr1.s new file mode 100644 index 0000000..8cc5c81 --- /dev/null +++ b/gas/testsuite/gas/csky/bsr1.s @@ -0,0 +1,6 @@ +.text +lable: + bsr lable + br lable + bt lable + bf lable diff --git a/gas/testsuite/gas/csky/bsr2.d b/gas/testsuite/gas/csky/bsr2.d new file mode 100644 index 0000000..c538acd --- /dev/null +++ b/gas/testsuite/gas/csky/bsr2.d @@ -0,0 +1,9 @@ +# name: bsr2 - csky +#as: -mcpu=ck610 +#objdump: -r + +.*: +file format .*csky.* + +RELOCATION RECORDS FOR \[\.text\]: +#... +[0-9a-f]*\s*R_CKCORE_PCREL_IMM11BY2\s*hello diff --git a/gas/testsuite/gas/csky/bsr2.s b/gas/testsuite/gas/csky/bsr2.s new file mode 100644 index 0000000..0bed607 --- /dev/null +++ b/gas/testsuite/gas/csky/bsr2.s @@ -0,0 +1,3 @@ +.text +lable: + bsr hello diff --git a/gas/testsuite/gas/csky/csky.exp b/gas/testsuite/gas/csky/csky.exp new file mode 100644 index 0000000..1f18b39 --- /dev/null +++ b/gas/testsuite/gas/csky/csky.exp @@ -0,0 +1,7 @@ +# +# Some CSKY tests +# + +if {[istarget csky*-*-*]} { + run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +} diff --git a/gas/testsuite/gas/csky/csky_vdsp.d b/gas/testsuite/gas/csky/csky_vdsp.d new file mode 100644 index 0000000..0e2eaa2 --- /dev/null +++ b/gas/testsuite/gas/csky/csky_vdsp.d @@ -0,0 +1,364 @@ +# name: csky - vdsp +#as: -mcpu=ck810v -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*f8623c02\s*vstrq\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623d02\s*vstrq\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623e02\s*vstrq\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623402\s*vldrq\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623502\s*vldrq\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623602\s*vldrq\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623802\s*vstrd\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623902\s*vstrd\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623a02\s*vstrd\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623002\s*vldrd\.8\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623102\s*vldrd\.16\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8623202\s*vldrd\.32\s*fr2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*f8022412\s*vldq\.8\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022512\s*vldq\.16\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022612\s*vldq\.32\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022c12\s*vstq\.8\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022d12\s*vstq\.16\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022e12\s*vstq\.32\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022022\s*vldd\.8\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022122\s*vldd\.16\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022222\s*vldd\.32\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022822\s*vstd\.8\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022922\s*vstd\.16\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*f8022a22\s*vstd\.32\s*fr2,\s*\(r2,\s*0x10\) +\s*[0-9a-f]*:\s*c43eb020\s*vmulsh\s*r30,\s*r1 +\s*[0-9a-f]*:\s*c7e0b040\s*vmulsha\s*r0,\s*r31 +\s*[0-9a-f]*:\s*c58cb420\s*vmulsw\s*r12,\s*r12 +\s*[0-9a-f]*:\s*c6bcb440\s*vmulswa\s*r28,\s*r21 +\s*[0-9a-f]*:\s*c481b480\s*vmulsws\s*r1,\s*r4 +\s*[0-9a-f]*:\s*f9221201\s*vmfvr.u8\s*r1,\s*vr2\[9\] +\s*[0-9a-f]*:\s*f8041223\s*vmfvr.u16\s*r3,\s*vr4\[0\] +\s*[0-9a-f]*:\s*f8a8125f\s*vmfvr.u32\s*r31,\s*vr8\[5\] +\s*[0-9a-f]*:\s*f824128d\s*vmfvr.s8\s*r13,\s*vr4\[1\] +\s*[0-9a-f]*:\s*f9af12b7\s*vmfvr.s16\s*r23,\s*vr15\[13\] +\s*[0-9a-f]*:\s*f8101305\s*vmtvr.u8\s*vr5\[0\],\s*r16 +\s*[0-9a-f]*:\s*f8ea1324\s*vmtvr.u16\s*vr4\[7\],\s*r10 +\s*[0-9a-f]*:\s*f9ea134f\s*vmtvr.u32\s*vr15\[15\],\s*r10 +\s*[0-9a-f]*:\s*f94a0e81\s*vdup.8\s*fr1,\s*vr10\[10\] +\s*[0-9a-f]*:\s*f83a0e8f\s*vdup.16\s*fr15,\s*vr10\[1\] +\s*[0-9a-f]*:\s*faaa0e87\s*vdup.32\s*fr7,\s*vr10\[5\] +\s*[0-9a-f]*:\s*f8030c02\s*vmov\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030062\s*vcadd\.eu8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130062\s*vcadd\.eu16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030072\s*vcadd\.es8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130072\s*vcadd\.es16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030c22\s*vmov\.eu8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130c22\s*vmov\.eu16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030c32\s*vmov\.es8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130c32\s*vmov\.es16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d02\s*vmov\.u16\.l\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d02\s*vmov\.u32\.l\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d12\s*vmov\.s16\.l\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d12\s*vmov\.s32\.l\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d42\s*vmov\.u16\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d42\s*vmov\.u32\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d52\s*vmov\.s16\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d52\s*vmov\.s32\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d62\s*vmov\.u16\.h\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d62\s*vmov\.u32\.h\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d72\s*vmov\.s16\.h\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d72\s*vmov\.s32\.h\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d82\s*vmov\.u16\.rh\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d82\s*vmov\.u32\.rh\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130d92\s*vmov\.s16\.rh\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030d92\s*vmov\.s32\.rh\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130dc2\s*vstou\.u16\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030dc2\s*vstou\.u32\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130dd2\s*vstou\.s16\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030dd2\s*vstou\.s32\.sl\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030e62\s*vrev\.8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130e62\s*vrev\.16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030e62\s*vrev\.32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030ea2\s*vcnt1\.8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030ec2\s*vclz\.8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130ec2\s*vclz\.16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030ec2\s*vclz\.32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030ee2\s*vcls\.u8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130ee2\s*vcls\.u16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030ee2\s*vcls\.u32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030ef2\s*vcls\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130ef2\s*vcls\.s16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030ef2\s*vcls\.s32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8031012\s*vabs\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8131012\s*vabs\.s16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa031012\s*vabs\.s32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8031042\s*vabs\.u8\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8131042\s*vabs\.u16\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa031042\s*vabs\.u32\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8031052\s*vabs\.s8\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8131052\s*vabs\.s16\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa031052\s*vabs\.s32\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8031082\s*vneg\.u8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8131082\s*vneg\.u16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa031082\s*vneg\.u32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8031092\s*vneg\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8131092\s*vneg\.s16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa031092\s*vneg\.s32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80310c2\s*vneg\.u8\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f81310c2\s*vneg\.u16\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa0310c2\s*vneg\.u32\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80310d2\s*vneg\.s8\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f81310d2\s*vneg\.s16\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa0310d2\s*vneg\.s32\.s\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030882\s*vcmphsz\.u8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130882\s*vcmphsz\.u16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030882\s*vcmphsz\.u32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8030892\s*vcmphsz\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8130892\s*vcmphsz\.s16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa030892\s*vcmphsz\.s32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80308a2\s*vcmpltz\.u8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f81308a2\s*vcmpltz\.u16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa0308a2\s*vcmpltz\.u32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80308b2\s*vcmpltz\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f81308b2\s*vcmpltz\.s16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa0308b2\s*vcmpltz\.s32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80308c2\s*vcmpnez\.u8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f81308c2\s*vcmpnez\.u16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa0308c2\s*vcmpnez\.u32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80308d2\s*vcmpnez\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f80308d2\s*vcmpnez\.s8\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f81308d2\s*vcmpnez\.s16\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*fa0308d2\s*vcmpnez\.s32\s*vr2,\s*vr3 +\s*[0-9a-f]*:\s*f8830f42\s*vtrch\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930f42\s*vtrch\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830f42\s*vtrch\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830f62\s*vtrcl\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930f62\s*vtrcl\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830f62\s*vtrcl\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830002\s*vadd\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930002\s*vadd\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830002\s*vadd\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830012\s*vadd\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930012\s*vadd\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830012\s*vadd\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830022\s*vadd\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930022\s*vadd\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830032\s*vadd\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930032\s*vadd\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830042\s*vcadd\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930042\s*vcadd\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830042\s*vcadd\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830052\s*vcadd\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930052\s*vcadd\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830052\s*vcadd\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930142\s*vadd\.xu16\.sl\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830142\s*vadd\.xu32\.sl\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930152\s*vadd\.xs16\.sl\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830152\s*vadd\.xs32\.sl\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930162\s*vadd\.xu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830162\s*vadd\.xu32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930172\s*vadd\.xs16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830172\s*vadd\.xs32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830182\s*vaddh\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930182\s*vaddh\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830182\s*vaddh\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830192\s*vaddh\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930192\s*vaddh\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830192\s*vaddh\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88301a2\s*vaddh\.u8\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89301a2\s*vaddh\.u16\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8301a2\s*vaddh\.u32\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88301b2\s*vaddh\.s8\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89301b2\s*vaddh\.s16\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8301b2\s*vaddh\.s32\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88301c2\s*vadd\.u8\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89301c2\s*vadd\.u16\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8301c2\s*vadd\.u32\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88301d2\s*vadd\.s8\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89301d2\s*vadd\.s16\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8301d2\s*vadd\.s32\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830202\s*vsub\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930202\s*vsub\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830202\s*vsub\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830212\s*vsub\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930212\s*vsub\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830212\s*vsub\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830222\s*vsub\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930222\s*vsub\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830232\s*vsub\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930232\s*vsub\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830242\s*vsabs\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930242\s*vsabs\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830242\s*vsabs\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830252\s*vsabs\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930252\s*vsabs\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830252\s*vsabs\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830262\s*vsabs\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930262\s*vsabs\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830272\s*vsabs\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930272\s*vsabs\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830282\s*vsabsa\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930282\s*vsabsa\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830282\s*vsabsa\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830292\s*vsabsa\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930292\s*vsabsa\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830292\s*vsabsa\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88302a2\s*vsabsa\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89302a2\s*vsabsa\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88302b2\s*vsabsa\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89302b2\s*vsabsa\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930362\s*vsub\.xu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830362\s*vsub\.xu32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930372\s*vsub\.xs16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830372\s*vsub\.xs32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830382\s*vsubh\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930382\s*vsubh\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830382\s*vsubh\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830392\s*vsubh\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930392\s*vsubh\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830392\s*vsubh\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88303a2\s*vsubh\.u8\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89303a2\s*vsubh\.u16\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8303a2\s*vsubh\.u32\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88303b2\s*vsubh\.s8\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89303b2\s*vsubh\.s16\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8303b2\s*vsubh\.s32\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88303c2\s*vsub\.u8\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89303c2\s*vsub\.u16\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8303c2\s*vsub\.u32\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88303d2\s*vsub\.s8\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89303d2\s*vsub\.s16\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8303d2\s*vsub\.s32\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830402\s*vmul\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930402\s*vmul\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830402\s*vmul\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830412\s*vmul\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930412\s*vmul\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830412\s*vmul\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830422\s*vmul\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930422\s*vmul\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830432\s*vmul\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930432\s*vmul\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830442\s*vmula\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930442\s*vmula\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830442\s*vmula\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830452\s*vmula\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930452\s*vmula\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830452\s*vmula\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830462\s*vmula\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930462\s*vmula\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830462\s*vmula\.eu32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830472\s*vmula\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930472\s*vmula\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830472\s*vmula\.es32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830482\s*vmuls\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930482\s*vmuls\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830482\s*vmuls\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830492\s*vmuls\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930492\s*vmuls\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830492\s*vmuls\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88304a2\s*vmuls\.eu8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89304a2\s*vmuls\.eu16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88304b2\s*vmuls\.es8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89304b2\s*vmuls\.es16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830682\s*vshr\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930682\s*vshr\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830682\s*vshr\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830692\s*vshr\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930692\s*vshr\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830692\s*vshr\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88306c2\s*vshr\.u8\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89306c2\s*vshr\.u16\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8306c2\s*vshr\.u32\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88306d2\s*vshr\.s8\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89306d2\s*vshr\.s16\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8306d2\s*vshr\.s32\.r\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830782\s*vshl\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930782\s*vshl\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830782\s*vshl\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830792\s*vshl\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930792\s*vshl\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830792\s*vshl\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88307c2\s*vshl\.u8\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89307c2\s*vshl\.u16\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8307c2\s*vshl\.u32\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88307d2\s*vshl\.s8\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89307d2\s*vshl\.s16\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8307d2\s*vshl\.s32\.s\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830802\s*vcmphs\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930802\s*vcmphs\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830802\s*vcmphs\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830812\s*vcmphs\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930812\s*vcmphs\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830812\s*vcmphs\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830822\s*vcmplt\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930822\s*vcmplt\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830822\s*vcmplt\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830832\s*vcmplt\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930832\s*vcmplt\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830832\s*vcmplt\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830842\s*vcmpne\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930842\s*vcmpne\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830842\s*vcmpne\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830852\s*vcmpne\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930852\s*vcmpne\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830852\s*vcmpne\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830902\s*vmax\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930902\s*vmax\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830902\s*vmax\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830912\s*vmax\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930912\s*vmax\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830912\s*vmax\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830922\s*vmin\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930922\s*vmin\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830922\s*vmin\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830932\s*vmin\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930932\s*vmin\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830932\s*vmin\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830982\s*vcmax\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930982\s*vcmax\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830982\s*vcmax\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830992\s*vcmax\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930992\s*vcmax\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830992\s*vcmax\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88309a2\s*vcmin\.u8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89309a2\s*vcmin\.u16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8309a2\s*vcmin\.u32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f88309b2\s*vcmin\.s8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f89309b2\s*vcmin\.s16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa8309b2\s*vcmin\.s32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830a02\s*vand\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930a02\s*vand\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830a02\s*vand\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830a22\s*vandn\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930a22\s*vandn\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830a22\s*vandn\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830a42\s*vor\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930a42\s*vor\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830a42\s*vor\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830a62\s*vnor\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930a62\s*vnor\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830a62\s*vnor\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830a82\s*vxor\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930a82\s*vxor\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830a82\s*vxor\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830b22\s*vtst\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930b22\s*vtst\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830b22\s*vtst\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830f02\s*vbpermz\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930f02\s*vbpermz\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830f02\s*vbpermz\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830f22\s*vbperm\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930f22\s*vbperm\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830f22\s*vbperm\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830fc2\s*vdch\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930fc2\s*vdch\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830fc2\s*vdch\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830fe2\s*vdcl\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930fe2\s*vdcl\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830fe2\s*vdcl\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830f82\s*vich\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930f82\s*vich\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830f82\s*vich\.32\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8830fa2\s*vicl\.8\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*f8930fa2\s*vicl\.16\s*vr2,\s*vr3,\s*vr4 +\s*[0-9a-f]*:\s*fa830fa2\s*vicl\.32\s*vr2,\s*vr3,\s*vr4 diff --git a/gas/testsuite/gas/csky/csky_vdsp.s b/gas/testsuite/gas/csky/csky_vdsp.s new file mode 100644 index 0000000..7ca46b7 --- /dev/null +++ b/gas/testsuite/gas/csky/csky_vdsp.s @@ -0,0 +1,359 @@ + +.text +vdsp_instructions: + vstrq.8 vr2, (r2, r3 << 0) + vstrq.16 vr2, (r2, r3 << 0) + vstrq.32 vr2, (r2, r3 << 0) + vldrq.8 vr2, (r2, r3 << 0) + vldrq.16 vr2, (r2, r3 << 0) + vldrq.32 vr2, (r2, r3 << 0) + vstrd.8 vr2, (r2, r3 << 0) + vstrd.16 vr2, (r2, r3 << 0) + vstrd.32 vr2, (r2, r3 << 0) + vldrd.8 vr2, (r2, r3 << 0) + vldrd.16 vr2, (r2, r3 << 0) + vldrd.32 vr2, (r2, r3 << 0) + vldq.8 vr2, (r2, 16) + vldq.16 vr2, (r2, 16) + vldq.32 vr2, (r2, 16) + vstq.8 vr2, (r2, 16) + vstq.16 vr2, (r2, 16) + vstq.32 vr2, (r2, 16) + vldd.8 vr2, (r2, 16) + vldd.16 vr2, (r2, 16) + vldd.32 vr2, (r2, 16) + vstd.8 vr2, (r2, 16) + vstd.16 vr2, (r2, 16) + vstd.32 vr2, (r2, 16) + vmulsh r30, r1 + vmulsha r0, r31 + vmulsw r12, r12 + vmulswa r28, r21 + vmulsws r1, r4 + vmfvr.u8 r1, vr2[9] + vmfvr.u16 r3, fr4[0] + vmfvr.u32 r31, vr8[5] + vmfvr.s8 r13, fr4[1] + vmfvr.s16 r23, vr15[13] + vmtvr.u8 vr5[0], r16 + vmtvr.u16 fr4[7], r10 + vmtvr.u32 vr15 [ 15 ] , r10 + vdup.8 vr1, vr10[10] + vdup.16 vr15, fr10[1] + vdup.32 fr7, fr10[5] + vmov vr2, vr3 + vcadd.eu8 vr2, vr3 + vcadd.eu16 vr2, vr3 + vcadd.es8 vr2, vr3 + vcadd.es16 vr2, vr3 + vmov.eu8 vr2, vr3 + vmov.eu16 vr2, vr3 + vmov.es8 vr2, vr3 + vmov.es16 vr2, vr3 + vmov.u16.l vr2, vr3 + vmov.u32.l vr2, vr3 + vmov.s16.l vr2, vr3 + vmov.s32.l vr2, vr3 + vmov.u16.sl vr2, vr3 + vmov.u32.sl vr2, vr3 + vmov.s16.sl vr2, vr3 + vmov.s32.sl vr2, vr3 + vmov.u16.h vr2, vr3 + vmov.u32.h vr2, vr3 + vmov.s16.h vr2, vr3 + vmov.s32.h vr2, vr3 + vmov.u16.rh vr2, vr3 + vmov.u32.rh vr2, vr3 + vmov.s16.rh vr2, vr3 + vmov.s32.rh vr2, vr3 + vstou.u16.sl vr2, vr3 + vstou.u32.sl vr2, vr3 + vstou.s16.sl vr2, vr3 + vstou.s32.sl vr2, vr3 + vrev.8 vr2, vr3 + vrev.16 vr2, vr3 + vrev.32 vr2, vr3 + vcnt1.8 vr2, vr3 + vclz.8 vr2, vr3 + vclz.16 vr2, vr3 + vclz.32 vr2, vr3 + vcls.u8 vr2, vr3 + vcls.u16 vr2, vr3 + vcls.u32 vr2, vr3 + vcls.s8 vr2, vr3 + vcls.s16 vr2, vr3 + vcls.s32 vr2, vr3 + vabs.s8 vr2, vr3 + vabs.s16 vr2, vr3 + vabs.s32 vr2, vr3 + vabs.u8.s vr2, vr3 + vabs.u16.s vr2, vr3 + vabs.u32.s vr2, vr3 + vabs.s8.s vr2, vr3 + vabs.s16.s vr2, vr3 + vabs.s32.s vr2, vr3 + vneg.u8 vr2, vr3 + vneg.u16 vr2, vr3 + vneg.u32 vr2, vr3 + vneg.s8 vr2, vr3 + vneg.s16 vr2, vr3 + vneg.s32 vr2, vr3 + vneg.u8.s vr2, vr3 + vneg.u16.s vr2, vr3 + vneg.u32.s vr2, vr3 + vneg.s8.s vr2, vr3 + vneg.s16.s vr2, vr3 + vneg.s32.s vr2, vr3 + vcmphsz.u8 vr2, vr3 + vcmphsz.u16 vr2, vr3 + vcmphsz.u32 vr2, vr3 + vcmphsz.s8 vr2, vr3 + vcmphsz.s16 vr2, vr3 + vcmphsz.s32 vr2, vr3 + vcmpltz.u8 vr2, vr3 + vcmpltz.u16 vr2, vr3 + vcmpltz.u32 vr2, vr3 + vcmpltz.s8 vr2, vr3 + vcmpltz.s16 vr2, vr3 + vcmpltz.s32 vr2, vr3 + vcmpnez.u8 vr2, vr3 + vcmpnez.u16 vr2, vr3 + vcmpnez.u32 vr2, vr3 + vcmpnez.s8 vr2, vr3 + vcmpnez.s8 vr2, vr3 + vcmpnez.s16 vr2, vr3 + vcmpnez.s32 vr2, vr3 + vtrch.8 vr2, vr3, vr4 + vtrch.16 vr2, vr3, vr4 + vtrch.32 vr2, vr3, vr4 + vtrcl.8 vr2, vr3, vr4 + vtrcl.16 vr2, vr3, vr4 + vtrcl.32 vr2, vr3, vr4 + vadd.u8 vr2, vr3, vr4 + vadd.u16 vr2, vr3, vr4 + vadd.u32 vr2, vr3, vr4 + vadd.s8 vr2, vr3, vr4 + vadd.s16 vr2, vr3, vr4 + vadd.s32 vr2, vr3, vr4 + vadd.eu8 vr2, vr3, vr4 + vadd.eu16 vr2, vr3, vr4 + vadd.es8 vr2, vr3, vr4 + vadd.es16 vr2, vr3, vr4 + vcadd.u8 vr2, vr3, vr4 + vcadd.u16 vr2, vr3, vr4 + vcadd.u32 vr2, vr3, vr4 + vcadd.s8 vr2, vr3, vr4 + vcadd.s16 vr2, vr3, vr4 + vcadd.s32 vr2, vr3, vr4 + vadd.xu16.sl vr2, vr3, vr4 + vadd.xu32.sl vr2, vr3, vr4 + vadd.xs16.sl vr2, vr3, vr4 + vadd.xs32.sl vr2, vr3, vr4 + vadd.xu16 vr2, vr3, vr4 + vadd.xu32 vr2, vr3, vr4 + vadd.xs16 vr2, vr3, vr4 + vadd.xs32 vr2, vr3, vr4 + vaddh.u8 vr2, vr3, vr4 + vaddh.u16 vr2, vr3, vr4 + vaddh.u32 vr2, vr3, vr4 + vaddh.s8 vr2, vr3, vr4 + vaddh.s16 vr2, vr3, vr4 + vaddh.s32 vr2, vr3, vr4 + vaddh.u8.r vr2, vr3, vr4 + vaddh.u16.r vr2, vr3, vr4 + vaddh.u32.r vr2, vr3, vr4 + vaddh.s8.r vr2, vr3, vr4 + vaddh.s16.r vr2, vr3, vr4 + vaddh.s32.r vr2, vr3, vr4 + vadd.u8.s vr2, vr3, vr4 + vadd.u16.s vr2, vr3, vr4 + vadd.u32.s vr2, vr3, vr4 + vadd.s8.s vr2, vr3, vr4 + vadd.s16.s vr2, vr3, vr4 + vadd.s32.s vr2, vr3, vr4 + vsub.u8 vr2, vr3, vr4 + vsub.u16 vr2, vr3, vr4 + vsub.u32 vr2, vr3, vr4 + vsub.s8 vr2, vr3, vr4 + vsub.s16 vr2, vr3, vr4 + vsub.s32 vr2, vr3, vr4 + vsub.eu8 vr2, vr3, vr4 + vsub.eu16 vr2, vr3, vr4 + vsub.es8 vr2, vr3, vr4 + vsub.es16 vr2, vr3, vr4 + vsabs.u8 vr2, vr3, vr4 + vsabs.u16 vr2, vr3, vr4 + vsabs.u32 vr2, vr3, vr4 + vsabs.s8 vr2, vr3, vr4 + vsabs.s16 vr2, vr3, vr4 + vsabs.s32 vr2, vr3, vr4 + vsabs.eu8 vr2, vr3, vr4 + vsabs.eu16 vr2, vr3, vr4 + vsabs.es8 vr2, vr3, vr4 + vsabs.es16 vr2, vr3, vr4 + vsabsa.u8 vr2, vr3, vr4 + vsabsa.u16 vr2, vr3, vr4 + vsabsa.u32 vr2, vr3, vr4 + vsabsa.s8 vr2, vr3, vr4 + vsabsa.s16 vr2, vr3, vr4 + vsabsa.s32 vr2, vr3, vr4 + vsabsa.eu8 vr2, vr3, vr4 + vsabsa.eu16 vr2, vr3, vr4 + vsabsa.es8 vr2, vr3, vr4 + vsabsa.es16 vr2, vr3, vr4 + vsub.xu16 vr2, vr3, vr4 + vsub.xu32 vr2, vr3, vr4 + vsub.xs16 vr2, vr3, vr4 + vsub.xs32 vr2, vr3, vr4 + vsubh.u8 vr2, vr3, vr4 + vsubh.u16 vr2, vr3, vr4 + vsubh.u32 vr2, vr3, vr4 + vsubh.s8 vr2, vr3, vr4 + vsubh.s16 vr2, vr3, vr4 + vsubh.s32 vr2, vr3, vr4 + vsubh.u8.r vr2, vr3, vr4 + vsubh.u16.r vr2, vr3, vr4 + vsubh.u32.r vr2, vr3, vr4 + vsubh.s8.r vr2, vr3, vr4 + vsubh.s16.r vr2, vr3, vr4 + vsubh.s32.r vr2, vr3, vr4 + vsub.u8.s vr2, vr3, vr4 + vsub.u16.s vr2, vr3, vr4 + vsub.u32.s vr2, vr3, vr4 + vsub.s8.s vr2, vr3, vr4 + vsub.s16.s vr2, vr3, vr4 + vsub.s32.s vr2, vr3, vr4 + vmul.u8 vr2, vr3, vr4 + vmul.u16 vr2, vr3, vr4 + vmul.u32 vr2, vr3, vr4 + vmul.s8 vr2, vr3, vr4 + vmul.s16 vr2, vr3, vr4 + vmul.s32 vr2, vr3, vr4 + vmul.eu8 vr2, vr3, vr4 + vmul.eu16 vr2, vr3, vr4 + vmul.es8 vr2, vr3, vr4 + vmul.es16 vr2, vr3, vr4 + vmula.u8 vr2, vr3, vr4 + vmula.u16 vr2, vr3, vr4 + vmula.u32 vr2, vr3, vr4 + vmula.s8 vr2, vr3, vr4 + vmula.s16 vr2, vr3, vr4 + vmula.s32 vr2, vr3, vr4 + vmula.eu8 vr2, vr3, vr4 + vmula.eu16 vr2, vr3, vr4 + vmula.eu32 vr2, vr3, vr4 + vmula.es8 vr2, vr3, vr4 + vmula.es16 vr2, vr3, vr4 + vmula.es32 vr2, vr3, vr4 + vmuls.u8 vr2, vr3, vr4 + vmuls.u16 vr2, vr3, vr4 + vmuls.u32 vr2, vr3, vr4 + vmuls.s8 vr2, vr3, vr4 + vmuls.s16 vr2, vr3, vr4 + vmuls.s32 vr2, vr3, vr4 + vmuls.eu8 vr2, vr3, vr4 + vmuls.eu16 vr2, vr3, vr4 + vmuls.es8 vr2, vr3, vr4 + vmuls.es16 vr2, vr3, vr4 + vshr.u8 vr2, vr3, vr4 + vshr.u16 vr2, vr3, vr4 + vshr.u32 vr2, vr3, vr4 + vshr.s8 vr2, vr3, vr4 + vshr.s16 vr2, vr3, vr4 + vshr.s32 vr2, vr3, vr4 + vshr.u8.r vr2, vr3, vr4 + vshr.u16.r vr2, vr3, vr4 + vshr.u32.r vr2, vr3, vr4 + vshr.s8.r vr2, vr3, vr4 + vshr.s16.r vr2, vr3, vr4 + vshr.s32.r vr2, vr3, vr4 + vshl.u8 vr2, vr3, vr4 + vshl.u16 vr2, vr3, vr4 + vshl.u32 vr2, vr3, vr4 + vshl.s8 vr2, vr3, vr4 + vshl.s16 vr2, vr3, vr4 + vshl.s32 vr2, vr3, vr4 + vshl.u8.s vr2, vr3, vr4 + vshl.u16.s vr2, vr3, vr4 + vshl.u32.s vr2, vr3, vr4 + vshl.s8.s vr2, vr3, vr4 + vshl.s16.s vr2, vr3, vr4 + vshl.s32.s vr2, vr3, vr4 + vcmphs.u8 vr2, vr3, vr4 + vcmphs.u16 vr2, vr3, vr4 + vcmphs.u32 vr2, vr3, vr4 + vcmphs.s8 vr2, vr3, vr4 + vcmphs.s16 vr2, vr3, vr4 + vcmphs.s32 vr2, vr3, vr4 + vcmplt.u8 vr2, vr3, vr4 + vcmplt.u16 vr2, vr3, vr4 + vcmplt.u32 vr2, vr3, vr4 + vcmplt.s8 vr2, vr3, vr4 + vcmplt.s16 vr2, vr3, vr4 + vcmplt.s32 vr2, vr3, vr4 + vcmpne.u8 vr2, vr3, vr4 + vcmpne.u16 vr2, vr3, vr4 + vcmpne.u32 vr2, vr3, vr4 + vcmpne.s8 vr2, vr3, vr4 + vcmpne.s16 vr2, vr3, vr4 + vcmpne.s32 vr2, vr3, vr4 + vmax.u8 vr2, vr3, vr4 + vmax.u16 vr2, vr3, vr4 + vmax.u32 vr2, vr3, vr4 + vmax.s8 vr2, vr3, vr4 + vmax.s16 vr2, vr3, vr4 + vmax.s32 vr2, vr3, vr4 + vmin.u8 vr2, vr3, vr4 + vmin.u16 vr2, vr3, vr4 + vmin.u32 vr2, vr3, vr4 + vmin.s8 vr2, vr3, vr4 + vmin.s16 vr2, vr3, vr4 + vmin.s32 vr2, vr3, vr4 + vcmax.u8 vr2, vr3, vr4 + vcmax.u16 vr2, vr3, vr4 + vcmax.u32 vr2, vr3, vr4 + vcmax.s8 vr2, vr3, vr4 + vcmax.s16 vr2, vr3, vr4 + vcmax.s32 vr2, vr3, vr4 + vcmin.u8 vr2, vr3, vr4 + vcmin.u16 vr2, vr3, vr4 + vcmin.u32 vr2, vr3, vr4 + vcmin.s8 vr2, vr3, vr4 + vcmin.s16 vr2, vr3, vr4 + vcmin.s32 vr2, vr3, vr4 + vand.8 vr2, vr3, vr4 + vand.16 vr2, vr3, vr4 + vand.32 vr2, vr3, vr4 + vandn.8 vr2, vr3, vr4 + vandn.16 vr2, vr3, vr4 + vandn.32 vr2, vr3, vr4 + vor.8 vr2, vr3, vr4 + vor.16 vr2, vr3, vr4 + vor.32 vr2, vr3, vr4 + vnor.8 vr2, vr3, vr4 + vnor.16 vr2, vr3, vr4 + vnor.32 vr2, vr3, vr4 + vxor.8 vr2, vr3, vr4 + vxor.16 vr2, vr3, vr4 + vxor.32 vr2, vr3, vr4 + vtst.8 vr2, vr3, vr4 + vtst.16 vr2, vr3, vr4 + vtst.32 vr2, vr3, vr4 + vbpermz.8 vr2, vr3, vr4 + vbpermz.16 vr2, vr3, vr4 + vbpermz.32 vr2, vr3, vr4 + vbperm.8 vr2, vr3, vr4 + vbperm.16 vr2, vr3, vr4 + vbperm.32 vr2, vr3, vr4 + vdch.8 vr2, vr3, vr4 + vdch.16 vr2, vr3, vr4 + vdch.32 vr2, vr3, vr4 + vdcl.8 vr2, vr3, vr4 + vdcl.16 vr2, vr3, vr4 + vdcl.32 vr2, vr3, vr4 + vich.8 vr2, vr3, vr4 + vich.16 vr2, vr3, vr4 + vich.32 vr2, vr3, vr4 + vicl.8 vr2, vr3, vr4 + vicl.16 vr2, vr3, vr4 + vicl.32 vr2, vr3, vr4 diff --git a/gas/testsuite/gas/csky/cskyv2_all.d b/gas/testsuite/gas/csky/cskyv2_all.d new file mode 100644 index 0000000..b17a5e7 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_all.d @@ -0,0 +1,325 @@ +# name: csky - all +#as: -mcpu=ck810 -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*0000\s*bkpt +\s*[0-9a-f]*:\s*3316\s*movi\s*r3,\s*22 +\s*[0-9a-f]*:\s*ea100016\s*movi\s*r16,\s*22 +\s*[0-9a-f]*:\s*ea03012c\s*movi\s*r3,\s*300 +\s*[0-9a-f]*:\s*c4104834\s*lsli\s*r20,\s*r16,\s*0 +\s*[0-9a-f]*:\s*c6824848\s*lsri\s*r8,\s*r2,\s*20 +\s*[0-9a-f]*:\s*5227\s*asri\s*r1,\s*r2,\s*7 +\s*[0-9a-f]*:\s*6049\s*addc\s*r1,\s*r2 +\s*[0-9a-f]*:\s*c4310051\s*addc\s*r17,\s*r17,\s*r1 +\s*[0-9a-f]*:\s*c4620041\s*addc\s*r1,\s*r2,\s*r3 +\s*[0-9a-f]*:\s*6049\s*addc\s*r1,\s*r2 +\s*[0-9a-f]*:\s*c6210041\s*addc\s*r1,\s*r1,\s*r17 +\s*[0-9a-f]*:\s*c7d20052\s*addc\s*r18,\s*r18,\s*r30 +\s*[0-9a-f]*:\s*604b\s*subc\s*r1,\s*r2 +\s*[0-9a-f]*:\s*c4310111\s*subc\s*r17,\s*r17,\s*r1 +\s*[0-9a-f]*:\s*c4620101\s*subc\s*r1,\s*r2,\s*r3 +\s*[0-9a-f]*:\s*c4220101\s*subc\s*r1,\s*r2,\s*r1 +\s*[0-9a-f]*:\s*c6210101\s*subc\s*r1,\s*r1,\s*r17 +\s*[0-9a-f]*:\s*c7d20112\s*subc\s*r18,\s*r18,\s*r30 +\s*[0-9a-f]*:\s*650c\s*cmphs\s*r3,\s*r4 +\s*[0-9a-f]*:\s*650d\s*cmplt\s*r3,\s*r4 +\s*[0-9a-f]*:\s*650e\s*cmpne\s*r3,\s*r4 +\s*[0-9a-f]*:\s*64c3\s*mvcv\s*r3 +\s*[0-9a-f]*:\s*c4000610\s*mvcv\s*r16 +\s*[0-9a-f]*:\s*6848\s*and\s*r1,\s*r2 +\s*[0-9a-f]*:\s*6849\s*andn\s*r1,\s*r2 +\s*[0-9a-f]*:\s*690e\s*tst\s*r3,\s*r4 +\s*[0-9a-f]*:\s*c4902080\s*tst\s*r16,\s*r4 +\s*[0-9a-f]*:\s*680f\s*tstnbz\s*r3 +\s*[0-9a-f]*:\s*c4102100\s*tstnbz\s*r16 +\s*[0-9a-f]*:\s*c6f22432\s*or\s*r18,\s*r18,\s*r23 +\s*[0-9a-f]*:\s*6c49\s*xor\s*r1,\s*r2 +\s*[0-9a-f]*:\s*6c4a\s*nor\s*r1,\s*r2 +\s*[0-9a-f]*:\s*6c8f\s*mov\s*r2,\s*r3 +\s*[0-9a-f]*:\s*7808\s*jmp\s*r2 +\s*[0-9a-f]*:\s*e8d00000\s*jmp\s*r16 +\s*[0-9a-f]*:\s*7bc9\s*jsr\s*r2 +\s*[0-9a-f]*:\s*e8f00000\s*jsr\s*r16 +\s*[0-9a-f]*:\s*783c\s*rts +\s*[0-9a-f]*:\s*e8cf0000\s*rts +\s*[0-9a-f]*:\s*6c03\s*mov\s*r0, \s*r0 +\s*[0-9a-f]*:\s*c4364036\s*lsl\s*r22,\s*r22,\s*r1 +\s*[0-9a-f]*:\s*c4224041\s*lsr\s*r1,\s*r2,\s*r1 +\s*[0-9a-f]*:\s*704a\s*asr\s*r1,\s*r2 +\s*[0-9a-f]*:\s*c6014101\s*rotl\s*r1,\s*r1,\s*r16 +\s*[0-9a-f]*:\s*748c\s*zextb\s*r2,\s*r3 +\s*[0-9a-f]*:\s*748d\s*zexth\s*r2,\s*r3 +\s*[0-9a-f]*:\s*748e\s*sextb\s*r2,\s*r3 +\s*[0-9a-f]*:\s*748f\s*sexth\s*r2,\s*r3 +\s*[0-9a-f]*:\s*788e\s*revb\s*r2,\s*r3 +\s*[0-9a-f]*:\s*788f\s*revh\s*r2,\s*r3 +\s*[0-9a-f]*:\s*c4036090\s*revb\s*r16,\s*r3 +\s*[0-9a-f]*:\s*c4106102\s*revh\s*r2,\s*r16 +\s*[0-9a-f]*:\s*c6218421\s*mult\s*r1,\s*r1,\s*r17 +\s*[0-9a-f]*:\s*7d1c\s*mult\s*r4,\s*r7 +\s*[0-9a-f]*:\s*c6479027\s*mulsh\s*r7,\s*r7,\s*r18 +\s*[0-9a-f]*:\s*7ca1\s*mulsh\s*r2,\s*r8 +\s*[0-9a-f]*:\s*c43e943e\s*mulsw\s*r30,\s*r30,\s*r1 +\s*[0-9a-f]*:\s*c4419421\s*mulsw\s*r1,\s*r1,\s*r2 +\s*[0-9a-f]*:\s*8344\s*ld.b\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*8b42\s*ld.h\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*9841\s*ld.w\s*r2,\s*\(sp,\s*0x4\) +\s*[0-9a-f]*:\s*a344\s*st.b\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*ab42\s*st.h\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*b841\s*st.w\s*r2,\s*\(sp,\s*0x4\) +\s*[0-9a-f]*:\s*d9030004\s*ld.b\s*r8,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*d8481002\s*ld.h\s*r2,\s*\(r8,\s*0x4\) +\s*[0-9a-f]*:\s*9841\s*ld.w\s*r2,\s*\(sp,\s*0x4\) +\s*[0-9a-f]*:\s*dc480004\s*st.b\s*r2,\s*\(r8,\s*0x4\) +\s*[0-9a-f]*:\s*dc481002\s*st.h\s*r2,\s*\(r8,\s*0x4\) +\s*[0-9a-f]*:\s*dd0e2001\s*st.w\s*r8,\s*\(sp,\s*0x4\) +\s*[0-9a-f]*:\s*d8434003\s*ld.bs\s*r2,\s*\(r3,\s*0x3\) +\s*[0-9a-f]*:\s*d8433001\s*ld.d\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*dc433001\s*st.d\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*dc437001\s*stex.w\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*d8437001\s*ldex.w\s*r2,\s*\(r3,\s*0x4\) +\s*[0-9a-f]*:\s*140c\s*addi\s*sp,\s*sp,\s*48 +\s*[0-9a-f]*:\s*1b01\s*addi\s*r3,\s*sp,\s*4 +\s*[0-9a-f]*:\s*2113\s*addi\s*r1,\s*20 +\s*[0-9a-f]*:\s*2113\s*addi\s*r1,\s*20 +\s*[0-9a-f]*:\s*e6b50013\s*addi\s*r21,\s*r21,\s*20 +\s*[0-9a-f]*:\s*e42101ff\s*addi\s*r1,\s*r1,\s*512 +\s*[0-9a-f]*:\s*5c42\s*addi\s*r2,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e5040000\s*addi\s*r8,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e4240008\s*addi\s*r1,\s*r4,\s*9 +\s*[0-9a-f]*:\s*cc3c0008\s*addi\s*r1,\s*r28,\s*9 +\s*[0-9a-f]*:\s*e46e0000\s*addi\s*r3,\s*sp,\s*1 +\s*[0-9a-f]*:\s*e46e03ff\s*addi\s*r3,\s*sp,\s*1024 +\s*[0-9a-f]*:\s*e5ce0032\s*addi\s*sp,\s*sp,\s*51 +\s*[0-9a-f]*:\s*e5ce01ff\s*addi\s*sp,\s*sp,\s*512 +\s*[0-9a-f]*:\s*2113\s*addi\s*r1,\s*20 +\s*[0-9a-f]*:\s*5c42\s*addi\s*r2,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e4440000\s*addi\s*r2,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e46e03ff\s*addi\s*r3,\s*sp,\s*1024 +\s*[0-9a-f]*:\s*e5ce0032\s*addi\s*sp,\s*sp,\s*51 +\s*[0-9a-f]*:\s*142c\s*subi\s*sp,\s*sp,\s*48 +\s*[0-9a-f]*:\s*2913\s*subi\s*r1,\s*20 +\s*[0-9a-f]*:\s*2913\s*subi\s*r1,\s*20 +\s*[0-9a-f]*:\s*e6b51013\s*subi\s*r21,\s*r21,\s*20 +\s*[0-9a-f]*:\s*e42111ff\s*subi\s*r1,\s*r1,\s*512 +\s*[0-9a-f]*:\s*5c43\s*subi\s*r2,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e5041000\s*subi\s*r8,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e4241008\s*subi\s*r1,\s*r4,\s*9 +\s*[0-9a-f]*:\s*e43c1008\s*subi\s*r1,\s*r28,\s*9 +\s*[0-9a-f]*:\s*e5ce1032\s*subi\s*sp,\s*sp,\s*51 +\s*[0-9a-f]*:\s*e5ce11ff\s*subi\s*sp,\s*sp,\s*512 +\s*[0-9a-f]*:\s*2913\s*subi\s*r1,\s*20 +\s*[0-9a-f]*:\s*5c43\s*subi\s*r2,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e4441000\s*subi\s*r2,\s*r4,\s*1 +\s*[0-9a-f]*:\s*e5ce1032\s*subi\s*sp,\s*sp,\s*51 +\s*[0-9a-f]*:\s*60c2\s*subu\s*r3,\s*r0 +\s*[0-9a-f]*:\s*6202\s*subu\s*r8,\s*r0 +\s*[0-9a-f]*:\s*c4030089\s*subu\s*r9,\s*r3,\s*r0 +\s*[0-9a-f]*:\s*60c2\s*subu\s*r3,\s*r0 +\s*[0-9a-f]*:\s*6242\s*subu\s*r9,\s*r0 +\s*[0-9a-f]*:\s*c417008d\s*subu\s*r13,\s*r23,\s*r0 +\s*[0-9a-f]*:\s*60c0\s*addu\s*r3,\s*r0 +\s*[0-9a-f]*:\s*6200\s*addu\s*r8,\s*r0 +\s*[0-9a-f]*:\s*c4030029\s*addu\s*r9,\s*r3,\s*r0 +\s*[0-9a-f]*:\s*60c0\s*addu\s*r3,\s*r0 +\s*[0-9a-f]*:\s*6240\s*addu\s*r9,\s*r0 +\s*[0-9a-f]*:\s*c417002d\s*addu\s*r13,\s*r23,\s*r0 +\s*[0-9a-f]*:\s*3921\s*cmplti\s*r1,\s*2 +\s*[0-9a-f]*:\s*eb320003\s*cmplti\s*r18,\s*4 +\s*[0-9a-f]*:\s*670c\s*cmphs\s*r3,\s*r12 +\s*[0-9a-f]*:\s*c6c30420\s*cmphs\s*r3,\s*r22 +\s*[0-9a-f]*:\s*6489\s*cmplt\s*r2,\s*r2 +\s*[0-9a-f]*:\s*c7220440\s*cmplt\s*r2,\s*r25 +\s*[0-9a-f]*:\s*3d20\s*cmplti\s*r5,\s*1 +\s*[0-9a-f]*:\s*eb390000\s*cmplti\s*r25,\s*1 +\s*[0-9a-f]*:\s*3a40\s*cmpnei\s*r2,\s*0 +\s*[0-9a-f]*:\s*eb580000\s*cmpnei\s*r24,\s*0 +\s*[0-9a-f]*:\s*c7e42880\s*btsti\s*r4,\s*31 +\s*[0-9a-f]*:\s*c7f82880\s*btsti\s*r24,\s*31 +\s*[0-9a-f]*:\s*6400\s*cmphs\s*r0,\s*r0 +\s*[0-9a-f]*:\s*6402\s*cmpne\s*r0,\s*r0 +\s*[0-9a-f]*:\s*6089\s*addc\s*r2,\s*r2 +\s*[0-9a-f]*:\s*c6100050\s*addc\s*r16,\s*r16,\s*r16 +\s*[0-9a-f]*:\s*c0a01820\s*sce\s*5 +\s*[0-9a-f]*:\s*c0002820\s*trap\s*2 +\s*[0-9a-f]*:\s*c4402c20\s*clrf\s*r2 +\s*[0-9a-f]*:\s*c7402c40\s*clrt\s*r26 +\s*[0-9a-f]*:\s*c0004020\s*rte +\s*[0-9a-f]*:\s*c0004420\s*rfi +\s*[0-9a-f]*:\s*c0004820\s*stop +\s*[0-9a-f]*:\s*c0004c20\s*wait +\s*[0-9a-f]*:\s*c0005020\s*doze +\s*[0-9a-f]*:\s*c0005420\s*we +\s*[0-9a-f]*:\s*c0005820\s*se +\s*[0-9a-f]*:\s*c4000517\s*mvc\s*r23 +\s*[0-9a-f]*:\s*c4009823\s*mfhis\s*r3 +\s*[0-9a-f]*:\s*c4009891\s*mflos\s*r17 +\s*[0-9a-f]*:\s*c4009a00\s*mvtc +\s*[0-9a-f]*:\s*c4009c32\s*mfhi\s*r18 +\s*[0-9a-f]*:\s*c4139c40\s*mthi\s*r19 +\s*[0-9a-f]*:\s*c4009c83\s*mflo\s*r3 +\s*[0-9a-f]*:\s*c4089d00\s*mtlo\s*r8 +\s*[0-9a-f]*:\s*c0000420\s*sync\s*0 +\s*[0-9a-f]*:\s*c0200420\s*sync\s*1 +\s*[0-9a-f]*:\s*c2800420\s*sync\s*20 +\s*[0-9a-f]*:\s*c0601c20\s*idly\s*4 +\s*[0-9a-f]*:\s*c0601c20\s*idly\s*4 +\s*[0-9a-f]*:\s*c0601c20\s*idly\s*4 +\s*[0-9a-f]*:\s*c0801c20\s*idly\s*5 +\s*[0-9a-f]*:\s*c3e01c20\s*idly\s*32 +\s*[0-9a-f]*:\s*fc2044d2\s*cprc\s*\<1,\s*1234\> +\s*[0-9a-f]*:\s*fc2084d2\s*cpop\s*\<1,\s*1234\> +\s*[0-9a-f]*:\s*fc3414d2\s*cpwgr\s*r20,\s*\<1,\s*1234\> +\s*[0-9a-f]*:\s*fc3434d2\s*cpwcr\s*r20,\s*\<1,\s*1234\> +\s*[0-9a-f]*:\s*fc3404d2\s*cprgr\s*r20,\s*\<1,\s*1234\> +\s*[0-9a-f]*:\s*fc3424d2\s*cprcr\s*r20,\s*\<1,\s*1234\> +\s*[0-9a-f]*:\s*320c\s*movi\s*r2,\s*12 +\s*[0-9a-f]*:\s*ea220010\s*movih\s*r2,\s*16 +\s*[0-9a-f]*:\s*ea021000\s*movi\s*r2,\s*4096 +\s*[0-9a-f]*:\s*ea220001\s*movih\s*r2,\s*1 +\s*[0-9a-f]*:\s*1491\s*pop\s*r4, r15 +\s*[0-9a-f]*:\s*1498\s*pop\s*r4-r11, r15 +\s*[0-9a-f]*:\s*ebc00100\s*pop\s*r28 +\s*[0-9a-f]*:\s*ebc00020\s*pop\s*r16 +\s*[0-9a-f]*:\s*14d1\s*push\s*r4, r15 +\s*[0-9a-f]*:\s*14d8\s*push\s*r4-r11, r15 +\s*[0-9a-f]*:\s*ebe00100\s*push\s*r28 +\s*[0-9a-f]*:\s*ebe00020\s*push\s*r16 +\s*[0-9a-f]*:\s*c4625c42\s*ins\s*r3,\s*r2,\s*4,\s*2 +\s*[0-9a-f]*:\s*c4425483\s*zext\s*r3,\s*r2,\s*4,\s*2 +\s*[0-9a-f]*:\s*c4425883\s*sext\s*r3,\s*r2,\s*4,\s*2 +\s*[0-9a-f]*:\s*e4622002\s*andi\s*r3,\s*r2,\s*2 +\s*[0-9a-f]*:\s*e4623002\s*andni\s*r3,\s*r2,\s* 2 +\s*[0-9a-f]*:\s*e462400c\s*xori\s*r3,\s*r2,\s* 12 +\s*[0-9a-f]*:\s*d0621c22\s*ldm\s*r3-r5,\s*\(r2\) +\s*[0-9a-f]*:\s*d4621c22\s*stm\s*r3-r5,\s*\(r2\) +\s*[0-9a-f]*:\s*c4410083\s*subu\s*r3,\s*r1,\s*r2 +\s*[0-9a-f]*:\s*d4220023\s*str\.b\s*r3,\s*\(r2,\s*r1\s*<<\s*0\) +\s*[0-9a-f]*:\s*d4220423\s*str\.h\s*r3,\s*\(r2,\s*r1\s*<<\s*0\) +\s*[0-9a-f]*:\s*d4220823\s*str\.w\s*r3,\s*\(r2,\s*r1\s*<<\s*0\) +\s*[0-9a-f]*:\s*d0220043\s*ldr\.b\s*r3,\s*\(r2,\s*r1\s*<<\s*1\) +\s*[0-9a-f]*:\s*d0220443\s*ldr\.h\s*r3,\s*\(r2,\s*r1\s*<<\s*1\) +\s*[0-9a-f]*:\s*d0220843\s*ldr\.w\s*r3,\s*\(r2,\s*r1\s*<<\s*1\) +\s*[0-9a-f]*:\s*d0621022\s*ldr\.bs\s*r2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*d0621042\s*ldr\.bs\s*r2,\s*\(r2,\s*r3\s*<<\s*1\) +\s*[0-9a-f]*:\s*d0621082\s*ldr\.bs\s*r2,\s*\(r2,\s*r3\s*<<\s*2\) +\s*[0-9a-f]*:\s*d0621102\s*ldr\.bs\s*r2,\s*\(r2,\s*r3\s*<<\s*3\) +\s*[0-9a-f]*:\s*d0621422\s*ldr\.hs\s*r2,\s*\(r2,\s*r3\s*<<\s*0\) +\s*[0-9a-f]*:\s*d0621442\s*ldr\.hs\s*r2,\s*\(r2,\s*r3\s*<<\s*1\) +\s*[0-9a-f]*:\s*d0621482\s*ldr\.hs\s*r2,\s*\(r2,\s*r3\s*<<\s*2\) +\s*[0-9a-f]*:\s*d0621502\s*ldr\.hs\s*r2,\s*\(r2,\s*r3\s*<<\s*3\) +\s*[0-9a-f]*:\s*c4424d03\s*xsr\s*r3,\s*r2,\s*3 +\s*[0-9a-f]*:\s*c4424c83\s*asrc\s*r3,\s*r2,\s*3 +\s*[0-9a-f]*:\s*c4424c43\s*lsrc\s*r3,\s*r2,\s*3 +\s*[0-9a-f]*:\s*c4424c23\s*lslc\s*r3,\s*r2,\s*3 +\s*[0-9a-f]*:\s*c4824903\s*rotli\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4014901\s*rotli\s*r1,\s*r1,\s*0 +\s*[0-9a-f]*:\s*c7e14901\s*rotli\s*r1,\s*r1,\s*31 +\s*[0-9a-f]*:\s*c7304901\s*rotli\s*r1,\s*r16,\s*25 +\s*[0-9a-f]*:\s*c7e14901\s*rotli\s*r1,\s*r1,\s*31 +\s*[0-9a-f]*:\s*c4014901\s*rotli\s*r1,\s*r1,\s*0 +\s*[0-9a-f]*:\s*c4f04901\s*rotli\s*r1,\s*r16,\s*7 +\s*[0-9a-f]*:\s*c4821083\s*decne\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4821043\s*declt\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4821023\s*decgt\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4620d04\s*dect\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4620c84\s*decf\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4620c24\s*incf\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*c4620c44\s*inct\s*r3,\s*r2,\s*4 +\s*[0-9a-f]*:\s*d0831c23\s*ldm\s*r4-r7,\s*\(r3\) +\s*[0-9a-f]*:\s*d4831c23\s*stm\s*r4-r7,\s*\(r3\) +\s*[0-9a-f]*:\s*c1007020\s*psrclr\s*ee +\s*[0-9a-f]*:\s*c0607020\s*psrclr\s*fe,\s*af +\s*[0-9a-f]*:\s*c1607420\s*psrset\s*ee,\s*fe,\s*af +\s*[0-9a-f]*:\s*c1e07420\s*psrset\s*ee,\s*ie,\s*fe,\s*af +\s*[0-9a-f]*:\s*c4140211\s*abs\s*r17,\s*r20 +\s*[0-9a-f]*:\s*c4155043\s*bgenr\s*r3,\s*r21 +\s*[0-9a-f]*:\s*c4016217\s*brev\s*r23,\s*r1 +\s*[0-9a-f]*:\s*c4037025\s*xtrb0\s*r5,\s*r3 +\s*[0-9a-f]*:\s*c4097043\s*xtrb1\s*r3,\s*r9 +\s*[0-9a-f]*:\s*c4147090\s*xtrb2\s*r16,\s*r20 +\s*[0-9a-f]*:\s*c418710b\s*xtrb3\s*r11,\s*r24 +\s*[0-9a-f]*:\s*c4157c22\s*ff0\s*r2,\s*r21 +\s*[0-9a-f]*:\s*c4017c52\s*ff1\s*r18,\s*r1 +\s*[0-9a-f]*:\s*c0026423\s*mtcr\s*r2,\s*cr<3,\s*0> +\s*[0-9a-f]*:\s*c0026424\s*mtcr\s*r2,\s*cr<4,\s*0> +\s*[0-9a-f]*:\s*c0026421\s*mtcr\s*r2,\s*cr<1,\s*0> +\s*[0-9a-f]*:\s*c0006022\s*mfcr\s*r2,\s*cr<0,\s*0> +\s*[0-9a-f]*:\s*c0006022\s*mfcr\s*r2,\s*cr<0,\s*0> +\s*[0-9a-f]*:\s*c0006022\s*mfcr\s*r2,\s*cr<0,\s*0> +\s*[0-9a-f]*:\s*6c8a\s*nor\s*r2,\s*r2 +\s*[0-9a-f]*:\s*c6102490\s*nor\s*r16,\s*r16,\s*r16 +\s*[0-9a-f]*:\s*c6102482\s*nor\s*r2,\s*r16,\s*r16 +\s*[0-9a-f]*:\s*6c8a\s*nor\s*r2,\s*r2 +\s*[0-9a-f]*:\s*c4830822\s*ixh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*c4830842\s*ixw\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*c4830882\s*ixd\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*c4838042\s*divs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*c4838022\s*divu\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*c4220c20\s*incf\s*r1,\s*r2,\s*0 +\s*[0-9a-f]*:\s*c6e20c40\s*inct\s*r23,\s*r2,\s*0 +\s*[0-9a-f]*:\s*ea0800ff\s*movi\s*r8,\s*255 +\s*[0-9a-f]*:\s*c7e05021\s*bmaski\s*r1,\s*32 +\s*[0-9a-f]*:\s*310f\s*movi\s*r1,\s*15 +\s*[0-9a-f]*:\s*c6005021\s*bmaski\s*r1,\s*17 +\s*[0-9a-f]*:\s*ea15ffff\s*movi\s*r21,\s*65535 +\s*[0-9a-f]*:\s*ea0dffff\s*movi\s*r13,\s*65535 +\s*[0-9a-f]*:\s*c7c05021\s*bmaski\s*r1,\s*31 +\s*[0-9a-f]*:\s*c7e05021\s*bmaski\s*r1,\s*32 +\s*[0-9a-f]*:\s*d8026002\s*pldr\s*\(r2,\s*0x8\) +\s*[0-9a-f]*:\s*dc026002\s*pldw\s*\(r2,\s*0x8\) +\s*[0-9a-f]*:\s*6c46\s*nor\s*r1,\s*r1 +\s*[0-9a-f]*:\s*2100\s*addi\s*r1,\s*1 +\s*[0-9a-f]*:\s*6c8a\s*nor\s*r2,\s*r2 +\s*[0-9a-f]*:\s*2217\s*addi\s*r2,\s*24 +\s*[0-9a-f]*:\s*c4034c83\s*asrc\s*r3,\s*r3,\s*1 +\s*[0-9a-f]*:\s*c4840c21\s*incf\s*r4,\s*r4,\s*1 +\s*[0-9a-f]*:\s*c5ad0c41\s*inct\s*r13,\s*r13,\s*1 +\s*[0-9a-f]*:\s*c6100c81\s*decf\s*r16,\s*r16,\s*1 +\s*[0-9a-f]*:\s*c4311031\s*decgt\s*r17,\s*r17,\s*1 +\s*[0-9a-f]*:\s*c4331053\s*declt\s*r19,\s*r19,\s*1 +\s*[0-9a-f]*:\s*c4341094\s*decne\s*r20,\s*r20,\s*1 +\s*[0-9a-f]*:\s*c7ff0d01\s*dect\s*r31,\s*r31,\s*1 +\s*[0-9a-f]*:\s*c40b4c2b\s*lslc\s*r11,\s*r11,\s*1 +\s*[0-9a-f]*:\s*c4194c59\s*lsrc\s*r25,\s*r25,\s*1 +\s*[0-9a-f]*:\s*c40c4d0c\s*xsr\s*r12,\s*r12,\s*1 +\s*[0-9a-f]*:\s*c4778057\s*divs\s*r23,\s*r23,\s*r3 +\s*[0-9a-f]*:\s*c7c18021\s*divu\s*r1,\s*r1,\s*r30 +\s*[0-9a-f]*:\s*c40d020d\s*abs\s*r13,\s*r13 +\s*[0-9a-f]*:\s*c40c620c\s*brev\s*r12,\s*r12 +\s*[0-9a-f]*:\s*c4087c48\s*ff1\s*r8,\s*r8 +\s*[0-9a-f]*:\s*6c46\s*nor\s*r1,\s*r1 +\s*[0-9a-f]*:\s*c6312491\s*nor\s*r17,\s*r17,\s*r17 +\s*[0-9a-f]*:\s*7488\s*zextb\s*r2,\s*r2 +\s*[0-9a-f]*:\s*c41355f3\s*zexth\s*r19,\s*r19 +\s*[0-9a-f]*:\s*c41d58fd\s*sextb\s*r29,\s*r29 +\s*[0-9a-f]*:\s*76ef\s*sexth\s*r11,\s*r11 +\s*[0-9a-f]*:\s*c6210821\s*ixh\s*r1,\s*r1,\s*r17 +\s*[0-9a-f]*:\s*c4370857\s*ixw\s*r23,\s*r23,\s*r1 +#... +\s*[0-9a-f]*:\s*c4630083\s*subu\s*r3,\s*r3,\s*r3 +\s*[0-9a-f]*:\s*c63f0091\s*subu\s*r17,\s*r31,\s*r17 +\s*[0-9a-f]*:\s*492c\s*lsri\s*r1,\s*r1,\s*12 +\s*[0-9a-f]*:\s*c4554835\s*lsli\s*r21,\s*r21,\s*2 +\s*[0-9a-f]*:\s*c4419421\s*mulsw\s*r1,\s*r1,\s*r2 +\s*[0-9a-f]*:\s*e463207b\s*andi\s*r3,\s*r3,\s*123 +\s*[0-9a-f]*:\s*c5684908\s*rotli\s*r8,\s*r8,\s*11 +\s*[0-9a-f]*:\s*e860fdf8\s*bt\s*0x0.* +\s*[0-9a-f]*:\s*e840fdf6\s*bf\s*0x0.* +\s*[0-9a-f]*:\s*e860fdf4\s*bt\s*0x0.* +\s*[0-9a-f]*:\s*e840fdf2\s*bf\s*0x0.* +\s*[0-9a-f]*:\s*e800fdf0\s*br\s*0x0.* +\s*[0-9a-f]*:\s*e800fdee\s*br\s*0x0.* +\s*[0-9a-f]*:\s*e3fffdec\s*bsr\s*0x0.* +\s*[0-9a-f]*:\s*cc500000\s*srs\.b\s*r2,\s*\[0x0\].* +\s*[0-9a-f]*:\s*cc400000\s*lrs\.b\s*r2,\s*\[0x0\].* +\s*[0-9a-f]*:\s*cc540000\s*srs\.h\s*r2,\s*\[0x0\].* +\s*[0-9a-f]*:\s*cc440000\s*lrs\.h\s*r2,\s*\[0x0\].* +\s*[0-9a-f]*:\s*cc580000\s*srs\.w\s*r2,\s*\[0x0\].* +\s*[0-9a-f]*:\s*cc480000\s*lrs\.w\s*r2,\s*\[0x0\].* +\s*[0-9a-f]*:\s*ec430002\s*ori\s*r2,\s*r3,\s*2 +\s*[0-9a-f]*:\s*ec43000a\s*ori\s*r2,\s*r3,\s*10 diff --git a/gas/testsuite/gas/csky/cskyv2_all.s b/gas/testsuite/gas/csky/cskyv2_all.s new file mode 100644 index 0000000..3826b06 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_all.s @@ -0,0 +1,316 @@ +.text +all: + bkpt + movi r3, 22 + movi r16, 22 + movi r3, 300 + lsli r20, r16, 0 + lsri r8, r2, 20 + asri r1, r2, 7 + addc r1, r2 + addc r17, r1 + addc r1, r2, r3 + addc r1, r2, r1 + addc r1, r17 + addc r18, r18, r30 + subc r1, r2 + subc r17, r1 + subc r1, r2, r3 + subc r1, r2, r1 + subc r1, r17 + subc r18, r18, r30 + cmphs r3, r4 + cmplt r3, r4 + cmpne r3, r4 + mvcv r3 + mvcv r16 + and r1, r2 + andn r1, r2 + tst r3, r4 + tst r16, r4 + tstnbz r3 + tstnbz r16 + or r18, r23 + xor r1, r1, r2 + nor r1, r2, r1 + mov r2, r3 + jmp r2 + jmp r16 + jsr r2 + jsr r16 + rts + rts32 + nop + lsl r22, r1 + lsr r1, r2, r1 + asr r1, r1, r2 + rotl r1, r1, r16 + zextb r2, r3 + zexth r2, r3 + sextb r2, r3 + sexth r2, r3 + revb r2, r3 + revh r2, r3 + revb r16, r3 + revh r2, r16 + mult r1, r1, r17 + mul r4, r7 + mulsh r7, r18 + muls.h r2, r8 + mulsw r30, r30, r1 + mulsw r1, r2 + ld.b r2, (r3, 4) + ld.h r2, (r3, 4) + ld.w r2, (r14, 4) + st.b r2, (r3, 4) + st.h r2, (r3, 4) + st.w r2, (r14, 4) + ld.b r8, (r3, 4) + ld.h r2, (r8, 4) + ld.w r2, (r14, 4) + st.b r2, (r8, 4) + st.h r2, (r8, 4) + st.w r8, (r14, 4) + ld.bs r2, (r3, 3) + ld.d r2, (r3, 4) + st.d r2, (r3, 4) + stex.w r2, (r3, 4) + ldex.w r2, (r3, 4) + addi sp, sp, 0x30 + addi r3, sp, 0x4 + addi r1, 20 + addi r1, r1, 20 + addi r21, 20 + addi r1, 0x200 + addi r2, r4, 1 + addi r8, r4, 1 + addi r1, r4, 9 + addi r1, r28, 9 + addi r3, sp, 0x1 + addi r3, sp, 0x400 + addi sp, sp, 0x33 + addi sp, sp, 0x200 + addi16 r1, 20 + addi16 r2, r4, 1 + addi32 r2, r4, 1 + addi32 r3, sp, 0x400 + addi32 sp, sp, 0x33 + subi sp, sp, 0x30 + subi r1, 20 + subi r1, r1, 20 + subi r21, 20 + subi r1, 0x200 + subi r2, r4, 1 + subi r8, r4, 1 + subi r1, r4, 9 + subi r1, r28, 9 + subi sp, sp, 0x33 + subi sp, sp, 0x200 + subi16 r1, 20 + subi16 r2, r4, 1 + subi32 r2, r4, 1 + subi32 sp, sp, 0x33 + sub r3, r0 + sub r8, r0 + sub r9, r3, r0 + sub r3, r3, r0 + sub r9, r9, r0 + sub r13, r23, r0 + add r3, r0 + add r8, r0 + add r9, r3, r0 + add r3, r3, r0 + add r9, r9, r0 + add r13, r23, r0 + cmplei r1, 1 + cmplei r18, 3 + cmpls r12, r3 + cmpls r22, r3 + cmpgt r2, r2 + cmpgt r25, r2 + tstle r5 + tstle r25 + tstne r2 + tstne r24 + tstlt r4 + tstlt r24 + setc + clrc + rotlc r2, 1 + rotlc r16, 1 + sce 5 + trap 2 + clrf r2 + clrt r26 + rte + rfi + stop + wait + doze + we + se + mvc r23 + mfhis r3 + mflos r17 + mvtc + mfhi r18 + mthi r19 + mflo r3 + mtlo r8 + sync 0 + sync 1 + sync 20 + idly 0 + idly 2 + idly 4 + idly 5 + idly 32 + cprc <1, 1234> + cpop <1, 1234> + cpwgr r20, <1, 1234> + cpwcr r20, <1, 1234> + cprgr r20, <1, 1234> + cprcr r20, <1, 1234> + movi r2, 12 + movih r2, 16 + bgeni r2, 12 + bgeni r2, 16 + pop r4, r15 + pop r15, r4-r11 + pop r28 + pop r16 + push r4, r15 + push r15, r4-r11 + push r28 + push r16 + ins r3, r2, 4, 2 + zext r3, r2, 4, 2 + sext r3, r2, 4, 2 + andi r3, r2, 2 + andni r3, r2, 2 + xori r3, r2, 12 + ldm r3-r5, (r2) + stm r3-r5, (r2) + rsub r3, r2, r1 + str.b r3, (r2, r1 << 0) + str.h r3, (r2, r1 << 0) + str.w r3, (r2, r1 << 0) + ldr.b r3, (r2, r1 << 1) + ldr.h r3, (r2, r1 << 1) + ldr.w r3, (r2, r1 << 1) + ldr.bs r2, (r2, r3 << 0) + ldr.bs r2, (r2, r3 << 1) + ldr.bs r2, (r2, r3 << 2) + ldr.bs r2, (r2, r3 << 3) + ldr.hs r2, (r2, r3 << 0) + ldr.hs r2, (r2, r3 << 1) + ldr.hs r2, (r2, r3 << 2) + ldr.hs r2, (r2, r3 << 3) + xsr r3, r2, 3 + asrc r3, r2, 3 + lsrc r3, r2, 3 + lslc r3, r2, 3 + rotli r3, r2, 4 + rotri r1, 32 + rotri r1, 1 + rotri r1, r16, 7 + rotli r1, 31 + rotli r1, 0 + rotli r1, r16, 7 + decne r3, r2, 4 + declt r3, r2, 4 + decgt r3, r2, 4 + dect r3, r2, 4 + decf r3, r2, 4 + incf r3, r2, 4 + inct r3, r2, 4 + ldq r4-r7, (r3) + stq r4-r7, (r3) + psrclr ee + psrclr af, fe + psrset ee, fe, af + psrset ie, ee, fe, af + abs r17, r20 + bgenr r3, r21 + brev r23, r1 + xtrb0 r5, r3 + xtrb1 r3, r9 + xtrb2 r16, r20 + xtrb3 r11, r24 + ff0 r2, r21 + ff1 r18, r1 + mtcr r2, cr<3, 0> + mtcr r2, cr4 + mtcr r2, vbr + mfcr r2, cr<0, 0> + mfcr r2, cr0 + mfcr r2, psr + not r2 + not r16 + not r2, r16 + not r2, r2 + ixh r2, r3, r4 + ixw r2, r3, r4 + ixd r2, r3, r4 + divs r2, r3, r4 + divu r2, r3, r4 + movf r1, r2 + movt r23, r2 + bmaski r8, 8 + bmaski r1, 0 + bmaski r1, 4 + bmaski r1, 17 + bmaski r21, 16 + bmaski r13, 16 + bmaski r1, 31 + bmaski r1, 32 + pldr (r2, 0x8) + pldw (r2, 0x8) + neg r1 + rsubi r2, 23 + asrc r3 + incf r4 + inct r13 + decf r16 + decgt r17 + declt r19 + decne r20 + dect r31 + lslc r11 + lsrc r25 + xsr r12 + divs r23, r3 + divu r1, r30 + abs r13 + brev r12 + ff1 r8 + not r1 + not r17 + zextb r2 + zexth r19 + sextb r29 + sexth r11 + ixh r1, r17 + ixw r23, r1 + rsub r3, r3 + rsub r17, r31 + lsri r1, 12 + lsli r21, 2 + mulsw r1, r2 + andi r3, 123 + rori r8, 21 + bt all + bf all + jbt all + jbf all + br all + jbr all + bsr all + srs.b r2, [all] + lrs.b r2, [all] + srs.h r2, [all] + lrs.h r2, [all] + srs.w r2, [all] + lrs.w r2, [all] + ori r2, r3, 2 + ori r2, r3, 10 diff --git a/gas/testsuite/gas/csky/cskyv2_dsp.d b/gas/testsuite/gas/csky/cskyv2_dsp.d new file mode 100644 index 0000000..f2e3d33 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_dsp.d @@ -0,0 +1,18 @@ +# name: csky - all +#as: -mcpu=ck810e -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*c4818820\s*mulu\s*r1,\s*r4 +\s*[0-9a-f]*:\s*c6ec8840\s*mulua\s*r12,\s*r23 +\s*[0-9a-f]*:\s*c46f8880\s*mulus\s*r15,\s*r3 +\s*[0-9a-f]*:\s*c4418c20\s*muls\s*r1,\s*r2 +\s*[0-9a-f]*:\s*c4428c40\s*mulsa\s*r2,\s*r2 +\s*[0-9a-f]*:\s*c4638c80\s*mulss\s*r3,\s*r3 +\s*[0-9a-f]*:\s*c6689040\s*mulsha\s*r8,\s*r19 +\s*[0-9a-f]*:\s*c4319080\s*mulshs\s*r17,\s*r1 +\s*[0-9a-f]*:\s*c6ec9440\s*mulswa\s*r12,\s*r23 +\s*[0-9a-f]*:\s*c4a39480\s*mulsws\s*r3,\s*r5 diff --git a/gas/testsuite/gas/csky/cskyv2_dsp.s b/gas/testsuite/gas/csky/cskyv2_dsp.s new file mode 100644 index 0000000..9c0666c --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_dsp.s @@ -0,0 +1,11 @@ +.text + mulu r1, r4 + mulua r12, r23 + mulus r15, r3 + muls r1, r2 + mulsa r2, r2 + mulss r3, r3 + mulsha r8, r19 + mulshs r17, r1 + mulswa r12, r23 + mulsws r3, r5 diff --git a/gas/testsuite/gas/csky/cskyv2_elrw.d b/gas/testsuite/gas/csky/cskyv2_elrw.d new file mode 100644 index 0000000..5a52d5a --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_elrw.d @@ -0,0 +1,10 @@ +# name: cskyv2 - elrw +#as: -mcpu=ck801 -melrw +#objdump: -D + +.*: +file format .*csky.* +#... +\s*[0-9a-f]*:\s*024e\s*lrw\s*r2,\s*0x1234.* +#... +\s*[0-9a-f]*:\s*c0004020\s*rte +\s*[0-9a-f]*:\s*00001234\s*\.long\s*0x00001234 diff --git a/gas/testsuite/gas/csky/cskyv2_elrw.s b/gas/testsuite/gas/csky/cskyv2_elrw.s new file mode 100644 index 0000000..07f8898 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_elrw.s @@ -0,0 +1,6 @@ +.text + lrw r2, 0x1234 +.rept 351 + nop +.endr + rte diff --git a/gas/testsuite/gas/csky/cskyv2_float.d b/gas/testsuite/gas/csky/cskyv2_float.d new file mode 100644 index 0000000..f1039c9 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_float.d @@ -0,0 +1,59 @@ +# name: csky - all +#as: -mcpu=ck810f -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*f4000100\s*fcmpzhss\s*fr0 +\s*[0-9a-f]*:\s*f4010120\s*fcmpzlss\s*fr1 +\s*[0-9a-f]*:\s*f4050140\s*fcmpznes\s*fr5 +\s*[0-9a-f]*:\s*f4080160\s*fcmpzuos\s*fr8 +\s*[0-9a-f]*:\s*f40a0900\s*fcmpzhsd\s*fr10 +\s*[0-9a-f]*:\s*f40d0920\s*fcmpzlsd\s*fr13 +\s*[0-9a-f]*:\s*f40e0940\s*fcmpzned\s*fr14 +\s*[0-9a-f]*:\s*f40f0960\s*fcmpzuod\s*fr15 +\s*[0-9a-f]*:\s*f409008c\s*fmovs\s*fr12,\s*fr9 +\s*[0-9a-f]*:\s*f40000c1\s*fabss\s*fr1,\s*fr0 +\s*[0-9a-f]*:\s*f40100e2\s*fnegs\s*fr2,\s*fr1 +\s*[0-9a-f]*:\s*f4470180\s*fcmphss\s*fr7,\s*fr2 +\s*[0-9a-f]*:\s*f46601a0\s*fcmplts\s*fr6,\s*fr3 +\s*[0-9a-f]*:\s*f48201c0\s*fcmpnes\s*fr2,\s*fr4 +\s*[0-9a-f]*:\s*f4ac01e0\s*fcmpuos\s*fr12,\s*fr5 +\s*[0-9a-f]*:\s*f406032b\s*frecips\s*fr11,\s*fr6 +\s*[0-9a-f]*:\s*f407034a\s*fsqrts\s*fr10,\s*fr7 +\s*[0-9a-f]*:\s*f4080889\s*fmovd\s*fr9,\s*fr8 +\s*[0-9a-f]*:\s*f40908cd\s*fabsd\s*fr13,\s*fr9 +\s*[0-9a-f]*:\s*f40a08ee\s*fnegd\s*fr14,\s*fr10 +\s*[0-9a-f]*:\s*f56f0980\s*fcmphsd\s*fr15,\s*fr11 +\s*[0-9a-f]*:\s*f58009a0\s*fcmpltd\s*fr0,\s*fr12 +\s*[0-9a-f]*:\s*f5a309c0\s*fcmpned\s*fr3,\s*fr13 +\s*[0-9a-f]*:\s*f5c409e0\s*fcmpuod\s*fr4,\s*fr14 +\s*[0-9a-f]*:\s*f40f0b25\s*frecipd\s*fr5,\s*fr15 +\s*[0-9a-f]*:\s*f4080b48\s*fsqrtd\s*fr8,\s*fr8 +\s*[0-9a-f]*:\s*f4031081\s*fmovm\s*fr1,\s*fr3 +\s*[0-9a-f]*:\s*f40d10c3\s*fabsm\s*fr3,\s*fr13 +\s*[0-9a-f]*:\s*f40210ef\s*fnegm\s*fr15,\s*fr2 +\s*[0-9a-f]*:\s*f402180f\s*fstosi.rn\s*fr15,\s*fr2 +\s*[0-9a-f]*:\s*f402182e\s*fstosi.rz\s*fr14,\s*fr2 +\s*[0-9a-f]*:\s*f40f184d\s*fstosi.rpi\s*fr13,\s*fr15 +\s*[0-9a-f]*:\s*f40e186c\s*fstosi.rni\s*fr12,\s*fr14 +\s*[0-9a-f]*:\s*f40d188b\s*fstoui.rn\s*fr11,\s*fr13 +\s*[0-9a-f]*:\s*f40c18aa\s*fstoui.rz\s*fr10,\s*fr12 +\s*[0-9a-f]*:\s*f40b18c9\s*fstoui.rpi\s*fr9,\s*fr11 +\s*[0-9a-f]*:\s*f40a18e8\s*fstoui.rni\s*fr8,\s*fr10 +\s*[0-9a-f]*:\s*f4091907\s*fdtosi.rn\s*fr7,\s*fr9 +\s*[0-9a-f]*:\s*f4081926\s*fdtosi.rz\s*fr6,\s*fr8 +\s*[0-9a-f]*:\s*f4071945\s*fdtosi.rpi\s*fr5,\s*fr7 +\s*[0-9a-f]*:\s*f4061964\s*fdtosi.rni\s*fr4,\s*fr6 +\s*[0-9a-f]*:\s*f4051983\s*fdtoui.rn\s*fr3,\s*fr5 +\s*[0-9a-f]*:\s*f40419a2\s*fdtoui.rz\s*fr2,\s*fr4 +\s*[0-9a-f]*:\s*f40319c1\s*fdtoui.rpi\s*fr1,\s*fr3 +\s*[0-9a-f]*:\s*f40219e0\s*fdtoui.rni\s*fr0,\s*fr2 +\s*[0-9a-f]*:\s*f4011a0e\s*fsitos\s*fr14,\s*fr1 +\s*[0-9a-f]*:\s*f4001a2c\s*fuitos\s*fr12,\s*fr0 +\s*[0-9a-f]*:\s*f4021a8d\s*fsitod\s*fr13,\s*fr2 +\s*[0-9a-f]*:\s*f4041aab\s*fuitod\s*fr11,\s*fr4 +\s*[0-9a-f]*:\s*f4081ac2\s*fdtos\s*fr2,\s*fr8 +\s*[0-9a-f]*:\s*f40b1ae5\s*fstod\s*fr5,\s*fr11 diff --git a/gas/testsuite/gas/csky/cskyv2_float.s b/gas/testsuite/gas/csky/cskyv2_float.s new file mode 100644 index 0000000..ff73391 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_float.s @@ -0,0 +1,52 @@ +.text +fcmpzhss vr0 +fcmpzlss vr1 +fcmpznes vr5 +fcmpzuos vr8 +fcmpzhsd vr10 +fcmpzlsd vr13 +fcmpzned vr14 +fcmpzuod vr15 +fmovs vr12, fr9 +fabss vr1, fr0 +fnegs vr2, fr1 +fcmphss vr7, fr2 +fcmplts vr6, fr3 +fcmpnes vr2, fr4 +fcmpuos vr12, fr5 +frecips vr11, fr6 +fsqrts vr10, fr7 +fmovd vr9, fr8 +fabsd vr13, fr9 +fnegd vr14, fr10 +fcmphsd vr15, fr11 +fcmpltd vr0, fr12 +fcmpned vr3, fr13 +fcmpuod vr4, fr14 +frecipd vr5, fr15 +fsqrtd vr8, fr8 +fmovm vr1, fr3 +fabsm vr3, fr13 +fnegm vr15, fr2 +fstosi.rn vr15, vr2 +fstosi.rz vr14, vr2 +fstosi.rpi vr13, vr15 +fstosi.rni vr12, vr14 +fstoui.rn vr11, fr13 +fstoui.rz vr10, fr12 +fstoui.rpi vr9, fr11 +fstoui.rni fr8, vr10 +fdtosi.rn fr7, vr9 +fdtosi.rz fr6, vr8 +fdtosi.rpi fr5, vr7 +fdtosi.rni fr4, vr6 +fdtoui.rn fr3, fr5 +fdtoui.rz fr2, fr4 +fdtoui.rpi fr1, fr3 +fdtoui.rni fr0, fr2 +fsitos vr14, vr1 +fuitos fr12, vr0 +fsitod fr13, fr2 +fuitod fr11, fr4 +fdtos vr2, vr8 +fstod fr5, vr11 diff --git a/gas/testsuite/gas/csky/cskyv2_lrw.d b/gas/testsuite/gas/csky/cskyv2_lrw.d new file mode 100644 index 0000000..5b8ea04 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_lrw.d @@ -0,0 +1,19 @@ +# name: cskyv2 - lrw +#as: -mcpu=ck810 -W +#objdump: -D + +.*: +file format .*csky.* +#... +00000000 <LRW>: +\s*[0-9a-f]*:\s*ea020100\s*movi\s*r2,\s*256 +\s*[0-9a-f]*:\s*ea021000\s*movi\s*r2,\s*4096 +\s*[0-9a-f]*:\s*ea220001\s*movih\s*r2,\s*1 +\s*[0-9a-f]*:\s*1042\s*lrw\s*r2,\s*0x12341234.* +\s*[0-9a-f]*:\s*1043\s*lrw\s*r2,\s*0x0.* +\s*[0-9a-f]*:\s*1041\s*lrw\s*r2,\s*0x12341234.* +#... +00000012 <L1>: +\s*[0-9a-f]*:\s*6c8f\s*mov\s*r2,\s*r3 +\s*[0-9a-f]*:\s*12341234\s*\.long\s*0x12341234 +\s*[0-9a-f]*:\s*00000000\s*\.long\s*0x00000000 +#... diff --git a/gas/testsuite/gas/csky/cskyv2_lrw.s b/gas/testsuite/gas/csky/cskyv2_lrw.s new file mode 100644 index 0000000..0ff6070 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_lrw.s @@ -0,0 +1,11 @@ +.text +LRW: + lrw r2, 0x100 + lrw16 r2, 0x1000 + lrw32 r2, 0x10000 + lrw r2, 0x12341234 + lrw r2, L1 + lrw r2, [L1] + +L1: + mov r2, r3 diff --git a/gas/testsuite/gas/csky/cskyv2_mnolrw1.d b/gas/testsuite/gas/csky/cskyv2_mnolrw1.d new file mode 100644 index 0000000..8714677 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_mnolrw1.d @@ -0,0 +1,23 @@ +# name: cskyv2 - nolrw +#as: -mcpu=ck810 -mnolrw -W +#objdump: -D + +.*: +file format .*csky.* +#... +00000000 <LRW>: +\s*[0-9a-f]*:\s*ea220000\s*movih\s*r2,\s*0 +\s*[0-9a-f]*:\s*ec420100\s*ori\s*r2,\s*r2,\s*256 +\s*[0-9a-f]*:\s*ea220000\s*movih\s*r2,\s*0 +\s*[0-9a-f]*:\s*ec421000\s*ori\s*r2,\s*r2,\s*4096 +\s*[0-9a-f]*:\s*ea220001\s*movih\s*r2,\s*1 +\s*[0-9a-f]*:\s*ec420000\s*ori\s*r2,\s*r2,\s*0 +\s*[0-9a-f]*:\s*ea221234\s*movih\s*r2,\s*4660 +\s*[0-9a-f]*:\s*ec421234\s*ori\s*r2,\s*r2,\s*4660 +\s*[0-9a-f]*:\s*ea220000\s*movih\s*r2,\s*0 +\s*[0-9a-f]*:\s*ec420000\s*ori\s*r2,\s*r2,\s*0 +\s*[0-9a-f]*:\s*ea220000\s*movih\s*r2,\s*0 +\s*[0-9a-f]*:\s*ec420000\s*ori\s*r2,\s*r2,\s*0 +#... +00000030 <L1>: +\s*[0-9a-f]*:\s*6c8f\s*mov\s*r2,\s*r3 +#... diff --git a/gas/testsuite/gas/csky/cskyv2_mnolrw1.s b/gas/testsuite/gas/csky/cskyv2_mnolrw1.s new file mode 100644 index 0000000..0ff6070 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_mnolrw1.s @@ -0,0 +1,11 @@ +.text +LRW: + lrw r2, 0x100 + lrw16 r2, 0x1000 + lrw32 r2, 0x10000 + lrw r2, 0x12341234 + lrw r2, L1 + lrw r2, [L1] + +L1: + mov r2, r3 diff --git a/gas/testsuite/gas/csky/cskyv2_mnolrw2.d b/gas/testsuite/gas/csky/cskyv2_mnolrw2.d new file mode 100644 index 0000000..2232e76 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_mnolrw2.d @@ -0,0 +1,12 @@ +# name: csky - nolrw +#as: -mcpu=ck810 -mnolrw -W +#readelf: -r --wide + + +Relocation section '.rela.text\' at offset .* contains 4 entries: +#... +00000020.*R_CKCORE_ADDR_HI16\s*00000030\s*L1\s*\+\s*0 +00000024.*R_CKCORE_ADDR_LO16\s*00000030\s*L1\s*\+\s*0 +00000028.*R_CKCORE_ADDR_HI16\s*00000030\s*L1\s*\+\s*0 +0000002c.*R_CKCORE_ADDR_LO16\s*00000030\s*L1\s*\+\s*0 +#pass diff --git a/gas/testsuite/gas/csky/cskyv2_mnolrw2.s b/gas/testsuite/gas/csky/cskyv2_mnolrw2.s new file mode 100644 index 0000000..0ff6070 --- /dev/null +++ b/gas/testsuite/gas/csky/cskyv2_mnolrw2.s @@ -0,0 +1,11 @@ +.text +LRW: + lrw r2, 0x100 + lrw16 r2, 0x1000 + lrw32 r2, 0x10000 + lrw r2, 0x12341234 + lrw r2, L1 + lrw r2, [L1] + +L1: + mov r2, r3 diff --git a/gas/testsuite/gas/csky/enhance_dsp.d b/gas/testsuite/gas/csky/enhance_dsp.d new file mode 100644 index 0000000..4317038 --- /dev/null +++ b/gas/testsuite/gas/csky/enhance_dsp.d @@ -0,0 +1,217 @@ +#name: csky - enhancedsp +#as: -mcpu=ck803er1 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*d0038002\s*ldbi.b\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d0038402\s*ldbi.h\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d0038802\s*ldbi.w\s*r2,\s*\(r3\) +#... +\s*[0-9a-f]*:\s*e9c20ffa\s*bloop\s*r2,\s*0x0,\s*0xc.* +\s*[0-9a-f]*:\s*d0038c02\s*pldbi.d\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d0039002\s*ldbi.hs\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d0039402\s*ldbi.bs\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d4038002\s*stbi.b\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d4038402\s*stbi.h\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d4038802\s*stbi.w\s*r2,\s*\(r3\) +\s*[0-9a-f]*:\s*d083a002\s*ldbir.b\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d083a402\s*ldbir.h\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d083a802\s*ldbir.w\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d083ac02\s*pldbir.d\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d083b402\s*ldbir.hs\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d083b002\s*ldbir.bs\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d483a002\s*stbir.b\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d483a402\s*stbir.h\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*d483a802\s*stbir.w\s*r2,\s*\(r3\),\s*r4 +\s*[0-9a-f]*:\s*f883c042\s*padd\.8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c002\s*padd\.16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c142\s*padd\.u8\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c1c2\s*padd\.s8\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c102\s*padd\.u16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c182\s*padd\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c122\s*add\.u32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c1a2\s*add\.s32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c442\s*psub\.8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c402\s*psub\.16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c542\s*psub\.u8\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c5c2\s*psub\.s8\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c502\s*psub\.u16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c582\s*psub\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c522\s*sub\.u32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c5a2\s*sub\.s32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c242\s*paddh\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c2c2\s*paddh\.s8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c202\s*paddh\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c282\s*paddh\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c222\s*addh\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c2a2\s*addh\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c642\s*psubh\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c6c2\s*psubh\.s8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c602\s*psubh\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c682\s*psubh\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c622\s*subh\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c6a2\s*subh\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c862\s*pasx\.16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cc62\s*psax\.16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c9e2\s*pasx\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c962\s*pasx\.u16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cd62\s*psax\.u16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cde2\s*psax\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ca62\s*pasxh\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cae2\s*pasxh\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ce62\s*psaxh\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cee2\s*psaxh\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c842\s*pcmpne\.8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c802\s*pcmpne\.16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c942\s*pcmphs\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c982\s*pcmphs\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c902\s*pcmphs\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883c9c2\s*pcmphs\.s8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ca42\s*pcmplt\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ca02\s*pcmplt\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ca82\s*pcmplt\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ca02\s*pcmplt\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cc42\s*pmax\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883ccc2\s*pmax\.s8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cc02\s*pmax\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cc82\s*pmax\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cc22\s*max\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cca2\s*max\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cd42\s*pmin\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cdc2\s*pmin\.s8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cd02\s*pmin\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cd82\s*pmin\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cd22\s*min\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883cda2\s*min\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8229083\s*sel\s*r3,\s*r2,\s*r1,\s*r4 +\s*[0-9a-f]*:\s*f883e042\s*psabsa\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883e142\s*psabsaa\.u8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883e262\s*divul\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883e2e2\s*divsl\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883e4c2\s*mulaca\.s8\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f9e3d1a2\s*asri\.s32\.r\s*r2,\s*r3,\s*16 +\s*[0-9a-f]*:\s*f8c3d1e2\s*asr\.s32\.r\s*r2,\s*r3,\s*r6 +\s*[0-9a-f]*:\s*f9e3d322\s*lsri\.u32\.r\s*r2,\s*r3,\s*16 +\s*[0-9a-f]*:\s*f8c3d362\s*lsr\.u32\.r\s*r2,\s*r3,\s*r6 +\s*[0-9a-f]*:\s*f9e3d522\s*lsli\.u32\.s\s*r2,\s*r3,\s*16 +\s*[0-9a-f]*:\s*f9e3d5a2\s*lsli\.s32\.s\s*r2,\s*r3,\s*16 +\s*[0-9a-f]*:\s*f8c3d562\s*lsl\.u32\.s\s*r2,\s*r3,\s*r6 +\s*[0-9a-f]*:\s*f8c3d5e2\s*lsl\.s32\.s\s*r2,\s*r3,\s*r6 +\s*[0-9a-f]*:\s*f8e3d082\s*pasri\.s16\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*f8c3d0c2\s*pasr\.s16\s*r2,\s*r3,\s*r6 +\s*[0-9a-f]*:\s*f8e3d182\s*pasri\.s16\.r\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*f8c3d1c2\s*pasr\.s16\.r\s*r2,\s*r3,\s*r6 +\s*[0-9a-f]*:\s*f8e3d202\s*plsri\.u16\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*f883d242\s*plsr\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8e3d302\s*plsri\.u16\.r\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*f883d342\s*plsr\.u16\.r\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8e3d402\s*plsli\.u16\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*fa03d442\s*plsl\.u16\s*r2,\s*r3,\s*r16 +\s*[0-9a-f]*:\s*f8e3d502\s*plsli\.u16\.s\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*f8e3d582\s*plsli\.s16\.s\s*r2,\s*r3,\s*8 +\s*[0-9a-f]*:\s*f883d542\s*plsl\.u16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883d5c2\s*plsl\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8a3a482\s*pkg\s*r2,\s*r3,\s*4,\s*r5,\s*3 +\s*[0-9a-f]*:\s*f8839882\s*dexti\s*r2,\s*r3,\s*r4,\s*4 +\s*[0-9a-f]*:\s*f8839ca2\s*dext\s*r2,\s*r3,\s*r4,\s*r5 +\s*[0-9a-f]*:\s*f883d842\s*pkgll\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883d862\s*pkghh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f803d902\s*pext\.u8\.e\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803d982\s*pext\.s8\.e\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803d922\s*pextx\.u8\.e\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803d9a2\s*pextx\.s8\.e\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f883da02\s*narl\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883da22\s*narh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883da42\s*narlx\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883da62\s*narhx\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*fa03db02\s*clipi\.u32\s*r2,\s*r3,\s*16 +\s*[0-9a-f]*:\s*f9e3db82\s*clipi\.s32\s*r2,\s*r3,\s*16 +\s*[0-9a-f]*:\s*f883db22\s*clip\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883dba2\s*clip\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f863dbc2\s*pclipi\.s16\s*r2,\s*r3,\s*4 +\s*[0-9a-f]*:\s*f883db42\s*pclipi\.u16\s*r2,\s*r3,\s*4 +\s*[0-9a-f]*:\s*f883dbe2\s*pclip\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f883db62\s*pclip\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f803dc82\s*pabs\.s8\.s\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803dca2\s*pabs\.s16\.s\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803dcc2\s*abs\.s32\.s\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803dd82\s*pneg\.s8\.s\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803dda2\s*pneg\.s16\.s\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803ddc2\s*neg\.s32\.s\s*r2,\s*r3 +\s*[0-9a-f]*:\s*f803de62\s*dup\.8\s*r2,\s*r3,\s*3 +\s*[0-9a-f]*:\s*f803df02\s*dup\.16\s*r2,\s*r3,\s*0 +\s*[0-9a-f]*:\s*f8838002\s*mul\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838202\s*mul\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838082\s*mula\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838282\s*mula\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88380c2\s*muls\.u32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88382c2\s*muls\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838182\s*mula\.u32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838382\s*mula\.s32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88381c2\s*muls\.u32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88383c2\s*muls\.s32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838402\s*mul\.s32\.h\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838602\s*mul\.s32\.rh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838502\s*rmul\.s32\.h\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838702\s*rmul\.s32\.rh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838582\s*mula\.s32\.hs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88385c2\s*muls\.s32\.hs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838782\s*mula\.s32\.rhs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88387c2\s*muls\.s32\.rhs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838802\s*mulxl\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838a02\s*mulxl\.s32\.r\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838c02\s*mulxh\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838e02\s*mulxh\.s32\.r\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838902\s*rmulxl\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838b02\s*rmulxl\.s32\.r\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838d02\s*rmulxh\.s32\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838f02\s*rmulxh\.s32\.r\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838982\s*mulaxl\.s32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838b82\s*mulaxl\.s32\.rs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838d82\s*mulaxh\.s32\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838f82\s*mulaxh\.s32\.rs\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838022\s*mulll\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838262\s*mulhh\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838222\s*mulhl\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838122\s*rmulll\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838362\s*rmulhh\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838322\s*rmulhl\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88381a2\s*mulall\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88383e2\s*mulahh\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88383a2\s*mulahl\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88380a2\s*mulall\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88382e2\s*mulahh\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88380e2\s*mulahl\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88384a2\s*pmul\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88384e2\s*pmulx\.u16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838422\s*pmul\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838462\s*pmulx\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838522\s*prmul\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838562\s*prmulx\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88385a2\s*prmul\.s16\.h\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88387a2\s*prmul\.s16\.rh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88385e2\s*prmulx\.s16\.h\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88387e2\s*prmulx\.s16\.rh\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838922\s*mulca\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838962\s*mulcax\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838a22\s*mulcs\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838a62\s*mulcsr\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838c22\s*mulcsx\.s16\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88389a2\s*mulaca\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88389e2\s*mulacax\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838ba2\s*mulacs\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838be2\s*mulacsr\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838da2\s*mulacsx\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838de2\s*mulsca\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838fa2\s*mulscax\.s16\.s\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88388a2\s*mulaca\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f88388e2\s*mulacax\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838aa2\s*mulacs\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838ae2\s*mulacsr\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838ca2\s*mulacsx\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838ce2\s*mulsca\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838ce2\s*mulsca\.s16\.e\s*r2,\s*r3,\s*r4 +\s*[0-9a-f]*:\s*f8838442\s*mula\.32\.l\s*r2,\s*r3,\s*r4 diff --git a/gas/testsuite/gas/csky/enhance_dsp.s b/gas/testsuite/gas/csky/enhance_dsp.s new file mode 100644 index 0000000..0491a53 --- /dev/null +++ b/gas/testsuite/gas/csky/enhance_dsp.s @@ -0,0 +1,219 @@ + +.text +hello: +.loop_start: + ldbi.b r2, (r3) + ldbi.h r2, (r3) + ldbi.w r2, (r3) +.loop_end: + bloop r2, .loop_start, .loop_end + pldbi.d r2, (r3) + ldbi.hs r2, (r3) + ldbi.bs r2, (r3) + stbi.b r2, (r3) + stbi.h r2, (r3) + stbi.w r2, (r3) + ldbir.b r2, (r3), r4 + ldbir.h r2, (r3), r4 + ldbir.w r2, (r3), r4 + pldbir.d r2, (r3), r4 + ldbir.hs r2, (r3), r4 + ldbir.bs r2, (r3), r4 + stbir.b r2, (r3), r4 + stbir.h r2, (r3), r4 + stbir.w r2, (r3), r4 + + padd.8 r2, r3, r4 + padd.16 r2, r3, r4 + padd.u8.s r2, r3, r4 + padd.s8.s r2, r3, r4 + padd.u16.s r2, r3, r4 + padd.s16.s r2, r3, r4 + add.u32.s r2, r3, r4 + add.s32.s r2, r3, r4 + psub.8 r2, r3, r4 + psub.16 r2, r3, r4 + psub.u8.s r2, r3, r4 + psub.s8.s r2, r3, r4 + psub.u16.s r2, r3, r4 + psub.s16.s r2, r3, r4 + sub.u32.s r2, r3, r4 + sub.s32.s r2, r3, r4 + paddh.u8 r2, r3, r4 + paddh.s8 r2, r3, r4 + paddh.u16 r2, r3, r4 + paddh.s16 r2, r3, r4 + addh.u32 r2, r3, r4 + addh.s32 r2, r3, r4 + psubh.u8 r2, r3, r4 + psubh.s8 r2, r3, r4 + psubh.u16 r2, r3, r4 + psubh.s16 r2, r3, r4 + subh.u32 r2, r3, r4 + subh.s32 r2, r3, r4 + + pasx.16 r2, r3, r4 + psax.16 r2, r3, r4 + pasx.s16.s r2, r3, r4 + pasx.u16.s r2, r3, r4 + psax.u16.s r2, r3, r4 + psax.s16.s r2, r3, r4 + pasxh.u16 r2, r3, r4 + pasxh.s16 r2, r3, r4 + psaxh.u16 r2, r3, r4 + psaxh.s16 r2, r3, r4 + pcmpne.8 r2, r3, r4 + pcmpne.16 r2, r3, r4 + pcmphs.u8 r2, r3, r4 + pcmphs.s16 r2, r3, r4 + pcmphs.u16 r2, r3, r4 + pcmphs.s8 r2, r3, r4 + pcmplt.u8 r2, r3, r4 + pcmplt.u16 r2, r3, r4 + pcmplt.s16 r2, r3, r4 + pcmplt.u16 r2, r3, r4 + pmax.u8 r2, r3, r4 + pmax.s8 r2, r3, r4 + pmax.u16 r2, r3, r4 + pmax.s16 r2, r3, r4 + max.u32 r2, r3, r4 + max.s32 r2, r3, r4 + pmin.u8 r2, r3, r4 + pmin.s8 r2, r3, r4 + pmin.u16 r2, r3, r4 + pmin.s16 r2, r3, r4 + min.u32 r2, r3, r4 + min.s32 r2, r3, r4 + sel r3, r2, r1, r4 + + psabsa.u8 r2, r3, r4 + psabsaa.u8 r2, r3, r4 + divul r2, r3, r4 + divsl r2, r3, r4 + mulaca.s8 r2, r3, r4 + + asri.s32.r r2, r3, 16 + asr.s32.r r2, r3, r6 + lsri.u32.r r2, r3, 16 + lsr.u32.r r2, r3, r6 + lsli.u32.s r2, r3, 16 + lsli.s32.s r2, r3, 16 + lsl.u32.s r2, r3, r6 + lsl.s32.s r2, r3, r6 + pasri.s16 r2, r3, 8 + pasr.s16 r2, r3, r6 + pasri.s16.r r2, r3, 8 + pasr.s16.r r2, r3, r6 + plsri.u16 r2, r3, 8 + plsr.u16 r2, r3, r4 + plsri.u16.r r2, r3, 8 + plsr.u16.r r2, r3, r4 + plsli.u16 r2, r3, 8 + plsl.u16 r2, r3, r16 + plsli.u16.s r2, r3, 8 + plsli.s16.s r2, r3, 8 + plsl.u16.s r2, r3, r4 + plsl.s16.s r2, r3, r4 + + pkg r2, r3, 4, r5, 3 + dexti r2, r3, r4, 4 + dext r2, r3, r4, r5 + pkgll r2, r3, r4 + pkghh r2, r3, r4 + pext.u8.e r2, r3 + pext.s8.e r2, r3 + pextx.u8.e r2, r3 + pextx.s8.e r2, r3 + narl r2, r3, r4 + narh r2, r3, r4 + narlx r2, r3, r4 + narhx r2, r3, r4 + clipi.u32 r2, r3, 16 + clipi.s32 r2, r3, 16 + clip.u32 r2, r3, r4 + clip.s32 r2, r3, r4 + pclipi.s16 r2, r3, 4 + pclipi.u16 r2, r3, 4 + pclip.s16 r2, r3, r4 + pclip.u16 r2, r3, r4 + pabs.s8.s r2, r3 + pabs.s16.s r2, r3 + abs.s32.s r2, r3 + pneg.s8.s r2, r3 + pneg.s16.s r2, r3 + neg.s32.s r2, r3 + dup.8 r2, r3, 3 + dup.16 r2, r3, 0 + + mul.u32 r2, r3, r4 + mul.s32 r2, r3, r4 + mula.u32 r2, r3, r4 + mula.s32 r2, r3, r4 + muls.u32 r2, r3, r4 + muls.s32 r2, r3, r4 + mula.u32.s r2, r3, r4 + mula.s32.s r2, r3, r4 + muls.u32.s r2, r3, r4 + muls.s32.s r2, r3, r4 + mul.s32.h r2, r3, r4 + mul.s32.rh r2, r3, r4 + rmul.s32.h r2, r3, r4 + rmul.s32.rh r2, r3, r4 + mula.s32.hs r2, r3, r4 + muls.s32.hs r2, r3, r4 + mula.s32.rhs r2, r3, r4 + muls.s32.rhs r2, r3, r4 + mulxl.s32 r2, r3, r4 + mulxl.s32.r r2, r3, r4 + mulxh.s32 r2, r3, r4 + mulxh.s32.r r2, r3, r4 + rmulxl.s32 r2, r3, r4 + rmulxl.s32.r r2, r3, r4 + rmulxh.s32 r2, r3, r4 + rmulxh.s32.r r2, r3, r4 + mulaxl.s32.s r2, r3, r4 + mulaxl.s32.rs r2, r3, r4 + mulaxh.s32.s r2, r3, r4 + mulaxh.s32.rs r2, r3, r4 + mulll.s16 r2, r3, r4 + mulhh.s16 r2, r3, r4 + mulhl.s16 r2, r3, r4 + rmulll.s16 r2, r3, r4 + rmulhh.s16 r2, r3, r4 + rmulhl.s16 r2, r3, r4 + mulall.s16.s r2, r3, r4 + mulahh.s16.s r2, r3, r4 + mulahl.s16.s r2, r3, r4 + mulall.s16.e r2, r3, r4 + mulahh.s16.e r2, r3, r4 + mulahl.s16.e r2, r3, r4 + pmul.u16 r2, r3, r4 + pmulx.u16 r2, r3, r4 + pmul.s16 r2, r3, r4 + pmulx.s16 r2, r3, r4 + prmul.s16 r2, r3, r4 + prmulx.s16 r2, r3, r4 + prmul.s16.h r2, r3, r4 + prmul.s16.rh r2, r3, r4 + prmulx.s16.h r2, r3, r4 + prmulx.s16.rh r2, r3, r4 + mulca.s16.s r2, r3, r4 + mulcax.s16.s r2, r3, r4 + mulcs.s16 r2, r3, r4 + mulcsr.s16 r2, r3, r4 + mulcsx.s16 r2, r3, r4 + mulaca.s16.s r2, r3, r4 + mulacax.s16.s r2, r3, r4 + mulacs.s16.s r2, r3, r4 + mulacsr.s16.s r2, r3, r4 + mulacsx.s16.s r2, r3, r4 + mulsca.s16.s r2, r3, r4 + mulscax.s16.s r2, r3, r4 + mulaca.s16.e r2, r3, r4 + mulacax.s16.e r2, r3, r4 + mulacs.s16.e r2, r3, r4 + mulacsr.s16.e r2, r3, r4 + mulacsx.s16.e r2, r3, r4 + mulsca.s16.e r2, r3, r4 + mulsca.s16.e r2, r3, r4 + mula.32.l r2, r3, r4 diff --git a/gas/testsuite/gas/csky/java.d b/gas/testsuite/gas/csky/java.d new file mode 100644 index 0000000..f433d52 --- /dev/null +++ b/gas/testsuite/gas/csky/java.d @@ -0,0 +1,12 @@ +# name: csky - java +#as: -mcpu=ck802j +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*14ac\s*bpop\.h\s*r3 +\s*[0-9a-f]:\s*14ae\s*bpop\.w\s*r3 +\s*[0-9a-f]:\s*14ec\s*bpush\.h\s*r3 +\s*[0-9a-f]:\s*14ee\s*bpush\.w\s*r3 diff --git a/gas/testsuite/gas/csky/java.s b/gas/testsuite/gas/csky/java.s new file mode 100644 index 0000000..c192750 --- /dev/null +++ b/gas/testsuite/gas/csky/java.s @@ -0,0 +1,6 @@ +.text +hello: + bpop.h r3 + bpop.w r3 + bpush.h r3 + bpush.w r3 diff --git a/gas/testsuite/gas/csky/jbsr.d b/gas/testsuite/gas/csky/jbsr.d new file mode 100644 index 0000000..c036910 --- /dev/null +++ b/gas/testsuite/gas/csky/jbsr.d @@ -0,0 +1,14 @@ +# name: jbsr - csky +#as: -mcpu=ck610 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*ffff\s*bsr\s*0x0.* +\s*[0-9a-f]*:\s*f7ff\s*br\s*0x2.* +\s*[0-9a-f]*:\s*f7ff\s*br\s*0x4.* +\s*[0-9a-f]*:\s*1200\s*\.short\s*0x1200.* +\s*[0-9a-f]*:\s*00000000\s*\.long\s*0x00000000.* +#... diff --git a/gas/testsuite/gas/csky/jbsr.s b/gas/testsuite/gas/csky/jbsr.s new file mode 100644 index 0000000..860431a --- /dev/null +++ b/gas/testsuite/gas/csky/jbsr.s @@ -0,0 +1,3 @@ +.text +hello: + jbsr hello diff --git a/gas/testsuite/gas/csky/jbt.d b/gas/testsuite/gas/csky/jbt.d new file mode 100644 index 0000000..098bdc2 --- /dev/null +++ b/gas/testsuite/gas/csky/jbt.d @@ -0,0 +1,16 @@ +# name: jbt - csky +#as: -mcpu=ck610 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*e7ff\s*bt\s*0x0.* +\s*[0-9a-f]*:\s*e804\s*bf\s*0xc.* +\s*[0-9a-f]*:\s*7001\s*jmpi\s*0x0.* +\s*[0-9a-f]*:\s*0000\s*bkpt\s* +\s*[0-9a-f]*:\s*0000\s*bkpt\s* +\s*[0-9a-f]*:\s*0000\s*bkpt\s* +\s*[0-9a-f]*:\s*1200\s*mov\s*r0,\s*r0 +#... diff --git a/gas/testsuite/gas/csky/jbt.s b/gas/testsuite/gas/csky/jbt.s new file mode 100644 index 0000000..10808df --- /dev/null +++ b/gas/testsuite/gas/csky/jbt.s @@ -0,0 +1,10 @@ +.text +hello: + jbt hello + jbt label +.rept 33*1024 + nop +.endr + +label: + nop diff --git a/gas/testsuite/gas/csky/jbt_pic.d b/gas/testsuite/gas/csky/jbt_pic.d new file mode 100644 index 0000000..932cd7d --- /dev/null +++ b/gas/testsuite/gas/csky/jbt_pic.d @@ -0,0 +1,23 @@ +# name: jbt - csky +#as: -mcpu=ck610 -fpic +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*e7ff\s*bt\s*0x0.* +\s*[0-9a-f]*:\s*e80b\s*bf\s*0x1a.* +\s*[0-9a-f]*:\s*2470\s*subi\s*r0,\s*r0,\s*8 +\s*[0-9a-f]*:\s*9f00\s*st.w\s*r15,\s*\(r0,\s*0x0\) +\s*[0-9a-f]*:\s*f800\s*bsr\s*0xa.* +\s*[0-9a-f]*:\s*7102\s*lrw\s*r1,\s*0x10810.* +\s*[0-9a-f]*:\s*1cf1\s*addu\s*r1,\s*r1,\s*r15 +\s*[0-9a-f]*:\s*8f00\s*ld.w\s*r15,\s*\(r0,\s*0x0\) +\s*[0-9a-f]*:\s*2070\s*addi\s*r0,\s*r0,\s*8 +\s*[0-9a-f]*:\s*00c1\s*jmp\s*r1 +\s*[0-9a-f]*:\s*0810\s*cprgr\s*r0,\s*cpr1 +\s*[0-9a-f]*:\s*0001\s*sync +\s*[0-9a-f]*:\s*0000\s*bkpt +\s*[0-9a-f]*:\s*1200\s*mov\s*r0,\s*r0 +#... diff --git a/gas/testsuite/gas/csky/jbt_pic.s b/gas/testsuite/gas/csky/jbt_pic.s new file mode 100644 index 0000000..10808df --- /dev/null +++ b/gas/testsuite/gas/csky/jbt_pic.s @@ -0,0 +1,10 @@ +.text +hello: + jbt hello + jbt label +.rept 33*1024 + nop +.endr + +label: + nop diff --git a/gas/testsuite/gas/csky/jmpi1.d b/gas/testsuite/gas/csky/jmpi1.d new file mode 100644 index 0000000..3cd1211 --- /dev/null +++ b/gas/testsuite/gas/csky/jmpi1.d @@ -0,0 +1,16 @@ +# name: jmpi1 - csky +#as: -mcpu=ck610 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*0000\s*bkpt\s* +\s*[0-9a-f]:\s*70[0-9a-f]*\s*jmpi\s*0x0\s*\/\/\s*from\s*address\s*pool\s*at\s*0x[0-9a-f]* +\s*[0-9a-f]:\s*0000\s*bkpt\s* +\s*[0-9a-f]:\s*f7ff\s*br\s*0x[0-9a-f]*\s*\/\/\s*[0-9a-f]*\s*\<LABEL\+0x[0-9a-f]*\> +\s*[0-9a-f]:\s*f7ff\s*br\s*0x[0-9a-f]*\s*\/\/\s*[0-9a-f]*\s*\<LABEL\+0x[0-9a-f]*\> +\s*[0-9a-f]:\s*1200\s*\.short\s*0x1200 +\s*[0-9a-f]:\s*00000000\s*\.long\s*0x00000000 +#... diff --git a/gas/testsuite/gas/csky/jmpi1.s b/gas/testsuite/gas/csky/jmpi1.s new file mode 100644 index 0000000..c7ad604 --- /dev/null +++ b/gas/testsuite/gas/csky/jmpi1.s @@ -0,0 +1,6 @@ +.text + +LABEL: + bkpt + jmpi LABEL + bkpt diff --git a/gas/testsuite/gas/csky/jmpi2.d b/gas/testsuite/gas/csky/jmpi2.d new file mode 100644 index 0000000..5d855cf --- /dev/null +++ b/gas/testsuite/gas/csky/jmpi2.d @@ -0,0 +1,14 @@ +# name: jmpi2 - csky +#as: -mcpu=ck610 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*0000\s*bkpt\s* +\s*[0-9a-f]:\s*70[0-9a-f]*\s*jmpi\s*0x0\s*\/\/\s*from\s*address\s*pool\s*at\s*0x[0-9a-f]* +\s*[0-9a-f]:\s*f7ff\s*br\s*0x[0-9a-f]*\s*\/\/\s*[0-9a-f]*\s*\<LABEL\+0x[0-9a-f]*\> +\s*[0-9a-f]:\s*f7ff\s*br\s*0x[0-9a-f]*\s*\/\/\s*[0-9a-f]*\s*\<LABEL\+0x[0-9a-f]*\> +\s*[0-9a-f]:\s*00000000\s*\.long\s*0x00000000 +#... diff --git a/gas/testsuite/gas/csky/jmpi2.s b/gas/testsuite/gas/csky/jmpi2.s new file mode 100644 index 0000000..91e209f --- /dev/null +++ b/gas/testsuite/gas/csky/jmpi2.s @@ -0,0 +1,5 @@ +.text + +LABEL: + bkpt + jmpi LABEL2 diff --git a/gas/testsuite/gas/csky/jmpi3.d b/gas/testsuite/gas/csky/jmpi3.d new file mode 100644 index 0000000..c19b04f --- /dev/null +++ b/gas/testsuite/gas/csky/jmpi3.d @@ -0,0 +1,9 @@ +# name: jmpi2 - csky +#as: -mcpu=ck610 +#readelf: -r --wide + + +Relocation section '.rela.text\' at offset .* contains 1 entry: +#... +.*R_CKCORE_ADDR32[ \t]+00000000[ \t]+\.text \+[ \t]+[0-9a-f]+ +#pass diff --git a/gas/testsuite/gas/csky/jmpi3.s b/gas/testsuite/gas/csky/jmpi3.s new file mode 100644 index 0000000..c7ad604 --- /dev/null +++ b/gas/testsuite/gas/csky/jmpi3.s @@ -0,0 +1,6 @@ +.text + +LABEL: + bkpt + jmpi LABEL + bkpt diff --git a/gas/testsuite/gas/csky/jmpiv2_1.d b/gas/testsuite/gas/csky/jmpiv2_1.d new file mode 100644 index 0000000..d8006e7 --- /dev/null +++ b/gas/testsuite/gas/csky/jmpiv2_1.d @@ -0,0 +1,13 @@ +# name: jmpiv2_1 - csky +#as: -mcpu=ck810 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*0000\s*bkpt\s* +\s*[0-9a-f]:\s*eac00002\s*jmpi\s*0x0\s*\/\/\s*from\s*address\s*pool\s*at\s*0x[0-9a-f]* +\s*[0-9a-f]:\s*0000\s*bkpt\s* +\s*[0-9a-f]:\s*00000000\s*\.long\s*0x00000000 +#... diff --git a/gas/testsuite/gas/csky/jmpiv2_1.s b/gas/testsuite/gas/csky/jmpiv2_1.s new file mode 100644 index 0000000..c7ad604 --- /dev/null +++ b/gas/testsuite/gas/csky/jmpiv2_1.s @@ -0,0 +1,6 @@ +.text + +LABEL: + bkpt + jmpi LABEL + bkpt diff --git a/gas/testsuite/gas/csky/jmpiv2_2.d b/gas/testsuite/gas/csky/jmpiv2_2.d new file mode 100644 index 0000000..c0aef4a --- /dev/null +++ b/gas/testsuite/gas/csky/jmpiv2_2.d @@ -0,0 +1,9 @@ +# name: jmpiv2_2 - csky +#as: -mcpu=ck810 +#readelf: -r --wide + + +Relocation section '.rela.text\' at offset .* contains 1 entry: +#... +.*R_CKCORE_ADDR32[ \t]+00000000[ \t]+\.text \+[ \t]+[0-9a-f]+ +#pass diff --git a/gas/testsuite/gas/csky/jmpiv2_2.s b/gas/testsuite/gas/csky/jmpiv2_2.s new file mode 100644 index 0000000..c7ad604 --- /dev/null +++ b/gas/testsuite/gas/csky/jmpiv2_2.s @@ -0,0 +1,6 @@ +.text + +LABEL: + bkpt + jmpi LABEL + bkpt diff --git a/gas/testsuite/gas/csky/jsriv2_1.d b/gas/testsuite/gas/csky/jsriv2_1.d new file mode 100644 index 0000000..524f847 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_1.d @@ -0,0 +1,13 @@ +# name: jsriv2_1 - csky +#as: -mcpu=ck807 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*0000\s*bkpt +\s*[0-9a-f]:\s*eae00002\s*jsri\s*0x0\s*\/\/\s*from\s*address\s*pool\s*at\s*0x[0-9a-f]* +\s*[0-9a-f]:\s*0000\s*.short\s*0x0000 +\s*[0-9a-f]:\s*00000000\s*.long\s*0x00000000 +#... diff --git a/gas/testsuite/gas/csky/jsriv2_1.s b/gas/testsuite/gas/csky/jsriv2_1.s new file mode 100644 index 0000000..45ce734 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_1.s @@ -0,0 +1,5 @@ +.text + +LABEL: +bkpt +jsri LABEL diff --git a/gas/testsuite/gas/csky/jsriv2_2.d b/gas/testsuite/gas/csky/jsriv2_2.d new file mode 100644 index 0000000..3a373b5 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_2.d @@ -0,0 +1,14 @@ +# name: jsriv2_2 - csky +#as: -mcpu=ck810 +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]:\s*0000\s*bkpt +\s*[0-9a-f]:\s*e3ffffff\s*bsr\s*0x0\s*\/\/\s*0\s*<LABEL> +\s*[0-9a-f]:\s*c4004820\s*lsli\s*r0,\s*\s*r0,\s*0 +\s*[0-9a-f]:\s*0000\s*.short\s*0x0000 +\s*[0-9a-f]:\s*00000000\s*.long\s*0x00000000 +#... diff --git a/gas/testsuite/gas/csky/jsriv2_2.s b/gas/testsuite/gas/csky/jsriv2_2.s new file mode 100644 index 0000000..45ce734 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_2.s @@ -0,0 +1,5 @@ +.text + +LABEL: +bkpt +jsri LABEL diff --git a/gas/testsuite/gas/csky/jsriv2_3.d b/gas/testsuite/gas/csky/jsriv2_3.d new file mode 100644 index 0000000..9e46368 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_3.d @@ -0,0 +1,9 @@ +# name: jsriv2_3 - csky +#as: -mcpu=ck807 +#readelf: -r --wide + + +Relocation section '.rela.text\' at offset .* contains 1 entry: +#... +00000008.*R_CKCORE_ADDR32[ \t]+00000000[ \t]+\.text \+[ \t]+[0-9a-f]+ +#pass diff --git a/gas/testsuite/gas/csky/jsriv2_3.s b/gas/testsuite/gas/csky/jsriv2_3.s new file mode 100644 index 0000000..45ce734 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_3.s @@ -0,0 +1,5 @@ +.text + +LABEL: +bkpt +jsri LABEL diff --git a/gas/testsuite/gas/csky/jsriv2_4.d b/gas/testsuite/gas/csky/jsriv2_4.d new file mode 100644 index 0000000..851ef6a --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_4.d @@ -0,0 +1,9 @@ +# name: jsriv2_4 - csky +#as: -mcpu=ck810 +#readelf: -r --wide + + +Relocation section '.rela.text\' at offset .* contains 1 entry: +#... +0000000c.*R_CKCORE_ADDR32[ \t]+00000000[ \t]+\.text \+[ \t]+[0-9a-f]+ +#pass diff --git a/gas/testsuite/gas/csky/jsriv2_4.s b/gas/testsuite/gas/csky/jsriv2_4.s new file mode 100644 index 0000000..45ce734 --- /dev/null +++ b/gas/testsuite/gas/csky/jsriv2_4.s @@ -0,0 +1,5 @@ +.text + +LABEL: +bkpt +jsri LABEL diff --git a/gas/testsuite/gas/csky/trust.d b/gas/testsuite/gas/csky/trust.d new file mode 100644 index 0000000..1a87b4d --- /dev/null +++ b/gas/testsuite/gas/csky/trust.d @@ -0,0 +1,17 @@ +# name: trust - csky +#as: -mcpu=ck810t +#objdump: -d + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*c0003c20\s*wsc +\s*[0-9a-f]*:\s*c0006024\s*mfcr\s*r4,\s*cr<0,\s*0> +\s*[0-9a-f]*:\s*c0156024\s*mfcr\s*r4,\s*cr<21,\s*0> +\s*[0-9a-f]*:\s*c004642b\s*mtcr\s*r4,\s*cr<11,\s*0> +\s*[0-9a-f]*:\s*c0046428\s*mtcr\s*r4,\s*cr<8,\s*0> +\s*[0-9a-f]*:\s*c0096024\s*mfcr\s*r4,\s*cr<9,\s*0> +\s*[0-9a-f]*:\s*c2007420\s*psrset\s*sie +\s*[0-9a-f]*:\s*c2007020\s*psrclr\s*sie +#... diff --git a/gas/testsuite/gas/csky/trust.s b/gas/testsuite/gas/csky/trust.s new file mode 100644 index 0000000..781dc8cb --- /dev/null +++ b/gas/testsuite/gas/csky/trust.s @@ -0,0 +1,9 @@ +TRUST: + wsc + mfcr r4, psr + mfcr r4, rid + mtcr r4, gcr + mtcr r4, sedcr + mfcr r4, sepcr + psrset sie + psrclr sie diff --git a/gas/testsuite/gas/csky/v1_float.d b/gas/testsuite/gas/csky/v1_float.d new file mode 100644 index 0000000..995a77d --- /dev/null +++ b/gas/testsuite/gas/csky/v1_float.d @@ -0,0 +1,222 @@ +# name: csky - v1-float +#as: -mcpu=ck610ef -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe06002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe06402.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffec1002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffec9002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffed9002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffee1002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffed1002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffee9002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffef1002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffef9002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +#... +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe04403.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe04c03.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe05403.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe05c03.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe38c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe48c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe58c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe68c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe78c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe88c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe98c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffea8c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffeb8c02.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe04002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe04802.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe05002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe05802.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe31002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe41002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe51002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe61002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe71002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe81002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe91002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffea1002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffeb1002.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +#... +\s*[0-9a-f]*:\s*744a\s*lrw\s*r4,\s*0xffe00840.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7449\s*lrw\s*r4,\s*0xffe00c40.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7449\s*lrw\s*r4,\s*0xffe01040.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7448\s*lrw\s*r4,\s*0xffe01440.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7448\s*lrw\s*r4,\s*0xffe01841.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7447\s*lrw\s*r4,\s*0xffe01c41.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7447\s*lrw\s*r4,\s*0xffe02041.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7446\s*lrw\s*r4,\s*0xffe02441.* +\s*[0-9a-f]*:\s*3204\s*cpwir\s*r4 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7346\s*lrw\s*r3,\s*0xffe00400.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7345\s*lrw\s*r3,\s*0xffe00480.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7345\s*lrw\s*r3,\s*0xffe00500.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7344\s*lrw\s*r3,\s*0xffe00580.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7344\s*lrw\s*r3,\s*0xffe00600.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7343\s*lrw\s*r3,\s*0xffe00680.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7343\s*lrw\s*r3,\s*0xffe00700.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +\s*[0-9a-f]*:\s*7342\s*lrw\s*r3,\s*0xffe00780.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*000d\s*cprc +#... +\s*[0-9a-f]*:\s*7242\s*lrw\s*r2,\s*0xffe02801.* +\s*[0-9a-f]*:\s*3202\s*cpwir\s*r2 +\s*[0-9a-f]*:\s*7242\s*lrw\s*r2,\s*0xffe02c02.* +\s*[0-9a-f]*:\s*3202\s*cpwir\s*r2 +\s*[0-9a-f]*:\s*7242\s*lrw\s*r2,\s*0xffe03402.* +\s*[0-9a-f]*:\s*3202\s*cpwir\s*r2 +\s*[0-9a-f]*:\s*7242\s*lrw\s*r2,\s*0xffe03002.* +\s*[0-9a-f]*:\s*3202\s*cpwir\s*r2 +\s*[0-9a-f]*:\s*7242\s*lrw\s*r2,\s*0xffe03c02.* +\s*[0-9a-f]*:\s*3202\s*cpwir\s*r2 +\s*[0-9a-f]*:\s*7242\s*lrw\s*r2,\s*0xffe03802.* +\s*[0-9a-f]*:\s*3202\s*cpwir\s*r2 +\s*[0-9a-f]*:\s*7342\s*lrw\s*r3,\s*0xffe10002.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*7342\s*lrw\s*r3,\s*0xffe08002.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*7342\s*lrw\s*r3,\s*0xffe20002.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +\s*[0-9a-f]*:\s*7342\s*lrw\s*r3,\s*0xffe18002.* +\s*[0-9a-f]*:\s*3203\s*cpwir\s*r3 +#... +\s*[0-9a-f]*:\s*2642\s*cpwgr\s*r2,\s*cpr4 +\s*[0-9a-f]*:\s*0842\s*cprgr\s*r2,\s*cpr4 +\s*[0-9a-f]*:\s*2642\s*cpwgr\s*r2,\s*cpr4 +\s*[0-9a-f]*:\s*2653\s*cpwgr\s*r3,\s*cpr5 +\s*[0-9a-f]*:\s*0842\s*cprgr\s*r2,\s*cpr4 +\s*[0-9a-f]*:\s*0853\s*cprgr\s*r3,\s*cpr5 +\s*[0-9a-f]*:\s*f7ff\s*br\s*0x124.* +\s*[0-9a-f]*:\s*f7ff\s*br\s*0x126.* +\s*[0-9a-f]*:\s*ffe06002\s*\.long\s*0xffe06002 +\s*[0-9a-f]*:\s*ffe06402\s*\.long\s*0xffe06402 +\s*[0-9a-f]*:\s*ffec1002\s*\.long\s*0xffec1002 +\s*[0-9a-f]*:\s*ffec9002\s*\.long\s*0xffec9002 +\s*[0-9a-f]*:\s*ffed9002\s*\.long\s*0xffed9002 +\s*[0-9a-f]*:\s*ffee1002\s*\.long\s*0xffee1002 +\s*[0-9a-f]*:\s*ffed1002\s*\.long\s*0xffed1002 +\s*[0-9a-f]*:\s*ffee9002\s*\.long\s*0xffee9002 +\s*[0-9a-f]*:\s*ffef1002\s*\.long\s*0xffef1002 +\s*[0-9a-f]*:\s*ffef9002\s*\.long\s*0xffef9002 +\s*[0-9a-f]*:\s*ffe04403\s*\.long\s*0xffe04403 +\s*[0-9a-f]*:\s*ffe04c03\s*\.long\s*0xffe04c03 +\s*[0-9a-f]*:\s*ffe05403\s*\.long\s*0xffe05403 +\s*[0-9a-f]*:\s*ffe05c03\s*\.long\s*0xffe05c03 +\s*[0-9a-f]*:\s*ffe38c02\s*\.long\s*0xffe38c02 +\s*[0-9a-f]*:\s*ffe48c02\s*\.long\s*0xffe48c02 +\s*[0-9a-f]*:\s*ffe58c02\s*\.long\s*0xffe58c02 +\s*[0-9a-f]*:\s*ffe68c02\s*\.long\s*0xffe68c02 +\s*[0-9a-f]*:\s*ffe78c02\s*\.long\s*0xffe78c02 +\s*[0-9a-f]*:\s*ffe88c02\s*\.long\s*0xffe88c02 +\s*[0-9a-f]*:\s*ffe98c02\s*\.long\s*0xffe98c02 +\s*[0-9a-f]*:\s*ffea8c02\s*\.long\s*0xffea8c02 +\s*[0-9a-f]*:\s*ffeb8c02\s*\.long\s*0xffeb8c02 +\s*[0-9a-f]*:\s*ffe04002\s*\.long\s*0xffe04002 +\s*[0-9a-f]*:\s*ffe04802\s*\.long\s*0xffe04802 +\s*[0-9a-f]*:\s*ffe05002\s*\.long\s*0xffe05002 +\s*[0-9a-f]*:\s*ffe05802\s*\.long\s*0xffe05802 +\s*[0-9a-f]*:\s*ffe31002\s*\.long\s*0xffe31002 +\s*[0-9a-f]*:\s*ffe41002\s*\.long\s*0xffe41002 +\s*[0-9a-f]*:\s*ffe51002\s*\.long\s*0xffe51002 +\s*[0-9a-f]*:\s*ffe61002\s*\.long\s*0xffe61002 +\s*[0-9a-f]*:\s*ffe71002\s*\.long\s*0xffe71002 +\s*[0-9a-f]*:\s*ffe81002\s*\.long\s*0xffe81002 +\s*[0-9a-f]*:\s*ffe91002\s*\.long\s*0xffe91002 +\s*[0-9a-f]*:\s*ffea1002\s*\.long\s*0xffea1002 +\s*[0-9a-f]*:\s*ffeb1002\s*\.long\s*0xffeb1002 +\s*[0-9a-f]*:\s*ffe00840\s*\.long\s*0xffe00840 +\s*[0-9a-f]*:\s*ffe00c40\s*\.long\s*0xffe00c40 +\s*[0-9a-f]*:\s*ffe01040\s*\.long\s*0xffe01040 +\s*[0-9a-f]*:\s*ffe01440\s*\.long\s*0xffe01440 +\s*[0-9a-f]*:\s*ffe01841\s*\.long\s*0xffe01841 +\s*[0-9a-f]*:\s*ffe01c41\s*\.long\s*0xffe01c41 +\s*[0-9a-f]*:\s*ffe02041\s*\.long\s*0xffe02041 +\s*[0-9a-f]*:\s*ffe02441\s*\.long\s*0xffe02441 +\s*[0-9a-f]*:\s*ffe00400\s*\.long\s*0xffe00400 +\s*[0-9a-f]*:\s*ffe00480\s*\.long\s*0xffe00480 +\s*[0-9a-f]*:\s*ffe00500\s*\.long\s*0xffe00500 +\s*[0-9a-f]*:\s*ffe00580\s*\.long\s*0xffe00580 +\s*[0-9a-f]*:\s*ffe00600\s*\.long\s*0xffe00600 +\s*[0-9a-f]*:\s*ffe00680\s*\.long\s*0xffe00680 +\s*[0-9a-f]*:\s*ffe00700\s*\.long\s*0xffe00700 +\s*[0-9a-f]*:\s*ffe00780\s*\.long\s*0xffe00780 +\s*[0-9a-f]*:\s*ffe02801\s*\.long\s*0xffe02801 +\s*[0-9a-f]*:\s*ffe02c02\s*\.long\s*0xffe02c02 +\s*[0-9a-f]*:\s*ffe03402\s*\.long\s*0xffe03402 +\s*[0-9a-f]*:\s*ffe03002\s*\.long\s*0xffe03002 +\s*[0-9a-f]*:\s*ffe03c02\s*\.long\s*0xffe03c02 +\s*[0-9a-f]*:\s*ffe03802\s*\.long\s*0xffe03802 +\s*[0-9a-f]*:\s*ffe10002\s*\.long\s*0xffe10002 +\s*[0-9a-f]*:\s*ffe08002\s*\.long\s*0xffe08002 +\s*[0-9a-f]*:\s*ffe20002\s*\.long\s*0xffe20002 +\s*[0-9a-f]*:\s*ffe18002\s*\.long\s*0xffe18002 diff --git a/gas/testsuite/gas/csky/v1_float.s b/gas/testsuite/gas/csky/v1_float.s new file mode 100644 index 0000000..550379a --- /dev/null +++ b/gas/testsuite/gas/csky/v1_float.s @@ -0,0 +1,78 @@ +.text + +L0: + fabsm fr0, fr2, r4 + fnegm fr0, fr2, r4 + faddm fr0, fr2, fr4, r4 + fsubm fr0, fr2, fr4, r4 + fmacm fr0, fr2, fr4, r4 + fmscm fr0, fr2, fr4, r4 + fmulm fr0, fr2, fr4, r4 + fnmacm fr0, fr2, fr4, r4 + fnmscm fr0, fr2, fr4, r4 + fnmulm fr0, fr2, fr4, r4 + +L1: + fabss fr0, fr3, r4 + fnegs fr0, fr3, r4 + fsqrts fr0, fr3, r4 + frecips fr0, fr3, r4 + fadds fr0, fr2, fr3, r4 + fsubs fr0, fr2, fr3, r4 + fmacs fr0, fr2, fr3, r4 + fmscs fr0, fr2, fr3, r4 + fmuls fr0, fr2, fr3, r4 + fdivs fr0, fr2, fr3, r4 + fnmacs fr0, fr2, fr3, r4 + fnmscs fr0, fr2, fr3, r4 + fnmuls fr0, fr2, fr3, r4 + + fabsd fr0, fr2, r4 + fnegd fr0, fr2, r4 + fsqrtd fr0, fr2, r4 + frecipd fr0, fr2, r4 + faddd fr0, fr2, fr4, r4 + fsubd fr0, fr2, fr4, r4 + fmacd fr0, fr2, fr4, r4 + fmscd fr0, fr2, fr4, r4 + fmuld fr0, fr2, fr4, r4 + fdivd fr0, fr2, fr4, r4 + fnmacd fr0, fr2, fr4, r4 + fnmscd fr0, fr2, fr4, r4 + fnmuld fr0, fr2, fr4, r4 + +L2: + fcmphsd fr0, fr2, r4 + fcmpltd fr0, fr2, r4 + fcmpned fr0, fr2, r4 + fcmpuod fr0, fr2, r4 + fcmphss fr1, fr2, r4 + fcmplts fr1, fr2, r4 + fcmpnes fr1, fr2, r4 + fcmpuos fr1, fr2, r4 + fcmpzhsd fr0, r3 + fcmpzltd fr0, r3 + fcmpzned fr0, r3 + fcmpzuod fr0, r3 + fcmpzhss fr0, r3 + fcmpzlts fr0, r3 + fcmpznes fr0, r3 + fcmpzuos fr0, r3 + +L3: + fstod fr0, fr1, r2 + fdtos fr0, fr2, r2 + fsitos fr0, fr2, r2 + fsitod fr0, fr2, r2 + fuitos fr0, fr2, r2 + fuitod fr0, fr2, r2 + fstosi fr0, fr2, RM_NEAREST, r3 + fdtosi fr0, fr2, RM_NEAREST, r3 + fstoui fr0, fr2, RM_NEAREST, r3 + fdtoui fr0, fr2, RM_NEAREST, r3 + +L4: + fmts r2, fr4 + fmfs r2, fr4 + fmtd r2, fr4 + fmfd r2, fr4 diff --git a/gas/testsuite/gas/csky/v2_float_part1.d b/gas/testsuite/gas/csky/v2_float_part1.d new file mode 100644 index 0000000..aa0b0a4 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_float_part1.d @@ -0,0 +1,54 @@ +# name: csky - v2-float +#as: -mcpu=ck810ef -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*f4243403\s*fstms\s*fr3-fr4,\s*\(r4\) +\s*[0-9a-f]*:\s*f4243003\s*fldms\s*fr3-fr4,\s*\(r4\) +\s*[0-9a-f]*:\s*f4243603\s*fstmm\s*fr3-fr4,\s*\(r4\) +\s*[0-9a-f]*:\s*f4243203\s*fldmm\s*fr3-fr4,\s*\(r4\) +\s*[0-9a-f]*:\s*f4243503\s*fstmd\s*fr3-fr4,\s*\(r4\) +\s*[0-9a-f]*:\s*f4243103\s*fldmd\s*fr3-fr4,\s*\(r4\) +\s*[0-9a-f]*:\s*f4022600\s*fstm\s*fr0,\s*\(r2,\s*0x0\) +\s*[0-9a-f]*:\s*f4022200\s*fldm\s*fr0,\s*\(r2,\s*0x0\) +\s*[0-9a-f]*:\s*f4022610\s*fstm\s*fr0,\s*\(r2,\s*0x8\) +\s*[0-9a-f]*:\s*f4022210\s*fldm\s*fr0,\s*\(r2,\s*0x8\) +\s*[0-9a-f]*:\s*f4022510\s*fstd\s*fr0,\s*\(r2,\s*0x4\) +\s*[0-9a-f]*:\s*f4022110\s*fldd\s*fr0,\s*\(r2,\s*0x4\) +\s*[0-9a-f]*:\s*f4022410\s*fsts\s*fr0,\s*\(r2,\s*0x4\) +\s*[0-9a-f]*:\s*f4022010\s*flds\s*fr0,\s*\(r2,\s*0x4\) +\s*[0-9a-f]*:\s*f4822e02\s*fstrm\s*fr2,\s*\(r2,\s*r4\s*<<\s*0\) +\s*[0-9a-f]*:\s*f4822e42\s*fstrm\s*fr2,\s*\(r2,\s*r4\s*<<\s*2\) +\s*[0-9a-f]*:\s*f4822d02\s*fstrd\s*fr2,\s*\(r2,\s*r4\s*<<\s*0\) +\s*[0-9a-f]*:\s*f4822d42\s*fstrd\s*fr2,\s*\(r2,\s*r4\s*<<\s*2\) +\s*[0-9a-f]*:\s*f4822c02\s*fstrs\s*fr2,\s*\(r2,\s*r4\s*<<\s*0\) +\s*[0-9a-f]*:\s*f4822c42\s*fstrs\s*fr2,\s*\(r2,\s*r4\s*<<\s*2\) +\s*[0-9a-f]*:\s*f4831222\s*fnmulm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f48312e2\s*fnmscm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f48312c2\s*fnmacm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f48312a2\s*fmscm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4831282\s*fmacm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4831202\s*fmulm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4831022\s*fsubm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4831002\s*faddm\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830a22\s*fnmuld\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830ae2\s*fnmscd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830ac2\s*fnmacd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830aa2\s*fmscd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830a82\s*fmacd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830b02\s*fdivd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830a02\s*fmuld\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830822\s*fsubd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830802\s*faddd\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830222\s*fnmuls\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f48302e2\s*fnmscs\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f48302c2\s*fnmacs\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f48302a2\s*fmscs\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830282\s*fmacs\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830302\s*fdivs\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830202\s*fmuls\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830022\s*fsubs\s*fr2,\s*fr3,\s*fr4 +\s*[0-9a-f]*:\s*f4830002\s*fadds\s*fr2,\s*fr3,\s*fr4 diff --git a/gas/testsuite/gas/csky/v2_float_part1.s b/gas/testsuite/gas/csky/v2_float_part1.s new file mode 100644 index 0000000..826b32d --- /dev/null +++ b/gas/testsuite/gas/csky/v2_float_part1.s @@ -0,0 +1,48 @@ + .text +L1: + fstms vr3-vr4, (r4) + fldms vr3-vr4, (r4) + fstmm vr3-vr4, (r4) + fldmm vr3-vr4, (r4) + fstmd vr3-vr4, (r4) + fldmd vr3-vr4, (r4) + fstm vr0, (r2, 0) + fldm vr0, (r2, 0) + fstm vr0, (r2, 8) + fldm vr0, (r2, 8) + fstd vr0, (r2, 4) + fldd vr0, (r2, 4) + fsts vr0, (r2, 4) + flds vr0, (r2, 4) + fstrm vr2, (r2, r4 << 0) + fstrm vr2, (r2, r4 << 2) + fstrd vr2, (r2, r4 << 0) + fstrd vr2, (r2, r4 << 2) + fstrs vr2, (r2, r4 << 0) + fstrs vr2, (r2, r4 << 2) + fnmulm vr2, vr3, vr4 + fnmscm vr2, vr3, vr4 + fnmacm vr2, vr3, vr4 + fmscm vr2, vr3, vr4 + fmacm vr2, vr3, vr4 + fmulm vr2, vr3, vr4 + fsubm vr2, vr3, vr4 + faddm vr2, vr3, vr4 + fnmuld vr2, vr3, vr4 + fnmscd vr2, vr3, vr4 + fnmacd vr2, vr3, vr4 + fmscd vr2, vr3, vr4 + fmacd vr2, vr3, vr4 + fdivd vr2, vr3, vr4 + fmuld vr2, vr3, vr4 + fsubd vr2, vr3, vr4 + faddd vr2, vr3, vr4 + fnmuls vr2, vr3, vr4 + fnmscs vr2, vr3, vr4 + fnmacs vr2, vr3, vr4 + fmscs vr2, vr3, vr4 + fmacs vr2, vr3, vr4 + fdivs vr2, vr3, vr4 + fmuls vr2, vr3, vr4 + fsubs vr2, vr3, vr4 + fadds vr2, vr3, vr4 diff --git a/gas/testsuite/gas/csky/v2_float_part2.d b/gas/testsuite/gas/csky/v2_float_part2.d new file mode 100644 index 0000000..94b04e0 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_float_part2.d @@ -0,0 +1,20 @@ +# name: csky - v2-float-part2 +#as: -mcpu=ck807f -W +#objdump: -D + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*f4003882\s*flrws\s*fr2,\s*3\.140000 +\s*[0-9a-f]*:\s*f50b1c02\s*fmovis\s*fr2,\s*1\.500000 +\s*[0-9a-f]*:\s*f51b1c02\s*fmovis\s*fr2,\s*-1\.500000 +\s*[0-9a-f]*:\s*f48a1c02\s*fmovis\s*fr2,\s*2\.500000 +#... +\s*[0-9a-f]*:\s*f4003952\s*flrwd\s*fr2,\s*3\.140000 +\s*[0-9a-f]*:\s*f48a1e02\s*fmovid\s*fr2,\s*2\.500000 +\s*[0-9a-f]*:\s*f49a1e02\s*fmovid\s*fr2,\s*-2\.500000 +\s*[0-9a-f]*:\s*f51b1e02\s*fmovid\s*fr2,\s*-1\.500000 +\s*[0-9a-f]*:\s*4048f5c3\s*\.long\s*0x4048f5c3 +\s*[0-9a-f]*:\s*51eb851f\s*\.long\s*0x51eb851f +\s*[0-9a-f]*:\s*40091eb8\s*\.long\s*0x40091eb8 diff --git a/gas/testsuite/gas/csky/v2_float_part2.s b/gas/testsuite/gas/csky/v2_float_part2.s new file mode 100644 index 0000000..92c253b --- /dev/null +++ b/gas/testsuite/gas/csky/v2_float_part2.s @@ -0,0 +1,10 @@ +only_in_803_807: + flrws fr2, 3.14 + fmovis fr2, 1.5 + fmovis fr2, -1.5 + fmovis fr2, 2.5 +only_in_807: + flrwd fr2, 3.14 + fmovid fr2, 2.5 + fmovid fr2, -2.5 + fmovid fr2, -1.5 diff --git a/gas/testsuite/gas/csky/v2_tls_gd.d b/gas/testsuite/gas/csky/v2_tls_gd.d new file mode 100644 index 0000000..226beaa --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_gd.d @@ -0,0 +1,10 @@ +# name: csky - v2 TLS GD +#as: -mcpu=ck810 -W +#objdump: -Dr + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*R_CKCORE_TLS_GD32\s*xxx.* +\s*[0-9a-f]*:\s*R_CKCORE_PLT32\s*__tls_get_addr diff --git a/gas/testsuite/gas/csky/v2_tls_gd.s b/gas/testsuite/gas/csky/v2_tls_gd.s new file mode 100644 index 0000000..4a419d3 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_gd.s @@ -0,0 +1,7 @@ +.LTLS0: + lrw a0, xxx@TLSGD32 + grs a2, .LTLS0 + addu a0, a0, a2 + lrw a3, __tls_get_addr@PLT + ldr.w a3, (gb, a3 << 0) + jsr a3 diff --git a/gas/testsuite/gas/csky/v2_tls_ie.d b/gas/testsuite/gas/csky/v2_tls_ie.d new file mode 100644 index 0000000..db77387 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_ie.d @@ -0,0 +1,9 @@ +# name: csky - v2 TLS IE +#as: -mcpu=ck810 -W +#objdump: -Dr + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*R_CKCORE_TLS_IE32\s*xxx.* diff --git a/gas/testsuite/gas/csky/v2_tls_ie.s b/gas/testsuite/gas/csky/v2_tls_ie.s new file mode 100644 index 0000000..15288c7 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_ie.s @@ -0,0 +1,7 @@ +.LTLS0: + lrw a3, xxx@GOTTPOFF + grs a2, .LTLS0 + addu a3, a3, a2 + ld.w a3, (a3, 0) + mov a2, tls + str.w a0, (a2, a3 << 0) diff --git a/gas/testsuite/gas/csky/v2_tls_ld.d b/gas/testsuite/gas/csky/v2_tls_ld.d new file mode 100644 index 0000000..9f12ace --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_ld.d @@ -0,0 +1,11 @@ +# name: csky - v2 TLS LD +#as: -mcpu=ck810 -W +#objdump: -Dr + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*R_CKCORE_TLS_LDM32\s*xxx.* +\s*[0-9a-f]*:\s*R_CKCORE_PLT32\s*__tls_get_addr +\s*[0-9a-f]*:\s*R_CKCORE_TLS_LDO32\s*xxx diff --git a/gas/testsuite/gas/csky/v2_tls_ld.s b/gas/testsuite/gas/csky/v2_tls_ld.s new file mode 100644 index 0000000..762f27e --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_ld.s @@ -0,0 +1,9 @@ +.LTLS0: + lrw a0, xxx@TLSLDM32 + grs a2, .LTLS0 + addu a0, a0, a2 + lrw a3, __tls_get_addr@PLT + ldr.w a3, (gb, a3 << 0) + jsr a3 + lrw a3, xxx@TLSLDO32 + str.w l0, (a0, a3 << 0) diff --git a/gas/testsuite/gas/csky/v2_tls_le.d b/gas/testsuite/gas/csky/v2_tls_le.d new file mode 100644 index 0000000..c34d6d7 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_le.d @@ -0,0 +1,9 @@ +# name: csky - v2 TLS IE +#as: -mcpu=ck810 -W +#objdump: -Dr + +.*: +file format .*csky.* + +Disassembly of section \.text: +#... +\s*[0-9a-f]*:\s*R_CKCORE_TLS_LE32\s*xxx diff --git a/gas/testsuite/gas/csky/v2_tls_le.s b/gas/testsuite/gas/csky/v2_tls_le.s new file mode 100644 index 0000000..06b05f4 --- /dev/null +++ b/gas/testsuite/gas/csky/v2_tls_le.s @@ -0,0 +1,3 @@ + lrw a3, xxx@TPOFF + mov a2, tls + str.w a0, (a2, a3 << 0) diff --git a/include/ChangeLog b/include/ChangeLog index b56b6ba..650f7c9 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2018-07-30 Andrew Jenner <andrew@codesourcery.com> + + * elf/common.h (EM_CSKY, EM_CSKY_OLD): Define. + * elf/csky.h: New file. + 2018-07-27 Chenghua Xu <paul.hua.gm@gmail.com> Maciej W. Rozycki <macro@linux-mips.org> diff --git a/include/dis-asm.h b/include/dis-asm.h index 77b9e61..949ccde 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -300,6 +300,7 @@ extern void print_s390_disassembler_options (FILE *); extern void print_wasm32_disassembler_options (FILE *); extern bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *); extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); +extern bfd_boolean csky_symbol_is_valid (asymbol *, struct disassemble_info *); extern void disassemble_init_powerpc (struct disassemble_info *); extern void disassemble_init_s390 (struct disassemble_info *); extern void disassemble_init_wasm32 (struct disassemble_info *); diff --git a/include/elf/common.h b/include/elf/common.h index 3a6244d..1a940ff 100644 --- a/include/elf/common.h +++ b/include/elf/common.h @@ -340,6 +340,7 @@ #define EM_LANAI 244 /* Lanai 32-bit processor. */ #define EM_BPF 247 /* Linux BPF – in-kernel virtual machine. */ #define EM_NFP 250 /* Netronome Flow Processor. */ +#define EM_CSKY 252 /* C-SKY processor family. */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision @@ -435,6 +436,10 @@ /* Old constant that might be in use by some software. */ #define EM_OPENRISC EM_OR1K +/* C-SKY historically used 39, the same value as MCORE, from which the + architecture was derived. */ +#define EM_CSKY_OLD EM_MCORE + /* See the above comment before you add a new EM_* value here. */ /* Values for e_version. */ diff --git a/include/elf/csky.h b/include/elf/csky.h new file mode 100644 index 0000000..1ccbd62 --- /dev/null +++ b/include/elf/csky.h @@ -0,0 +1,97 @@ +/* C-SKY ELF support for BFD. + Copyright (C) 1998-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_CSKY_H +#define _ELF_CSKY_H + +#include "elf/reloc-macros.h" + +/* Values of relocation types according to the ABI doc. + The order should be consistent with csky bfd reloc type + table in bfd-in2.h. */ +START_RELOC_NUMBERS (elf_csky_reloc_type) + RELOC_NUMBER (R_CKCORE_NONE,0) + RELOC_NUMBER (R_CKCORE_ADDR32,1) + RELOC_NUMBER (R_CKCORE_PCREL_IMM8BY4,2) + RELOC_NUMBER (R_CKCORE_PCREL_IMM11BY2,3) + RELOC_NUMBER (R_CKCORE_PCREL_IMM4BY2,4) + RELOC_NUMBER (R_CKCORE_PCREL32,5) + RELOC_NUMBER (R_CKCORE_PCREL_JSR_IMM11BY2,6) + RELOC_NUMBER (R_CKCORE_GNU_VTINHERIT,7) + RELOC_NUMBER (R_CKCORE_GNU_VTENTRY,8) + RELOC_NUMBER (R_CKCORE_RELATIVE,9) + RELOC_NUMBER (R_CKCORE_COPY,10) + RELOC_NUMBER (R_CKCORE_GLOB_DAT,11) + RELOC_NUMBER (R_CKCORE_JUMP_SLOT,12) + RELOC_NUMBER (R_CKCORE_GOTOFF,13) + RELOC_NUMBER (R_CKCORE_GOTPC,14) + RELOC_NUMBER (R_CKCORE_GOT32,15) + RELOC_NUMBER (R_CKCORE_PLT32,16) + RELOC_NUMBER (R_CKCORE_ADDRGOT,17) + RELOC_NUMBER (R_CKCORE_ADDRPLT,18) + RELOC_NUMBER (R_CKCORE_PCREL_IMM26BY2,19) + RELOC_NUMBER (R_CKCORE_PCREL_IMM16BY2,20) + RELOC_NUMBER (R_CKCORE_PCREL_IMM16BY4,21) + RELOC_NUMBER (R_CKCORE_PCREL_IMM10BY2,22) + RELOC_NUMBER (R_CKCORE_PCREL_IMM10BY4,23) + RELOC_NUMBER (R_CKCORE_ADDR_HI16,24) + RELOC_NUMBER (R_CKCORE_ADDR_LO16,25) + RELOC_NUMBER (R_CKCORE_GOTPC_HI16,26) + RELOC_NUMBER (R_CKCORE_GOTPC_LO16,27) + RELOC_NUMBER (R_CKCORE_GOTOFF_HI16,28) + RELOC_NUMBER (R_CKCORE_GOTOFF_LO16,29) + RELOC_NUMBER (R_CKCORE_GOT12,30) + RELOC_NUMBER (R_CKCORE_GOT_HI16,31) + RELOC_NUMBER (R_CKCORE_GOT_LO16,32) + RELOC_NUMBER (R_CKCORE_PLT12,33) + RELOC_NUMBER (R_CKCORE_PLT_HI16,34) + RELOC_NUMBER (R_CKCORE_PLT_LO16,35) + RELOC_NUMBER (R_CKCORE_ADDRGOT_HI16,36) + RELOC_NUMBER (R_CKCORE_ADDRGOT_LO16,37) + RELOC_NUMBER (R_CKCORE_ADDRPLT_HI16,38) + RELOC_NUMBER (R_CKCORE_ADDRPLT_LO16,39) + RELOC_NUMBER (R_CKCORE_PCREL_JSR_IMM26BY2,40) + RELOC_NUMBER (R_CKCORE_TOFFSET_LO16, 41) + RELOC_NUMBER (R_CKCORE_DOFFSET_LO16, 42) + RELOC_NUMBER (R_CKCORE_PCREL_IMM18BY2, 43) + RELOC_NUMBER (R_CKCORE_DOFFSET_IMM18, 44) + RELOC_NUMBER (R_CKCORE_DOFFSET_IMM18BY2, 45) + RELOC_NUMBER (R_CKCORE_DOFFSET_IMM18BY4, 46) + RELOC_NUMBER (R_CKCORE_GOTOFF_IMM18, 47) + RELOC_NUMBER (R_CKCORE_GOT_IMM18BY4, 48) + RELOC_NUMBER (R_CKCORE_PLT_IMM18BY4, 49) + RELOC_NUMBER (R_CKCORE_PCREL_IMM7BY4, 50) + RELOC_NUMBER (R_CKCORE_TLS_LE32, 51) + RELOC_NUMBER (R_CKCORE_TLS_IE32, 52) + RELOC_NUMBER (R_CKCORE_TLS_GD32, 53) + RELOC_NUMBER (R_CKCORE_TLS_LDM32, 54) + RELOC_NUMBER (R_CKCORE_TLS_LDO32, 55) + RELOC_NUMBER (R_CKCORE_TLS_DTPMOD32, 56) + RELOC_NUMBER (R_CKCORE_TLS_DTPOFF32, 57) + RELOC_NUMBER (R_CKCORE_TLS_TPOFF32, 58) + RELOC_NUMBER (R_CKCORE_PCREL_FLRW_IMM8BY4, 59) + RELOC_NUMBER (R_CKCORE_NOJSRI, 60) + RELOC_NUMBER (R_CKCORE_CALLGRAPH, 61) + RELOC_NUMBER (R_CKCORE_IRELATIVE, 62) + RELOC_NUMBER (R_CKCORE_PCREL_BLOOP_IMM4BY4, 63) + RELOC_NUMBER (R_CKCORE_PCREL_BLOOP_IMM12BY4, 64) +END_RELOC_NUMBERS (R_CKCORE_MAX) + +#endif /* _ELF_CSKY_H */ diff --git a/include/opcode/csky.h b/include/opcode/csky.h new file mode 100644 index 0000000..9b193b6 --- /dev/null +++ b/include/opcode/csky.h @@ -0,0 +1,110 @@ +/* C-SKY assembler/disassembler support. + Copyright (C) 2004-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3, or (at + your option) any later version. + + GDB and GAS are distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING3. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "dis-asm.h" + +/* The following bitmasks control instruction set architecture. */ +#define CSKYV1_ISA_E1 (1 << 0) +#define CSKYV2_ISA_E1 (1 << 1) +#define CSKYV2_ISA_1E2 (1 << 2) +#define CSKYV2_ISA_2E3 (1 << 3) +#define CSKYV2_ISA_3E7 (1 << 4) +#define CSKYV2_ISA_7E10 (1 << 5) +#define CSKYV2_ISA_3E3R1 (1 << 6) + +#define CSKY_ISA_TRUST (1 << 11) +#define CSKY_ISA_CACHE (1 << 12) +#define CSKY_ISA_NVIC (1 << 13) +#define CSKY_ISA_CP (1 << 14) +#define CSKY_ISA_MP (1 << 15) +#define CSKY_ISA_MP_1E2 (1 << 16) +#define CSKY_ISA_JAVA (1 << 17) +#define CSKY_ISA_MAC (1 << 18) +#define CSKY_ISA_MAC_DSP (1 << 19) + +/* Base ISA for csky v1 and v2. */ +#define CSKY_ISA_DSP (1 << 20) +#define CSKY_ISA_DSP_1E2 (1 << 21) +#define CSKY_ISA_DSP_ENHANCE (1 << 22) + +/* Base float instruction (803f & 810f). */ +#define CSKY_ISA_FLOAT_E1 (1 << 25) +/* M_FLOAT support (810f). */ +#define CSKY_ISA_FLOAT_1E2 (1 << 26) +/* 803 support (803f). */ +#define CSKY_ISA_FLOAT_1E3 (1 << 27) +/* 807 support (803f & 807f). */ +#define CSKY_ISA_FLOAT_3E4 (1 << 28) +/* Vector DSP support. */ +#define CSKY_ISA_VDSP (1 << 29) + +/* The following bitmasks control cpu architecture for CSKY. */ +#define CSKY_ABI_V1 (1 << 28) +#define CSKY_ABI_V2 (2 << 28) +#define CSKY_ARCH_MASK 0x0000001F +#define CSKY_ABI_MASK 0xF0000000 + +#define CSKY_ARCH_510 0x1 +#define CSKY_ARCH_610 0x2 +#define CSKY_ARCH_801 0xa +#define CSKY_ARCH_802 0x10 +#define CSKY_ARCH_803 0x9 +#define CSKY_ARCH_807 0x6 +#define CSKY_ARCH_810 0x8 + +#define CSKY_ARCH_MAC (1 << 15) +#define CSKY_ARCH_DSP (1 << 14) +#define CSKY_ARCH_FLOAT (1 << 13) +#define CSKY_ARCH_SIMD (1 << 12) +#define CSKY_ARCH_CP (1 << 11) +#define CSKY_ARCH_MP (1 << 10) +#define CSKY_ARCH_CACHE (1 << 9) +#define CSKY_ARCH_JAVA (1 << 8) +#define CSKY_ARCH_APS (1 << 7) + +#define IS_CSKY_V1(a) \ + (((a) & CSKY_ABI_MASK) == CSKY_ABI_V1) +#define IS_CSKY_V2(a) \ + (((a) & CSKY_ABI_MASK) == CSKY_ABI_V2) +#define IS_CSKY_ARCH_V1(a) \ + (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_510 \ + || ((a) & CSKY_ARCH_MASK) == CSKY_ARCH_610) +#define IS_CSKY_ARCH_V2(a) \ + (!(IS_CSKY_ARCH_V1 (a))) + +#define IS_CSKY_ARCH_510(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_510) +#define IS_CSKY_ARCH_610(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_610) +#define IS_CSKY_ARCH_801(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_801) +#define IS_CSKY_ARCH_802(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_802) +#define IS_CSKY_ARCH_803(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_803) +#define IS_CSKY_ARCH_807(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_807) +#define IS_CSKY_ARCH_810(a) (((a) & CSKY_ARCH_MASK) == CSKY_ARCH_810) + +#define CPU_ARCH_MASK \ + (CSKY_ARCH_JAVA | CSKY_ARCH_FLOAT | CSKY_ARCH_DSP | CSKY_ARCH_MASK) + +#ifdef __cplusplus +extern "C" { +#endif +extern int print_insn_csky (bfd_vma memaddr, struct disassemble_info *info); +#ifdef __cplusplus +} +#endif diff --git a/ld/ChangeLog b/ld/ChangeLog index 0f3906b..60deb47 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,18 @@ +2018-07-30 Andrew Jenner <andrew@codesourcery.com> + + * Makefile.am (ALL_EMULATION_SOURCES): Add C-SKY emulations. + (ecskyelf.c, ecskyelf_linux.c): New rules. + * Makefile.in: Regenerated. + * configure.tgt: Add C-SKY. + * emulparams/cskyelf.sh: New file. + * emulparams/cskyelf_linux.sh: New file. + * emultempl/cskyelf.em: New file. + * gen-doc.texi: Add C-SKY. + * ld.texi: Likewise. + (Options specific to C-SKY targets): New section. + * testsuite/ld-csky/*: New tests. + * NEWS: Mention the support. + 2018-07-30 Nick Clifton <nickc@redhat.com> * scripttempl/elf.sc: Place .gnu.build.attributes sections with diff --git a/ld/Makefile.am b/ld/Makefile.am index d86ad09..7ae1c53 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am @@ -209,6 +209,8 @@ ALL_EMULATION_SOURCES = \ ecrisaout.c \ ecriself.c \ ecrislinux.c \ + ecskyelf.c \ + ecskyelf_linux.c \ ed10velf.c \ ed30v_e.c \ ed30v_o.c \ @@ -876,6 +878,12 @@ ecriself.c: $(srcdir)/emulparams/criself.sh \ ecrislinux.c: $(srcdir)/emulparams/crislinux.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +ecskyelf.c: $(srcdir)/emulparams/cskyelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + +ecskyelf_linux.c: $(srcdir)/emulparams/cskyelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ed10velf.c: $(srcdir)/emulparams/d10velf.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elfd10v.sc ${GEN_DEPENDS} diff --git a/ld/Makefile.in b/ld/Makefile.in index 4792b2b..bfb5599 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in @@ -695,6 +695,8 @@ ALL_EMULATION_SOURCES = \ ecrisaout.c \ ecriself.c \ ecrislinux.c \ + ecskyelf.c \ + ecskyelf_linux.c \ ed10velf.c \ ed30v_e.c \ ed30v_o.c \ @@ -1256,6 +1258,8 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ecrisaout.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ecriself.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ecrislinux.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ecskyelf.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ecskyelf_linux.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ed10velf.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ed30v_e.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ed30v_o.Po@am__quote@ @@ -2477,6 +2481,12 @@ ecriself.c: $(srcdir)/emulparams/criself.sh \ ecrislinux.c: $(srcdir)/emulparams/crislinux.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} +ecskyelf.c: $(srcdir)/emulparams/cskyelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + +ecskyelf_linux.c: $(srcdir)/emulparams/cskyelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} + ed10velf.c: $(srcdir)/emulparams/d10velf.sh \ $(ELF_DEPS) $(srcdir)/scripttempl/elfd10v.sc ${GEN_DEPENDS} @@ -1,5 +1,7 @@ -*- text -*- +* Add support for the C-SKY processor series. + Changes in 2.31: * Speed up direct linking with DLLs for Cygwin and Mingw targets. diff --git a/ld/configure.tgt b/ld/configure.tgt index fad8b2e..e0e05b8 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -196,6 +196,10 @@ cris-*-* | crisv32-*-*) targ_emul=criself ;; crx-*-elf*) targ_emul=elf32crx ;; + +csky-*-elf*) targ_emul=cskyelf ;; +csky-*-linux*) targ_emul=cskyelf_linux ;; + d10v-*-*) targ_emul=d10velf ;; d30v-*-*ext*) targ_emul=d30v_e; targ_extra_emuls="d30velf d30v_o" ;; d30v-*-*onchip*) targ_emul=d30v_o; targ_extra_emuls="d30velf d30v_e" ;; diff --git a/ld/emulparams/cskyelf.sh b/ld/emulparams/cskyelf.sh new file mode 100644 index 0000000..218951c --- /dev/null +++ b/ld/emulparams/cskyelf.sh @@ -0,0 +1,34 @@ +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-csky-little" +BIG_OUTPUT_FORMAT="elf32-csky-big" +LITTLE_OUTPUT_FORMAT="elf32-csky-little" +NO_REL_RELOCS=yes +PAGE_SIZE=0x1000 +TARGET_PAGE_SIZE=0x400 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +TEXT_START_ADDR=0x8000 +CHECK_RELOCS_AFTER_OPEN_INPUT=yes +NONPAGED_TEXT_START_ADDR=0 +ARCH=csky +EMBEDDED=yes +EXTRA_EM_FILE=cskyelf + +# There is a problem with the NOP value - it must work for both +# big endian and little endian systems. Unfortunately there is +# no symmetrical mcore opcode that functions as a noop. The +# chosen solution is to use "tst r0, r14". This is a symmetrical +# value, and apart from the corruption of the C bit, it has no other +# side effects. Since the carry bit is never tested without being +# explicitly set first, and since the NOP code is only used as a +# fill value between independently viable pieces of code, it should +# not matter. +NOP=0 + +ENTRY=__start +OTHER_BSS_SYMBOLS="__bss_start__ = . ;" +OTHER_BSS_END_SYMBOLS="__bss_end__ = . ;" + +# This sets the stack to the top of the simulator memory (2^19 bytes). +# STACK_ADDR=0x80000 + +TEMPLATE_NAME=elf32 diff --git a/ld/emulparams/cskyelf_linux.sh b/ld/emulparams/cskyelf_linux.sh new file mode 100644 index 0000000..118be1a --- /dev/null +++ b/ld/emulparams/cskyelf_linux.sh @@ -0,0 +1,36 @@ +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-csky-little" +BIG_OUTPUT_FORMAT="elf32-csky-big" +LITTLE_OUTPUT_FORMAT="elf32-csky-little" +NO_REL_RELOCS=yes +TARGET_PAGE_SIZE=0x400 +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" +COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" +CHECK_RELOCS_AFTER_OPEN_INPUT=yes +TEXT_START_ADDR=0x8000 +NONPAGED_TEXT_START_ADDR=0 +ARCH=csky +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes + +# There is a problem with the NOP value - it must work for both +# big endian and little endian systems. Unfortunately there is +# no symmetrical mcore opcode that functions as a noop. The +# chosen solution is to use "tst r0, r14". This is a symmetrical +# value, and apart from the corruption of the C bit, it has no other +# side effects. Since the carry bit is never tested without being +# explicitly set first, and since the NOP code is only used as a +# fill value between independently viable pieces of code, it should +# not matter. +NOP=0 + +OTHER_BSS_SYMBOLS="__bss_start__ = . ;" +OTHER_BSS_END_SYMBOLS="__bss_end__ = . ;" + +# This sets the stack to the top of the simulator memory (2^19 bytes). +# STACK_ADDR=0x80000 + +TEMPLATE_NAME=elf32 +GENERATE_SHLIB_SCRIPT=yes +GENERATE_COMBRELOC_SCRIPT=yes +EXTRA_EM_FILE=cskyelf diff --git a/ld/emultempl/cskyelf.em b/ld/emultempl/cskyelf.em new file mode 100644 index 0000000..cd4c3fa --- /dev/null +++ b/ld/emultempl/cskyelf.em @@ -0,0 +1,355 @@ +# This shell script emits a C file. -*- C -*- +# Copyright (C) 2013-2018 Free Software Foundation, Inc. +# +# This file is part of GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + +# This file is sourced from elf32.em, and defines extra C-SKY ELF +# specific routines. +# +fragment <<EOF + +#include "ldctor.h" +#include "elf/csky.h" + +/* To use branch stub or not. */ +extern bfd_boolean use_branch_stub; + +/* Fake input file for stubs. */ +static lang_input_statement_type *stub_file; + +/* Whether we need to call gldcsky_layout_sections_again. */ +static int need_laying_out = 0; + +/* Maximum size of a group of input sections that can be handled by + one stub section. A value of +/-1 indicates the bfd back-end + should use a suitable default size. */ +static bfd_signed_vma group_size = 1; + +struct hook_stub_info +{ + lang_statement_list_type add; + asection *input_section; +}; + +/* Traverse the linker tree to find the spot where the stub goes. */ +static bfd_boolean +hook_in_stub (struct hook_stub_info *info, lang_statement_union_type **lp) +{ + lang_statement_union_type *l; + bfd_boolean ret; + + for (l = *lp; l != NULL; lp = &l->header.next, l = *lp) + switch (l->header.type) + { + case lang_constructors_statement_enum: + ret = hook_in_stub (info, &constructor_list.head); + if (ret) + return ret; + break; + + case lang_output_section_statement_enum: + ret = hook_in_stub (info, + &l->output_section_statement.children.head); + if (ret) + return ret; + break; + + case lang_wild_statement_enum: + ret = hook_in_stub (info, &l->wild_statement.children.head); + if (ret) + return ret; + break; + + case lang_group_statement_enum: + ret = hook_in_stub (info, &l->group_statement.children.head); + if (ret) + return ret; + break; + + case lang_input_section_enum: + if (l->input_section.section == info->input_section) + { + /* We've found our section. Insert the stub immediately + after its associated input section. */ + *(info->add.tail) = l->header.next; + l->header.next = info->add.head; + return TRUE; + } + break; + + case lang_data_statement_enum: + case lang_reloc_statement_enum: + case lang_object_symbols_statement_enum: + case lang_output_statement_enum: + case lang_target_statement_enum: + case lang_input_statement_enum: + case lang_assignment_statement_enum: + case lang_padding_statement_enum: + case lang_address_statement_enum: + case lang_fill_statement_enum: + break; + + default: + FAIL (); + break; + } + + return FALSE; +} +EOF + +case ${target} in + csky-*-linux-*) +fragment <<EOF +/* This is a convenient point to tell BFD about target specific flags. + After the output has been created, but before inputs are read. */ +static void +csky_elf_create_output_section_statements (void) +{ + use_branch_stub = FALSE; +} +EOF + ;; + *) +fragment <<EOF +/* This is a convenient point to tell BFD about target specific flags. + After the output has been created, but before inputs are read. */ +static void +csky_elf_create_output_section_statements (void) +{ + /* If don't use branch stub, just do not emit stub_file. */ + if (use_branch_stub == FALSE) + return; + stub_file = lang_add_input_file ("linker stubs", + lang_input_file_is_fake_enum, NULL); + stub_file->the_bfd = bfd_create ("linker stubs", link_info.output_bfd); + if (stub_file->the_bfd == NULL + || !bfd_set_arch_mach (stub_file->the_bfd, + bfd_get_arch (link_info.output_bfd), + bfd_get_mach (link_info.output_bfd))) + { + einfo (_("%F%P: can not create BFD: %E\n")); + return; + } + + stub_file->the_bfd->flags |= BFD_LINKER_CREATED; + ldlang_add_file (stub_file); +} +EOF + ;; +esac + +fragment <<EOF +/* Call-back for elf32_csky_size_stubs. */ + +/* Create a new stub section, and arrange for it to be linked + immediately after INPUT_SECTION. */ +static asection * +elf32_csky_add_stub_section (const char *stub_sec_name, + asection *input_section) +{ + asection *stub_sec; + flagword flags; + asection *output_section; + const char *secname; + lang_output_section_statement_type *os; + struct hook_stub_info info; + + flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE + | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP); + stub_sec = bfd_make_section_anyway_with_flags (stub_file->the_bfd, + stub_sec_name, flags); + if (stub_sec == NULL) + goto err_ret; + + bfd_set_section_alignment (stub_file->the_bfd, stub_sec, 3); + + output_section = input_section->output_section; + secname = bfd_get_section_name (output_section->owner, output_section); + os = lang_output_section_find (secname); + + info.input_section = input_section; + lang_list_init (&info.add); + lang_add_section (&info.add, stub_sec, NULL, os); + + if (info.add.head == NULL) + goto err_ret; + + if (hook_in_stub (&info, &os->children.head)) + return stub_sec; + +err_ret: + einfo (_("%X%P: can not make stub section: %E\n")); + return NULL; +} + +/* Another call-back for elf_csky_size_stubs. */ +static void +gldcsky_layout_sections_again (void) +{ + /* If we have changed sizes of the stub sections, then we need + to recalculate all the section offsets. This may mean we need to + add even more stubs. */ + gld${EMULATION_NAME}_map_segments (TRUE); + need_laying_out = -1; +} + +static void +build_section_lists (lang_statement_union_type *statement) +{ + if (statement->header.type == lang_input_section_enum) + { + asection *i = statement->input_section.section; + + if (i->sec_info_type != SEC_INFO_TYPE_JUST_SYMS + && (i->flags & SEC_EXCLUDE) == 0 + && i->output_section != NULL + && i->output_section->owner == link_info.output_bfd) + elf32_csky_next_input_section (&link_info, i); + } +} + +static void +gld${EMULATION_NAME}_after_allocation (void) +{ + /* bfd_elf32_discard_info just plays with debugging sections, + ie. doesn't affect any code, so we can delay resizing the + sections. It's likely we'll resize everything in the process of + adding stubs. */ + if (bfd_elf_discard_info (link_info.output_bfd, &link_info)) + need_laying_out = 1; + + /* If generating a relocatable output file, then we don't + have to examine the relocs. */ + + if (stub_file != NULL && !bfd_link_relocatable (&link_info)) + { + int ret = elf32_csky_setup_section_lists (link_info.output_bfd, + &link_info); + + if (ret < 0) + { + einfo (_("%X%P: could not compute sections lists for stub generation: %E\n")); + return; + } + else if (ret != 0) + { + lang_for_each_statement (build_section_lists); + + /* Call into the BFD backend to do the real work. */ + if (! elf32_csky_size_stubs (link_info.output_bfd, + stub_file->the_bfd, + &link_info, + group_size, + &elf32_csky_add_stub_section, + &gldcsky_layout_sections_again)) + { + einfo (_("%X%P: cannot size stub section: %E\n")); + return; + } + } + } + + if (need_laying_out != -1) + gld${EMULATION_NAME}_map_segments (need_laying_out); +} + +static void +gld${EMULATION_NAME}_finish (void) +{ + if (stub_file != NULL + && !bfd_link_relocatable (&link_info) + && stub_file->the_bfd->sections != NULL + && !elf32_csky_build_stubs (&link_info)) + einfo (_("%X%P: cannot build stubs: %E\n")); + finish_default (); +} + +/* Avoid processing the fake stub_file in vercheck, stat_needed and + check_needed routines. */ + +static void (*real_func) (lang_input_statement_type *); + +static void csky_for_each_input_file_wrapper (lang_input_statement_type *l) +{ + if (l != stub_file) + (*real_func) (l); +} + +static void +csky_lang_for_each_input_file (void (*func) (lang_input_statement_type *)) +{ + real_func = func; + lang_for_each_input_file (&csky_for_each_input_file_wrapper); +} + +#define lang_for_each_input_file csky_lang_for_each_input_file + +EOF + +# This code gets inserted into the generic elf32.sc linker script +# and allows us to define our own command line switches. +case ${target} in + csky-*-linux-*) + ;; + + *) +PARSE_AND_LIST_PROLOGUE=' +#define OPTION_BRANCH_STUB 301 +#define OPTION_NO_BRANCH_STUB 302 +#define OPTION_STUBGROUP_SIZE 303 +' + +PARSE_AND_LIST_LONGOPTS=' + {"branch-stub", no_argument, NULL, OPTION_BRANCH_STUB}, + {"no-branch-stub", no_argument, NULL, OPTION_NO_BRANCH_STUB}, + {"stub-group-size", required_argument, NULL, OPTION_STUBGROUP_SIZE}, +' +PARSE_AND_LIST_OPTIONS=' + fprintf (file, _(" --[no-]branch-stub\n")); + fprintf (file, _("\t\t\tDisable/enable use of stubs to expand branch " + "instructions that cannot reach the target.\n")); + fprintf (file, _(" --stub-group-size=N\n")); + fprintf (file, _("\t\t\tMaximum size of a group of input sections " + "handled by one stub section.")); +' + +PARSE_AND_LIST_ARGS_CASES=' + case OPTION_BRANCH_STUB: + use_branch_stub = TRUE; + break; + case OPTION_NO_BRANCH_STUB: + use_branch_stub = FALSE; + break; + + case OPTION_STUBGROUP_SIZE: + { + const char *end; + + group_size = bfd_scan_vma (optarg, &end, 0); + if (*end) + einfo (_("%F%P: invalid number `%s'\''\n"), optarg); + } + break; +' + ;; +esac + +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=csky_elf_create_output_section_statements +LDEMUL_FINISH=gld${EMULATION_NAME}_finish diff --git a/ld/gen-doc.texi b/ld/gen-doc.texi index 1b80ee6..1712d4d 100644 --- a/ld/gen-doc.texi +++ b/ld/gen-doc.texi @@ -8,6 +8,7 @@ @c 2. Specific target machines @set ARM @set C6X +@set CSKY @set H8300 @set HPPA @set I960 @@ -21,6 +21,7 @@ @set GENERIC @set ARM @set C6X +@set CSKY @set H8300 @set HPPA @set M68HC11 @@ -3008,6 +3009,36 @@ exidx entries in frame unwind info. @c man end @end ifset +@ifset CSKY +@subsection Options specific to C-SKY targets + +@c man begin OPTIONS + +@table @gcctabopt + +@kindex --branch-stub on C-SKY +@item --branch-stub +This option enables linker branch relaxation by inserting branch stub +sections when needed to extend the range of branches. This option is +usually not required since C-SKY supports branch and call instructions that +can access the full memory range and branch relaxation is normally handled by +the compiler or assembler. + +@kindex --stub-group-size on C-SKY +@item --stub-group-size=@var{N} +This option allows finer control of linker branch stub creation. +It sets the maximum size of a group of input sections that can +be handled by one stub section. A negative value of @var{N} locates +stub sections after their branches, while a positive value allows stub +sections to appear either before or after the branches. Values of +@samp{1} or @samp{-1} indicate that the +linker should choose suitable defaults. + +@end table + +@c man end +@end ifset + @ifset M68HC11 @subsection Options specific to Motorola 68HC11 and 68HC12 targets diff --git a/ld/testsuite/ld-csky/csky.exp b/ld/testsuite/ld-csky/csky.exp new file mode 100644 index 0000000..94a769f --- /dev/null +++ b/ld/testsuite/ld-csky/csky.exp @@ -0,0 +1,15 @@ +if { ! [istarget csky-*-*] } { + return +} + +set linux_gnu [expr [istarget csky*-*-linux*]] + +foreach test [lsort [glob -nocomplain $srcdir/$subdir/*.d]] { + + if { ! $linux_gnu && ([string match "$srcdir/$subdir/tls-*.d" $test] + || [string match "$srcdir/$subdir/got*.d" $test]) } { + continue + } + + run_dump_test [file rootname $test] +} diff --git a/ld/testsuite/ld-csky/data.d b/ld/testsuite/ld-csky/data.d new file mode 100644 index 0000000..21b2f27 --- /dev/null +++ b/ld/testsuite/ld-csky/data.d @@ -0,0 +1,18 @@ +#name: GB(r28) relative .data section references +#source: data.s +#source: data_section.s +#ld: -e __start +#objdump: -dr + +.*: file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <__start>: + [0-9a-f]+: cd400004 lrs.b r10, \[0x4\] // the offset is based on .data + [0-9a-f]+: cd440002 lrs.h r10, \[0x2\] // the offset is based on .data + [0-9a-f]+: cd480001 lrs.w r10, \[0x1\] // the offset is based on .data + [0-9a-f]+: cd700004 srs.b r11, \[0x4\] // the offset is based on .data + [0-9a-f]+: cd740002 srs.h r11, \[0x2\] // the offset is based on .data + [0-9a-f]+: cd780001 srs.w r11, \[0x1\] // the offset is based on .data diff --git a/ld/testsuite/ld-csky/data.s b/ld/testsuite/ld-csky/data.s new file mode 100644 index 0000000..b5af989 --- /dev/null +++ b/ld/testsuite/ld-csky/data.s @@ -0,0 +1,10 @@ + .text + .global __start +__start: + lrs.b r10, [word1] + lrs.h r10, [word1] + lrs.w r10, [word1] + + srs.b r11, [word1] + srs.h r11, [word1] + srs.w r11, [word1] diff --git a/ld/testsuite/ld-csky/data_section.s b/ld/testsuite/ld-csky/data_section.s new file mode 100644 index 0000000..886561c --- /dev/null +++ b/ld/testsuite/ld-csky/data_section.s @@ -0,0 +1,7 @@ + .global word0, word1 + .data + .align 4 +word0: + .word 0xabcd1234 +word1: + .word 0xdeadbeef diff --git a/ld/testsuite/ld-csky/emit-relocs-1.d b/ld/testsuite/ld-csky/emit-relocs-1.d new file mode 100644 index 0000000..3cc05ac --- /dev/null +++ b/ld/testsuite/ld-csky/emit-relocs-1.d @@ -0,0 +1,37 @@ +#name: Emit relocs 1 +#source: emit-relocs-1a.s +#source: emit-relocs-1b.s +#ld: -q -T emit-relocs-1.ld +#objdump: -sr + +.*: file format .* + +RELOCATION RECORDS FOR \[\.data\]: +OFFSET TYPE VALUE * +00000000 R_CKCORE_ADDR32 \.data +00000004 R_CKCORE_ADDR32 \.data\+0x00001000 +00000008 R_CKCORE_ADDR32 \.merge1\+0x00000002 +0000000c R_CKCORE_ADDR32 \.merge2 +00000010 R_CKCORE_ADDR32 \.merge3 +00000014 R_CKCORE_ADDR32 \.merge3\+0x00000004 +00000020 R_CKCORE_ADDR32 \.data\+0x00000020 +00000024 R_CKCORE_ADDR32 \.data\+0x00001020 +00000028 R_CKCORE_ADDR32 \.merge1 +0000002c R_CKCORE_ADDR32 \.merge2\+0x00000002 +00000030 R_CKCORE_ADDR32 \.merge3\+0x00000008 +00000034 R_CKCORE_ADDR32 \.merge3\+0x00000004 + + +Contents of section \.text: + 80000 036c .* +Contents of section \.merge1: + 80400 666c7574 74657200 flutter.* +Contents of section \.merge2: + 80800 74617374 696e6700 tasting.* +Contents of section \.merge3: + 80c00 00010000 00020000 00030000 .* +Contents of section \.data: + 81000 00100800 00200800 02040800 00080800 .* + 81010 000c0800 040c0800 00000000 00000000 .* + 81020 20100800 20200800 00040800 02080800 .* + 81030 080c0800 040c0800 .* diff --git a/ld/testsuite/ld-csky/emit-relocs-1.ld b/ld/testsuite/ld-csky/emit-relocs-1.ld new file mode 100644 index 0000000..574030b --- /dev/null +++ b/ld/testsuite/ld-csky/emit-relocs-1.ld @@ -0,0 +1,20 @@ +ENTRY(__start) +SECTIONS +{ + . = 0x80000; + .text : { *(.text) } + + . = ALIGN (0x400); + .merge1 : { *(.merge1) } + + . = ALIGN (0x400); + .merge2 : { *(.merge2) } + + . = ALIGN (0x400); + .merge3 : { *(.merge3) } + + . = ALIGN (0x400); + .data : { *(.data) } + + /DISCARD/ : { *(*) } +} diff --git a/ld/testsuite/ld-csky/emit-relocs-1a.s b/ld/testsuite/ld-csky/emit-relocs-1a.s new file mode 100644 index 0000000..89bbf99 --- /dev/null +++ b/ld/testsuite/ld-csky/emit-relocs-1a.s @@ -0,0 +1,24 @@ + .text + .align 4 + .globl __start +__start: + nop + + .section .merge1,"aMS",@progbits,1 +A: .string "utter" + + .section .merge2,"aMS",@progbits,1 +B: .string "tasting" + + .section .merge3,"aM",@progbits,4 +C: .4byte 0x100 +D: .4byte 0x200 + + .data + .align 4 +E: .4byte E + .4byte E + 0x1000 + .4byte A + .4byte B + .4byte C + .4byte D diff --git a/ld/testsuite/ld-csky/emit-relocs-1b.s b/ld/testsuite/ld-csky/emit-relocs-1b.s new file mode 100644 index 0000000..82229c1 --- /dev/null +++ b/ld/testsuite/ld-csky/emit-relocs-1b.s @@ -0,0 +1,18 @@ + .section .merge1,"aMS",@progbits,1 +A: .string "flutter" + + .section .merge2,"aMS",@progbits,1 +B: .string "sting" + + .section .merge3,"aM",@progbits,4 +C: .4byte 0x300 +D: .4byte 0x200 + + .data + .align 4 +E: .4byte E + .4byte E + 0x1000 + .4byte A + .4byte B + .4byte C + .4byte D diff --git a/ld/testsuite/ld-csky/got.d b/ld/testsuite/ld-csky/got.d new file mode 100644 index 0000000..ac997c4 --- /dev/null +++ b/ld/testsuite/ld-csky/got.d @@ -0,0 +1,29 @@ +#name: GOT/PLT Link test +#source: got.s +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 12 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 24 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ [0-9a-f]+ R_CKCORE_GLOB_DAT 00000000 var1 \+ 0 +[0-9a-f]+ [0-9a-f]+ R_CKCORE_GLOB_DAT 00000000 var2 \+ 0 + +Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ [0-9a-f]+ R_CKCORE_JUMP_SLO 00000000 bar \+ .* diff --git a/ld/testsuite/ld-csky/got.s b/ld/testsuite/ld-csky/got.s new file mode 100644 index 0000000..d5f3b72 --- /dev/null +++ b/ld/testsuite/ld-csky/got.s @@ -0,0 +1,19 @@ + .text + .align 2 + .global foo + .type foo, @function +foo: + push l0, lr, gb + lrw t1, .L2@GOTPC + grs gb, .L2 +.L2: + addu gb, gb, t1 + lrs.w a3, [var1@GOT] + ld.w l0, (a3, 0) + lrs.w a3, [var2@GOT] + ld.w a3, (a3, 0) + lrs.w a0, [bar@PLT] + addu l0, l0, a3 + jsr a0 + addu a0, l0, a0 + pop l0, lr, gb diff --git a/ld/testsuite/ld-csky/hilo16.d b/ld/testsuite/ld-csky/hilo16.d new file mode 100644 index 0000000..f2435c0 --- /dev/null +++ b/ld/testsuite/ld-csky/hilo16.d @@ -0,0 +1,14 @@ +#name: address hi16/lo16 relocations +#source: hilo16.s +#source: hilo16_symbol.s +#ld: -e __start +#objdump: -dr + +.*: file format .* + + +Disassembly of section .text: + +[0-9a-f]+ <__start>: + [0-9a-f]+: ea21dead movih r1, 57005 + [0-9a-f]+: ec21beef ori r1, r1, 48879 diff --git a/ld/testsuite/ld-csky/hilo16.s b/ld/testsuite/ld-csky/hilo16.s new file mode 100644 index 0000000..601fbc6 --- /dev/null +++ b/ld/testsuite/ld-csky/hilo16.s @@ -0,0 +1,7 @@ +# Test the hi16/lo16 relocations + +.text +.global __start +__start: + movih r1, (long_symbol) >> 16 + ori r1, r1, (long_symbol) & 0xffff diff --git a/ld/testsuite/ld-csky/hilo16_symbol.s b/ld/testsuite/ld-csky/hilo16_symbol.s new file mode 100644 index 0000000..e8fad0f --- /dev/null +++ b/ld/testsuite/ld-csky/hilo16_symbol.s @@ -0,0 +1,2 @@ +.global long_symbol +.set long_symbol, 0xDEADBEEF diff --git a/ld/testsuite/ld-csky/tls-gd-v1.d b/ld/testsuite/ld-csky/tls-gd-v1.d new file mode 100644 index 0000000..c2c8766 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-gd-v1.d @@ -0,0 +1,30 @@ +#name: TLS Global Dynamic link test (C-SKY V1) +#source: tls-gd-v1.s +#as: -mcpu=ck610 +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 12 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 24 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ [0-9a-f]+ R_CKCORE_TLS_DTPM 00000000 var \+ 0 +[0-9a-f]+ [0-9a-f]+ R_CKCORE_TLS_DTPO 00000000 var \+ 0 + +Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 0000040c R_CKCORE_JUMP_SLO 00000000 __tls_get_addr \+ .* diff --git a/ld/testsuite/ld-csky/tls-gd-v1.s b/ld/testsuite/ld-csky/tls-gd-v1.s new file mode 100644 index 0000000..617aac0 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-gd-v1.s @@ -0,0 +1,26 @@ + .global __tls_get_addr + .text + .align 2 + .global foo + .type foo, @function +foo: + subi sp, sp, 8 + st.w gb, (sp) + st.w r15, (sp, 4) + bsr .L2 +.L2: + lrw gb, .L2@GOTPC + addu gb, gb, r15 + lrw r7, __tls_get_addr@PLT + addu r7, r7, gb + ld.w r7, (r7) + bsr .LTLS0 +.LTLS0: + lrw r2, var@TLSGD32 + addu r2, r15 + jsr r7 + ld.w r2, (r2) + ld.w r15, (sp, 4) + ld.w gb, (sp) + addi sp, sp, 8 + jmp r15 diff --git a/ld/testsuite/ld-csky/tls-gd.d b/ld/testsuite/ld-csky/tls-gd.d new file mode 100644 index 0000000..2d5e1fc --- /dev/null +++ b/ld/testsuite/ld-csky/tls-gd.d @@ -0,0 +1,29 @@ +#name: TLS Global Dynamic link test +#source: tls-gd.s +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 12 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 24 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ [0-9a-f]+ R_CKCORE_TLS_DTPM 00000000 var \+ 0 +[0-9a-f]+ [0-9a-f]+ R_CKCORE_TLS_DTPO 00000000 var \+ 0 + +Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 0000040c R_CKCORE_JUMP_SLO 00000000 __tls_get_addr \+ .* diff --git a/ld/testsuite/ld-csky/tls-gd.s b/ld/testsuite/ld-csky/tls-gd.s new file mode 100644 index 0000000..8fe0e37 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-gd.s @@ -0,0 +1,20 @@ + .text + .global __tls_get_addr + .align 2 + .global foo + .type foo, @function +foo: + push lr, gb + lrw t1, .L2@GOTPC + grs gb, .L2 +.L2: + addu gb, gb, t1 + grs a2, .LTLS0 + lrw a3, __tls_get_addr@PLT +.LTLS0: + lrw a0, var@TLSGD32 + ldr.w a3, (gb, a3 << 0) + addu a0, a0, a2 + jsr a3 + ld.w a0, (a0, 0) + pop lr, gb diff --git a/ld/testsuite/ld-csky/tls-ie-v1.d b/ld/testsuite/ld-csky/tls-ie-v1.d new file mode 100644 index 0000000..1f5f446 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ie-v1.d @@ -0,0 +1,25 @@ +#name: TLS Initial Exec link test (C-SKY v1) +#source: tls-ie-v1.s +#as: -mcpu=ck610 +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 0 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 12 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 0000003a R_CKCORE_TLS_TPOF 0 diff --git a/ld/testsuite/ld-csky/tls-ie-v1.s b/ld/testsuite/ld-csky/tls-ie-v1.s new file mode 100644 index 0000000..7c72362 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ie-v1.s @@ -0,0 +1,29 @@ + .text + .section .tbss,"awT",@nobits + .align 2 + .type var, @object + .size var, 4 +var: + .word 0 + + .text + .align 2 + .global _start + .type _start, @function +_start: + subi sp, sp, 8 + st.w r15, (sp) + bsr .LTLS0 +.LTLS0: + lrw r7, var@GOTTPOFF + addu r7, r15 + ld.w r7, (r7) + bsr __read_tp + addu r7, r7, r2 + ld.w r2, (r7) + ld.w r15, (sp) + addi sp, sp, 8 + jmp r15 +__read_tp: + movi r2, 0 + jmp r15 diff --git a/ld/testsuite/ld-csky/tls-ie.d b/ld/testsuite/ld-csky/tls-ie.d new file mode 100644 index 0000000..45a8a11 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ie.d @@ -0,0 +1,24 @@ +#name: TLS Initial Exec link test +#source: tls-ie.s +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 0 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 12 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 0000003a R_CKCORE_TLS_TPOF 0 diff --git a/ld/testsuite/ld-csky/tls-ie.s b/ld/testsuite/ld-csky/tls-ie.s new file mode 100644 index 0000000..36def90 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ie.s @@ -0,0 +1,27 @@ + .text + .section .tbss,"awT",@nobits + .align 2 + .type var, @object + .size var, 4 +var: + .word 0 + + .text + .align 2 + .global _start + .type _start, @function +_start: + subi sp, sp, 4 + st.w l4, (sp, 0) + mov l4, sp +.LTLS0: + lrw a3, var@GOTTPOFF + grs a2, .LTLS0 + addu a3, a3, a2 + ld.w a3, (a3, 0) + ldr.w a3, (r31, a3 << 0) + mov a0, a3 + mov sp, l4 + ld.w l4, (sp, 0) + addi sp, sp, 4 + rts diff --git a/ld/testsuite/ld-csky/tls-ld-v1.d b/ld/testsuite/ld-csky/tls-ld-v1.d new file mode 100644 index 0000000..3aaa351 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ld-v1.d @@ -0,0 +1,29 @@ +#name: TLS Local Dynamic link test (C-SKY v1) +#source: tls-ld-v1.s +#as: -mcpu=ck610 +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 12 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 12 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 00000038 R_CKCORE_TLS_DTPM 0 + +Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 0000050c R_CKCORE_JUMP_SLO 00000000 __tls_get_addr \+ .* diff --git a/ld/testsuite/ld-csky/tls-ld-v1.s b/ld/testsuite/ld-csky/tls-ld-v1.s new file mode 100644 index 0000000..e0a8e76 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ld-v1.s @@ -0,0 +1,34 @@ + .global __tls_get_addr + .text + .align 2 + .global foo + .type foo, @function +foo: + subi sp, sp, 8 + st.w gb, (sp) + st.w r15, (sp, 4) + bsr .L2 +.L2: + lrw gb, .L2@GOTPC + addu gb, gb, r15 + lrw r7, __tls_get_addr@PLT + addu r7, r7, gb + ld.w r7, (r7) + bsr .LTLS0 +.LTLS0: + lrw r2, var@TLSLDM32 + addu r2, r15 + jsr r7 + lrw r7, var@TLSLDO32 + addu r2, r2, r7 + ld.w r15, (sp, 4) + ld.w gb, (sp) + addi sp, sp, 8 + jmp r15 + .size foo, .-foo + .section .tbss,"awT",@nobits + .align 2 + .type var, @object + .size var, 4 +var: + .fill 4, 1 diff --git a/ld/testsuite/ld-csky/tls-ld.d b/ld/testsuite/ld-csky/tls-ld.d new file mode 100644 index 0000000..3922152 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ld.d @@ -0,0 +1,28 @@ +#name: TLS Local Dynamic link test +#source: tls-ld.s +#ld: -shared --hash-style=sysv +#readelf: -d -r + +Dynamic section at offset 0x[0-9a-f]+ contains 13 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) .* + 0x00000005 \(STRTAB\) .* + 0x00000006 \(SYMTAB\) .* + 0x0000000a \(STRSZ\) .* \(bytes\) + 0x0000000b \(SYMENT\) .* \(bytes\) + 0x00000003 \(PLTGOT\) 0x[0-9a-f]+ + 0x00000002 \(PLTRELSZ\) 12 \(bytes\) + 0x00000014 \(PLTREL\) RELA + 0x00000017 \(JMPREL\) 0x[0-9a-f]+ + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 12 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 + +Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 00000038 R_CKCORE_TLS_DTPM 0 + +Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entry: + Offset Info Type Sym.Value Sym. Name \+ Addend +[0-9a-f]+ 0000050c R_CKCORE_JUMP_SLO 00000000 __tls_get_addr \+ .* diff --git a/ld/testsuite/ld-csky/tls-ld.s b/ld/testsuite/ld-csky/tls-ld.s new file mode 100644 index 0000000..3ad06ce --- /dev/null +++ b/ld/testsuite/ld-csky/tls-ld.s @@ -0,0 +1,28 @@ + .text + .global __tls_get_addr + .align 2 + .global foo + .type foo, @function +foo: + push lr, gb + lrw t1, .L2@GOTPC + grs gb, .L2 +.L2: + addu gb, gb, t1 + grs a3, .LTLS0 +.LTLS0: + lrw a0, .LANCHOR0@TLSLDM32 + addu a0, a0, a3 + lrs.w a3, [__tls_get_addr@PLT] + jsr a3 + lrw a3, .LANCHOR0@TLSLDO32 + addu a0, a0, a3 + pop lr, gb + .size foo, .-foo + .section .tbss,"awT",@nobits + .align 2 + .set .LANCHOR0,. + 0 + .type var, @object + .size var, 4 +var: + .fill 4, 1 diff --git a/ld/testsuite/ld-csky/tls-le-v1.d b/ld/testsuite/ld-csky/tls-le-v1.d new file mode 100644 index 0000000..034d5d9 --- /dev/null +++ b/ld/testsuite/ld-csky/tls-le-v1.d @@ -0,0 +1,14 @@ +#name: TLS Local Exec link test (C-SKY v1) +#source: tls-le-v1.s +#as: -mcpu=ck610 +#ld: +#objdump: -h + +.*: file format .* + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text .* + .* + 1 .tbss .* + .* diff --git a/ld/testsuite/ld-csky/tls-le-v1.s b/ld/testsuite/ld-csky/tls-le-v1.s new file mode 100644 index 0000000..b93521e --- /dev/null +++ b/ld/testsuite/ld-csky/tls-le-v1.s @@ -0,0 +1,29 @@ + .section .tbss,"awT",@nobits + .align 2 + .type var, @object + .size var, 4 +var: + .fill 4, 1 + .text + .align 2 + .global _start + .type _start, @function +_start: + subi sp, sp, 8 + st.w r15, (sp) + st.w r8, (sp, 4) + mov r8, sp + bsr __read_tp + mov r6, r2 + lrw r7, var@TPOFF + addu r7, r7, r6 + ld.w r7, (r7) + mov r2, r7 + mov sp, r8 + ld.w r15, (sp) + ld.w r8, (sp, 4) + addi sp, sp, 8 + jmp r15 +__read_tp: + movi r2, 0 + jmp r15 diff --git a/ld/testsuite/ld-csky/tls-le.d b/ld/testsuite/ld-csky/tls-le.d new file mode 100644 index 0000000..8a0d90f --- /dev/null +++ b/ld/testsuite/ld-csky/tls-le.d @@ -0,0 +1,13 @@ +#name: TLS Local Exec link test +#source: tls-le.s +#ld: +#objdump: -h + +.*: file format .* + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text .* + .* + 1 .tbss .* + .* diff --git a/ld/testsuite/ld-csky/tls-le.s b/ld/testsuite/ld-csky/tls-le.s new file mode 100644 index 0000000..240a59d --- /dev/null +++ b/ld/testsuite/ld-csky/tls-le.s @@ -0,0 +1,23 @@ + .text + .section .tbss,"awT",@nobits + .align 2 + .type var, @object + .size var, 4 +var: + .word 0 + + .text + .align 2 + .global _start + .type _start, @function +_start: + subi sp, sp, 4 + st.w l4, (sp, 0) + mov l4, sp + lrw a3, var@TPOFF + ldr.w a3, (r31, a3 << 0) + mov a0, a3 + mov sp, l4 + ld.w l4, (sp, 0) + addi sp, sp, 4 + rts diff --git a/ld/testsuite/ld-elf/merge.d b/ld/testsuite/ld-elf/merge.d index 3e3bcba..c0a8511 100644 --- a/ld/testsuite/ld-elf/merge.d +++ b/ld/testsuite/ld-elf/merge.d @@ -1,7 +1,7 @@ #source: merge.s #ld: -T merge.ld #objdump: -s -#xfail: bfin-*-* cr16-*-* cris*-*-* crx-*-* d10v-*-* d30v-*-* dlx-*-* +#xfail: bfin-*-* cr16-*-* cris*-*-* crx-*-* csky-*-* d10v-*-* d30v-*-* dlx-*-* #xfail: fr30-*-* frv-*-* ft32-*-* h8300-*-* hppa*64*-*-* ip2k-*-* iq2000-*-* #xfail: lm32-*-* m68hc11-*-* mcore-*-* mep-*-* metag-*-* mn102*-*-* ms1-*-* #xfail: nios2-*-* or32-*-* pj-*-* pru-*-* s12z-*-* score-*-* tic6x-*-* diff --git a/ld/testsuite/ld-elf/pr16496b.od b/ld/testsuite/ld-elf/pr16496b.od index 6fb54c1..f348ca2 100644 --- a/ld/testsuite/ld-elf/pr16496b.od +++ b/ld/testsuite/ld-elf/pr16496b.od @@ -1,3 +1,3 @@ #... -.* sd_get_seats@LIBSYSTEMD_209 +.* sd_get_seats@LIBSYSTEMD_209(\+0x.*)? #pass diff --git a/ld/testsuite/ld-elf/pr21884.d b/ld/testsuite/ld-elf/pr21884.d index 3d44ccf..c230924 100644 --- a/ld/testsuite/ld-elf/pr21884.d +++ b/ld/testsuite/ld-elf/pr21884.d @@ -3,7 +3,7 @@ #ld: -T pr21884.t #objdump: -b binary -s #xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* -#xfail: riscv*-*-* score-*-* v850-*-* +#xfail: riscv*-*-* score-*-* v850-*-* csky-*-* # Skip targets which can't change output format to binary. .*: file format binary diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp index 7604e53..d155c18 100644 --- a/ld/testsuite/ld-srec/srec.exp +++ b/ld/testsuite/ld-srec/srec.exp @@ -418,6 +418,9 @@ setup_xfail "bfin-*-linux-uclibc" # generate the format if need be). setup_xfail "tile*-*-*" +# The S-record linker is not supported for C-SKY. +setup_xfail "csky*-*-*" + run_srec_test $test1 "tmpdir/sr1.o tmpdir/sr2.o" # Now try linking a C++ program with global constructors and @@ -453,6 +456,7 @@ setup_xfail "*-*-cygwin*" "*-*-mingw*" "*-*-pe*" "*-*-winnt*" setup_xfail "score-*-*" setup_xfail "bfin-*-linux-uclibc" setup_xfail "tile*-*-*" +setup_xfail "csky*-*-*" run_srec_test $test2 "tmpdir/sr3.o" diff --git a/ld/testsuite/ld-unique/pr21529.d b/ld/testsuite/ld-unique/pr21529.d index fb63794..0e6332e 100644 --- a/ld/testsuite/ld-unique/pr21529.d +++ b/ld/testsuite/ld-unique/pr21529.d @@ -1,6 +1,6 @@ #ld: --oformat binary -T pr21529.ld -e main #objdump: -s -b binary -#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* +#xfail: aarch64*-*-* arm*-*-* avr-*-* ia64-*-* m68hc1*-*-* nds32*-*-* riscv*-*-* score-*-* v850-*-* csky-*-* # Skip targets which can't change output format to binary. #pass diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ff652dc..da38824 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2018-07-30 Andrew Jenner <andrew@codesourcery.com> + + * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c. + * Makefile.in: Regenerated. + * configure.ac: Add C-SKY. + * configure: Regenerated. + * csky-dis.c: New file. + * csky-opc.h: New file. + * disassemble.c (ARCH_csky): Define. + (disassembler, disassemble_init_for_target): Add case for ARCH_csky. + * disassemble.h (print_insn_csky, csky_get_disassembler): Declare. + 2018-07-27 Alan Modra <amodra@gmail.com> * ppc-opc.c (insert_sprbat): Correct function parameter and diff --git a/opcodes/Makefile.am b/opcodes/Makefile.am index a571f2b..53cd4b3 100644 --- a/opcodes/Makefile.am +++ b/opcodes/Makefile.am @@ -112,6 +112,7 @@ TARGET_LIBOPCODES_CFILES = \ cris-opc.c \ crx-dis.c \ crx-opc.c \ + csky-dis.c \ d10v-dis.c \ d10v-opc.c \ d30v-dis.c \ diff --git a/opcodes/Makefile.in b/opcodes/Makefile.in index 31f7bf5..4d9b818 100644 --- a/opcodes/Makefile.in +++ b/opcodes/Makefile.in @@ -503,6 +503,7 @@ TARGET_LIBOPCODES_CFILES = \ cris-opc.c \ crx-dis.c \ crx-opc.c \ + csky-dis.c \ d10v-dis.c \ d10v-opc.c \ d30v-dis.c \ @@ -907,6 +908,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cris-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crx-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/crx-opc.Plo@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/csky-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/d10v-dis.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/d10v-opc.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/d30v-dis.Plo@am__quote@ diff --git a/opcodes/configure b/opcodes/configure index a2e4393..29b4690 100755 --- a/opcodes/configure +++ b/opcodes/configure @@ -12925,6 +12925,7 @@ if test x${all_targets} = xfalse ; then bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; + bfd_csky_arch) ta="$ta csky-dis.lo" ;; bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; diff --git a/opcodes/configure.ac b/opcodes/configure.ac index d820dc9..d4e45f1 100644 --- a/opcodes/configure.ac +++ b/opcodes/configure.ac @@ -260,6 +260,7 @@ if test x${all_targets} = xfalse ; then bfd_cr16_arch) ta="$ta cr16-dis.lo cr16-opc.lo" ;; bfd_cris_arch) ta="$ta cris-dis.lo cris-opc.lo cgen-bitset.lo" ;; bfd_crx_arch) ta="$ta crx-dis.lo crx-opc.lo" ;; + bfd_csky_arch) ta="$ta csky-dis.lo" ;; bfd_d10v_arch) ta="$ta d10v-dis.lo d10v-opc.lo" ;; bfd_d30v_arch) ta="$ta d30v-dis.lo d30v-opc.lo" ;; bfd_dlx_arch) ta="$ta dlx-dis.lo" ;; diff --git a/opcodes/csky-dis.c b/opcodes/csky-dis.c new file mode 100644 index 0000000..9c3495f --- /dev/null +++ b/opcodes/csky-dis.c @@ -0,0 +1,1068 @@ +/* C-SKY disassembler. + Copyright (C) 1988-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "config.h" +#include <stdio.h> +#include <stdint.h> +#include "disassemble.h" +#include "elf-bfd.h" +#include "opcode/csky.h" +#include "libiberty.h" +#include "csky-opc.h" +#include "floatformat.h" + +#define CSKY_INST_TYPE unsigned long +#define HAS_SUB_OPERAND (unsigned int)0xffffffff + +enum sym_type +{ + CUR_TEXT, + CUR_DATA +}; + +struct csky_dis_info +{ + /* Mem to disassemble. */ + bfd_vma mem; + /* Disassemble info. */ + disassemble_info *info; + /* Opcode information. */ + struct csky_opcode_info const *opinfo; + /* The value of operand to show. */ + int value; + /* Whether to look up/print a symbol name. */ + int need_output_symbol; +} dis_info; + + +enum sym_type last_type; +int last_map_sym = 1; +bfd_vma last_map_addr = 0; + +/* Only for objdump tool. */ +#define INIT_MACH_FLAG 0xffffffff +#define BINARY_MACH_FLAG 0x0 + +static unsigned int mach_flag = INIT_MACH_FLAG; + +static void +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, + struct disassemble_info *info, + long given) +{ + switch (info->bytes_per_chunk) + { + case 1: + info->fprintf_func (info->stream, ".byte\t0x%02lx", given); + break; + case 2: + info->fprintf_func (info->stream, ".short\t0x%04lx", given); + break; + case 4: + info->fprintf_func (info->stream, ".long\t0x%08lx", given); + break; + default: + abort (); + } +} + +static int +get_sym_code_type (struct disassemble_info *info, + int n, + enum sym_type *sym_type) +{ + const char *name; + name = bfd_asymbol_name (info->symtab[n]); + if (name[0] == '$' && (name[1] == 't' || name[1] == 'd') + && (name[2] == 0 || name[2] == '.')) + { + *sym_type = ((name[1] == 't') ? CUR_TEXT : CUR_DATA); + return TRUE; + } + return FALSE; +} + +static int +csky_get_operand_mask (struct operand const *oprnd) +{ + int mask = 0; + if (oprnd->mask == HAS_SUB_OPERAND) + { + struct soperand *sop = (struct soperand *)oprnd; + mask |= csky_get_operand_mask (&sop->subs[0]); + mask |= csky_get_operand_mask (&sop->subs[1]); + return mask; + } + return oprnd->mask; +} + +static int +csky_get_mask (struct csky_opcode_info const *pinfo) +{ + int i = 0; + int mask = 0; + /* List type. */ + if (pinfo->operand_num == -1) + mask |= csky_get_operand_mask (&pinfo->oprnd.oprnds[i]); + else + for (; i < pinfo->operand_num; i++) + mask |= csky_get_operand_mask (&pinfo->oprnd.oprnds[i]); + + mask = ~mask; + return mask; +} + +static unsigned int +csky_chars_to_number (unsigned char * buf, int n) +{ + if (n == 0) + abort (); + int i; + int val = 0; + + if (dis_info.info->endian == BFD_ENDIAN_BIG) + while (n--) + val |= buf[n] << (n*8); + else + for (i = 0; i < n; i++) + val |= buf[i] << (i*8); + return val; +} + +static struct csky_opcode const *g_opcodeP; + +static struct csky_opcode const * +csky_find_inst_info (struct csky_opcode_info const **pinfo, + CSKY_INST_TYPE inst, int length) +{ + int i; + unsigned int mask; + struct csky_opcode const *p; + + p = g_opcodeP; + while (p->mnemonic) + { + /* Get the opcode mask. */ + for (i = 0; i < OP_TABLE_NUM; i++) + if (length == 2) + { + mask = csky_get_mask (&p->op16[i]); + if (mask != 0 && (inst & mask) == p->op16[i].opcode) + { + *pinfo = &p->op16[i]; + g_opcodeP = p; + return p; + } + } + else if (length == 4) + { + mask = csky_get_mask (&p->op32[i]); + if (mask != 0 + && ((unsigned long)(inst & mask) + == (unsigned long)p->op32[i].opcode)) + { + *pinfo = &p->op32[i]; + g_opcodeP = p; + return p; + } + } + p++; + } + + return NULL; +} + +static bfd_boolean +is_extern_symbol (struct disassemble_info *info, int addr) +{ + unsigned int rel_count = 0; + + if (info->section == NULL) + return 0; + if ((info->section->flags & SEC_RELOC) != 0) /* Fit .o file. */ + { + struct reloc_cache_entry *pt = info->section->relocation; + for (; rel_count < info->section->reloc_count; rel_count++, pt++) + if ((long unsigned int)addr == pt->address) + return TRUE; + return FALSE; + } + return FALSE; +} + + +/* Suppress printing of mapping symbols emitted by the assembler to mark + the beginning of code and data sequences. */ + +bfd_boolean +csky_symbol_is_valid (asymbol *sym, + struct disassemble_info *info ATTRIBUTE_UNUSED) +{ + const char *name; + + if (sym == NULL) + return FALSE; + name = bfd_asymbol_name (sym); + return name && *name != '$'; +} + +disassembler_ftype +csky_get_disassembler (bfd *abfd) +{ + if (abfd != NULL) + mach_flag = elf_elfheader (abfd)->e_flags; + return print_insn_csky; +} + +static int +csky_output_operand (char *str, struct operand const *oprnd, + CSKY_INST_TYPE inst, int reloc ATTRIBUTE_UNUSED) +{ + int ret = 0;; + int bit = 0; + int result = 0; + bfd_vma value; + int mask = oprnd->mask; + int max = 0; + char buf[128]; + + /* Get operand value with mask. */ + value = inst & mask; + for (; mask; mask >>= 1, value >>=1) + if (mask & 0x1) + { + result |= ((value & 0x1) << bit); + max |= (1 << bit); + bit++; + } + value = result; + + /* Here is general instructions that have no reloc. */ + switch (oprnd->type) + { + case OPRND_TYPE_CTRLREG: + if (IS_CSKY_V1 (mach_flag)) + { + /* In V1 only cr0-cr12 have alias names. */ + if (value <= 12) + strcat (str, csky_ctrl_regs[value].name); + /* Others using crn(n > 12). */ + else if (value <= 30) + { + sprintf (buf, "cr%d", (int)value); + strcat (str, buf); + } + else + return -1; + } + else + { + int sel; + int crx; + sel = value >> 5; + crx = value & 0x1f; + sprintf (buf, "cr<%d, %d>", crx, sel); + strcat (str, buf); + } + break; + case OPRND_TYPE_DUMMY_REG: + mask = dis_info.opinfo->oprnd.oprnds[0].mask; + value = inst & mask; + for (; mask; mask >>= 1, value >>=1) + if (mask & 0x1) + { + result |= ((value & 0x1) << bit); + bit++; + } + value = result; + strcat (str, csky_general_reg[value]); + break; + case OPRND_TYPE_GREG0_7: + case OPRND_TYPE_GREG0_15: + case OPRND_TYPE_GREG16_31: + case OPRND_TYPE_REGnsplr: + case OPRND_TYPE_AREG: + if (IS_CSKY_V2 (mach_flag) && value == 14) + strcat (str, "sp"); + else + strcat (str, csky_general_reg[value]); + dis_info.value = value; + break; + case OPRND_TYPE_CPREG: + strcat (str, csky_cp_reg[value]); + break; + case OPRND_TYPE_FREG: + sprintf (buf, "fr%d", (int)value); + strcat (str, buf); + break; + case OPRND_TYPE_VREG: + sprintf (buf, "vr%d", (int)value); + strcat (str, buf); + break; + case OPRND_TYPE_CPCREG: + strcat (str, csky_cp_creg[value]); + break; + case OPRND_TYPE_CPIDX: + strcat (str, csky_cp_idx[value]); + break; + case OPRND_TYPE_IMM2b_JMPIX: + value = (value + 2) << 3; + sprintf (buf, "%d", (int)value); + strcat (str, buf); + break; + case OPRND_TYPE_IMM_LDST: + case OPRND_TYPE_IMM_FLDST: + value <<= oprnd->shift; + sprintf (buf, "0x%x", (unsigned int)value); + strcat (str, buf); + break; + case OPRND_TYPE_IMM7b_LS2: + case OPRND_TYPE_IMM8b_LS2: + sprintf (buf, "%d", (int)(value << 2)); + strcat (str, buf); + ret = 0; + break; + case OPRND_TYPE_IMM5b_BMASKI: + if ((value != 0) && (value > 31 || value < 8)) + { + ret = -1; + break; + } + sprintf (buf, "%d", (int)value); + strcat (str, buf); + ret = 0; + break; + case OPRND_TYPE_IMM5b_1_31: + if (value > 31 || value < 1) + { + ret = -1; + break; + } + sprintf (buf, "%d", (int)value); + strcat (str, buf); + ret = 0; + break; + case OPRND_TYPE_IMM5b_7_31: + if (value > 31 || value < 7) + { + ret = -1; + break; + } + sprintf (buf, "%d", (int)value); + strcat (str, buf); + ret = 0; + break; + case OPRND_TYPE_MSB2SIZE: + case OPRND_TYPE_LSB2SIZE: + { + static int size; + if (oprnd->type == OPRND_TYPE_MSB2SIZE) + size = value; + else + { + str[strlen (str) - 2] = '\0'; + sprintf (buf, "%d, %d", (int)(size + value), (int)value); + strcat (str, buf); + } + break; + } + case OPRND_TYPE_IMM1b: + case OPRND_TYPE_IMM2b: + case OPRND_TYPE_IMM4b: + case OPRND_TYPE_IMM5b: + case OPRND_TYPE_IMM7b: + case OPRND_TYPE_IMM8b: + case OPRND_TYPE_IMM12b: + case OPRND_TYPE_IMM15b: + case OPRND_TYPE_IMM16b: + case OPRND_TYPE_IMM16b_MOVIH: + case OPRND_TYPE_IMM16b_ORI: + sprintf (buf, "%d", (int)value); + strcat (str, buf); + ret = 0; + break; + case OPRND_TYPE_OFF8b: + case OPRND_TYPE_OFF16b: + { + unsigned char ibytes[4]; + int shift = oprnd->shift; + int status; + unsigned int mem_val; + + dis_info.info->stop_vma = 0; + + value = ((dis_info.mem + (value << shift) + + ((IS_CSKY_V1 (mach_flag)) ? 2 : 0)) + & 0xfffffffc); + status = dis_info.info->read_memory_func (value, ibytes, 4, + dis_info.info); + if (status != 0) + { + dis_info.info->memory_error_func (status, dis_info.mem, + dis_info.info); + return -1; + } + mem_val = csky_chars_to_number (ibytes, 4); + /* Remove [] around literal value to match ABI syntax. */ + sprintf (buf, "0x%X", mem_val); + strcat (str, buf); + /* For jmpi/jsri, we'll try to get a symbol for the target. */ + if (dis_info.info->print_address_func && mem_val != 0) + { + dis_info.value = mem_val; + dis_info.need_output_symbol = 1; + } + else + { + sprintf (buf, "\t// from address pool at 0x%x", + (unsigned int)value); + strcat (str, buf); + } + break; + } + case OPRND_TYPE_BLOOP_OFF4b: + case OPRND_TYPE_BLOOP_OFF12b: + case OPRND_TYPE_OFF11b: + case OPRND_TYPE_OFF16b_LSL1: + case OPRND_TYPE_IMM_OFF18b: + case OPRND_TYPE_OFF26b: + { + int shift = oprnd->shift; + if (value & ((max >> 1) + 1)) + value |= ~max; + if (is_extern_symbol (dis_info.info, dis_info.mem)) + value = 0; + else if (IS_CSKY_V1 (mach_flag)) + value = dis_info.mem + 2 + (value << shift); + else + value = dis_info.mem + (value << shift); + dis_info.need_output_symbol = 1; + dis_info.value= value; + sprintf (buf, "0x%x", (unsigned int)value); + strcat (str, buf); + break; + } + case OPRND_TYPE_CONSTANT: + case OPRND_TYPE_FCONSTANT: + { + int shift = oprnd->shift; + char ibytes[8]; + int status; + bfd_vma addr; + int nbytes; + + dis_info.info->stop_vma = 0; + value <<= shift; + + if (IS_CSKY_V1 (mach_flag)) + addr = (dis_info.mem + 2 + value) & 0xfffffffc; + else + addr = (dis_info.mem + value) & 0xfffffffc; + + if (oprnd->type == OPRND_TYPE_FCONSTANT + && dis_info.opinfo->opcode != CSKYV2_INST_FLRW) + nbytes = 8; + else + nbytes = 4; + + status = dis_info.info->read_memory_func (addr, (bfd_byte *)ibytes, + nbytes, dis_info.info); + if (status != 0) + /* Address out of bounds. -> lrw rx, [pc, 0ffset]. */ + sprintf (buf, "[pc, %d]\t// from address pool at %x", (int)value, + (unsigned int)addr); + else + { + dis_info.value = addr; + value = csky_chars_to_number ((unsigned char *)ibytes, 4); + } + + if (oprnd->type == OPRND_TYPE_FCONSTANT) + { + double f; + + if (dis_info.opinfo->opcode == CSKYV2_INST_FLRW) + /* flrws. */ + floatformat_to_double ((dis_info.info->endian == BFD_ENDIAN_BIG + ? &floatformat_ieee_single_big + : &floatformat_ieee_single_little), + ibytes, &f); + else + floatformat_to_double ((dis_info.info->endian == BFD_ENDIAN_BIG + ? &floatformat_ieee_double_big + : &floatformat_ieee_double_little), + ibytes, &f); + sprintf (buf, "%f", f); + } + else + { + dis_info.need_output_symbol = 1; + sprintf (buf, "0x%x", (unsigned int)value); + } + + strcat (str, buf); + break; + } + case OPRND_TYPE_ELRW_CONSTANT: + { + int shift = oprnd->shift; + char ibytes[4]; + int status; + bfd_vma addr; + dis_info.info->stop_vma = 0; + + value = 0x80 + ((~value) & 0x7f); + + value = value << shift; + addr = (dis_info.mem + value) & 0xfffffffc; + + status = dis_info.info->read_memory_func (addr, (bfd_byte *)ibytes, + 4, dis_info.info); + if (status != 0) + /* Address out of bounds. -> lrw rx, [pc, 0ffset]. */ + sprintf (buf, "[pc, %d]\t// from address pool at %x", (int) value, + (unsigned int)addr); + else + { + dis_info.value = addr; + value = csky_chars_to_number ((unsigned char *)ibytes, 4); + dis_info.need_output_symbol = 1; + sprintf (buf, "0x%x", (unsigned int)value); + } + + strcat (str, buf); + break; + } + case OPRND_TYPE_SFLOAT: + case OPRND_TYPE_DFLOAT: + { + /* This is for fmovis/fmovid, which have an internal 13-bit + encoding that they convert to single/double precision + (respectively). We'll convert the 13-bit encoding to an IEEE + double and then to host double format to print it. + Sign bit: bit 20. + 4-bit exponent: bits 19:16, biased by 11. + 8-bit mantissa: split between 24:21 and 7:4. */ + uint64_t imm4; + uint64_t imm8; + uint64_t dbnum; + unsigned char valbytes[8]; + double fvalue; + + imm4 = ((inst >> 16) & 0xf); + imm4 = (uint64_t)(1023 - (imm4 - 11)) << 52; + + imm8 = (uint64_t)((inst >> 4) & 0xf) << 44; + imm8 |= (uint64_t)((inst >> 21) & 0xf) << 48; + + dbnum = (uint64_t)((inst >> 20) & 1) << 63; + dbnum |= imm4 | imm8; + + /* Do this a byte at a time so we don't have to + worry about the host's endianness. */ + valbytes[0] = dbnum & 0xff; + valbytes[1] = (dbnum >> 8) & 0xff; + valbytes[2] = (dbnum >> 16) & 0xff; + valbytes[3] = (dbnum >> 24) & 0xff; + valbytes[4] = (dbnum >> 32) & 0xff; + valbytes[5] = (dbnum >> 40) & 0xff; + valbytes[6] = (dbnum >> 48) & 0xff; + valbytes[7] = (dbnum >> 56) & 0xff; + + floatformat_to_double (&floatformat_ieee_double_little, valbytes, + &fvalue); + + sprintf (buf, "%f", fvalue); + strcat (str, buf); + break; + } + case OPRND_TYPE_LABEL_WITH_BRACKET: + sprintf (buf, "[0x%x]", (unsigned int)value); + strcat (str, buf); + strcat (str, "\t// the offset is based on .data"); + break; + case OPRND_TYPE_OIMM3b: + case OPRND_TYPE_OIMM4b: + case OPRND_TYPE_OIMM5b: + case OPRND_TYPE_OIMM5b_IDLY: + case OPRND_TYPE_OIMM8b: + case OPRND_TYPE_OIMM12b: + case OPRND_TYPE_OIMM16b: + case OPRND_TYPE_OIMM18b: + value += 1; + sprintf (buf, "%d", (int)value); + strcat (str, buf); + break; + case OPRND_TYPE_OIMM5b_BMASKI: + if (value > 32 || value < 16) + { + ret = -1; + break; + } + sprintf (buf, "%d", (int)(value + 1)); + strcat (str, buf); + ret = 0; + break; + case OPRND_TYPE_FREGLIST_DASH: + if (IS_CSKY_V2 (mach_flag)) + { + int vrx = value & 0xf; + int vry = vrx + (value >> 4); + sprintf (buf, "fr%d-fr%d", vrx, vry); + strcat (str, buf); + } + break; + case OPRND_TYPE_REGLIST_DASH: + if (IS_CSKY_V1 (mach_flag)) + { + strcat (str, csky_general_reg[value]); + strcat (str, "-r15"); + } + else + { + strcat (str, csky_general_reg[value >> 5]); + strcat (str, "-"); + strcat (str, csky_general_reg[(value & 0x1f) + (value >> 5)]); + } + break; + case OPRND_TYPE_PSR_BITS_LIST: + { + struct psrbit const *bits; + int first_oprnd = TRUE; + int i = 0; + if (IS_CSKY_V1 (mach_flag)) + { + if (value == 0) + { + strcat (str, "af"); + break; + } + bits = cskyv1_psr_bits; + } + else + bits = cskyv2_psr_bits; + while (value != 0 && bits[i].name != NULL) + { + if (value & bits[i].value) + { + if (!first_oprnd) + strcat (str, ", "); + strcat (str, bits[i].name); + value &= ~bits[i].value; + first_oprnd = FALSE; + } + i++; + } + break; + } + case OPRND_TYPE_REGbsp: + if (IS_CSKY_V1 (mach_flag)) + strcat (str, "(sp)"); + else + strcat (str, "(sp)"); + break; + case OPRND_TYPE_REGsp: + if (IS_CSKY_V1 (mach_flag)) + strcat (str, "sp"); + else + strcat (str, "sp"); + break; + case OPRND_TYPE_REGnr4_r7: + case OPRND_TYPE_AREG_WITH_BRACKET: + if (IS_CSKY_V1 (mach_flag) && (value < 4 || value > 7)) + { + strcat (str, "("); + strcat (str, csky_general_reg[value]); + strcat (str, ")"); + } + else + { + strcat (str, "("); + strcat (str, csky_general_reg[value]); + strcat (str, ")"); + } + break; + case OPRND_TYPE_AREG_WITH_LSHIFT: + strcat (str, csky_general_reg[value >> 5]); + strcat (str, " << "); + if ((value & 0x1f) == 0x1) + strcat (str, "0"); + else if ((value & 0x1f) == 0x2) + strcat (str, "1"); + else if ((value & 0x1f) == 0x4) + strcat (str, "2"); + else if ((value & 0x1f) == 0x8) + strcat (str, "3"); + break; + case OPRND_TYPE_AREG_WITH_LSHIFT_FPU: + strcat (str, csky_general_reg[value >> 2]); + strcat (str, " << "); + if ((value & 0x3) == 0x0) + strcat (str, "0"); + else if ((value & 0x3) == 0x1) + strcat (str, "1"); + else if ((value & 0x3) == 0x2) + strcat (str, "2"); + else if ((value & 0x3) == 0x3) + strcat (str, "3"); + break; + case OPRND_TYPE_FREG_WITH_INDEX: + { + unsigned freg_val = value & 0xf; + unsigned index_val = (value >> 4) & 0xf; + sprintf (buf, "vr%d[%d]", freg_val, index_val); + strcat(str, buf); + break; + } + case OPRND_TYPE_REGr4_r7: + if (IS_CSKY_V1 (mach_flag)) + strcat (str, "r4-r7"); + break; + case OPRND_TYPE_CONST1: + strcat (str, "1"); + break; + case OPRND_TYPE_REG_r1a: + case OPRND_TYPE_REG_r1b: + strcat (str, "r1"); + break; + case OPRND_TYPE_REG_r28: + strcat (str, "r28"); + break; + case OPRND_TYPE_REGLIST_DASH_COMMA: + /* 16-bit reglist. */ + if (value & 0xf) + { + strcat (str, "r4"); + if ((value & 0xf) > 1) + { + strcat (str, "-"); + strcat (str, csky_general_reg[(value & 0xf) + 3]); + } + if (value & ~0xf) + strcat (str, ", "); + } + if (value & 0x10) + { + /* r15. */ + strcat (str, "r15"); + if (value & ~0x1f) + strcat (str, ", "); + } + if (dis_info.opinfo->oprnd.oprnds[0].mask != OPRND_MASK_0_4) + { + /* 32bits reglist. */ + value >>= 5; + if (value & 0x3) + { + strcat (str, "r16"); + if ((value & 0x7) > 1) + { + strcat (str, "-"); + strcat (str, csky_general_reg[(value & 0xf) + 15]); + } + if (value & ~0x7) + strcat (str, ", "); + } + if (value & 0x8) + /* r15. */ + strcat (str, "r28"); + } + break; + case OPRND_TYPE_UNCOND10b: + case OPRND_TYPE_UNCOND16b: + case OPRND_TYPE_COND10b: + case OPRND_TYPE_COND16b: + { + int shift = oprnd->shift; + + if (value & ((max >> 1) + 1)) + value |= ~max; + if (is_extern_symbol (dis_info.info, dis_info.mem)) + value = 0; + else + value = dis_info.mem + (value << shift); + sprintf (buf, "0x%x", (unsigned int)value); + strcat (str, buf); + dis_info.need_output_symbol = 1; + dis_info.value = value; + } + break; + + default: + ret = -1; + break; + } + return ret; +} + +static int +csky_print_operand (char *str, struct operand const *oprnd, + CSKY_INST_TYPE inst, int reloc) +{ + int ret = -1; + char *lc = ""; + char *rc = ""; + if (oprnd->mask == HAS_SUB_OPERAND) + { + struct soperand *sop = (struct soperand *)oprnd; + if (oprnd->type == OPRND_TYPE_BRACKET) + { + lc = "("; + rc = ")"; + } + else if (oprnd->type == OPRND_TYPE_ABRACKET) + { + lc = "<"; + rc = ">"; + } + strcat (str, lc); + ret = csky_print_operand (str, &sop->subs[0], inst, reloc); + if (ret) + return ret; + strcat (str, ", "); + ret = csky_print_operand (str, &sop->subs[1], inst, reloc); + strcat (str, rc); + return ret; + } + return csky_output_operand (str, oprnd, inst, reloc); +} + +static int +csky_print_operands (char *str, struct csky_opcode_info const *pinfo, + struct disassemble_info *info, CSKY_INST_TYPE inst, + int reloc) +{ + int i = 0; + int ret = 0; + if (pinfo->operand_num) + strcat (str, " \t"); + if (pinfo->operand_num == -1) + { + ret = csky_print_operand (str, &pinfo->oprnd.oprnds[i], inst, reloc); + if (ret) + return ret; + } + else + for (; i < pinfo->operand_num; i++) + { + if (i != 0) + strcat (str, ", "); + ret = csky_print_operand (str, &pinfo->oprnd.oprnds[i], inst, reloc); + if (ret) + return ret; + } + info->fprintf_func (info->stream, "%s", str); + if (dis_info.need_output_symbol) + { + info->fprintf_func (info->stream, "\t// "); + info->print_address_func (dis_info.value, dis_info.info); + } + return 0; +} + +static void +number_to_chars_littleendian (char *buf, CSKY_INST_TYPE val, int n) +{ + if (n <= 0) + abort (); + while (n--) + { + *buf++ = val & 0xff; + val >>= 8; + } +} + +#define CSKY_READ_DATA() \ +{ \ + status = info->read_memory_func (memaddr, buf, 2, info); \ + if (status) \ + { \ + info->memory_error_func (status, memaddr, info); \ + return -1; \ + } \ + if (info->endian == BFD_ENDIAN_BIG) \ + inst |= (buf[0] << 8) | buf[1]; \ + else if (info->endian == BFD_ENDIAN_LITTLE) \ + inst |= (buf[1] << 8) | buf[0]; \ + else \ + abort(); \ + info->bytes_per_chunk += 2; \ + memaddr += 2; \ +} + +int +print_insn_csky (bfd_vma memaddr, struct disassemble_info *info) +{ + unsigned char buf[4]; + CSKY_INST_TYPE inst = 0; + int status; + char str[256]; + long given; + int is_data = FALSE; + void (*printer) (bfd_vma, struct disassemble_info *, long); + unsigned int size = 4; + + memset (str, 0, sizeof (str)); + info->bytes_per_chunk = 0; + info->bytes_per_chunk = 0; + dis_info.mem = memaddr; + dis_info.info = info; + dis_info.need_output_symbol = 0; + if (mach_flag != INIT_MACH_FLAG && mach_flag != BINARY_MACH_FLAG) + info->mach = mach_flag; + else if (mach_flag == INIT_MACH_FLAG) + mach_flag = info->mach; + + if (mach_flag == BINARY_MACH_FLAG && info->endian == BFD_ENDIAN_UNKNOWN) + info->endian = BFD_ENDIAN_LITTLE; + + /* First check the full symtab for a mapping symbol, even if there + are no usable non-mapping symbols for this address. */ + if (info->symtab_size != 0 + && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour) + { + bfd_vma addr; + int n; + int last_sym = -1; + enum sym_type type = CUR_TEXT; + + if (memaddr <= last_map_addr) + last_map_sym = -1; + /* Start scanning at the start of the function, or wherever + we finished last time. */ + n = 0; + if (n < last_map_sym) + n = last_map_sym; + + /* Scan up to the location being disassembled. */ + for (; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > memaddr) + break; + if ((info->section == NULL + || info->section == info->symtab[n]->section) + && get_sym_code_type (info, n, &type)) + last_sym = n; + } + last_map_sym = last_sym; + last_type = type; + is_data = (last_type == CUR_DATA); + if (is_data) + { + size = 4 - ( memaddr & 3); + for (n = last_sym + 1; n < info->symtab_size; n++) + { + addr = bfd_asymbol_value (info->symtab[n]); + if (addr > memaddr) + { + if (addr - memaddr < size) + size = addr - memaddr; + break; + } + } + /* If the next symbol is after three bytes, we need to + print only part of the data, so that we can use either + .byte or .short. */ + if (size == 3) + size = (memaddr & 1) ? 1 : 2; + } + } + info->bytes_per_line = 4; + + if (is_data) + { + int i; + + /* Size was already set above. */ + info->bytes_per_chunk = size; + printer = print_insn_data; + + status = info->read_memory_func (memaddr, (bfd_byte *) buf, size, info); + given = 0; + if (info->endian == BFD_ENDIAN_LITTLE) + for (i = size - 1; i >= 0; i--) + given = buf[i] | (given << 8); + else + for (i = 0; i < (int) size; i++) + given = buf[i] | (given << 8); + + printer (memaddr, info, given); + return info->bytes_per_chunk; + } + + /* Handle instructions. */ + CSKY_READ_DATA(); + if ((inst & 0xc000) == 0xc000 && IS_CSKY_V2 (mach_flag)) + { + /* It's a 32-bit instruction. */ + inst <<= 16; + CSKY_READ_DATA(); + if (info->buffer && (info->endian == BFD_ENDIAN_LITTLE)) + { + char* src = (char *)(info->buffer + + ((memaddr - 4 - info->buffer_vma) + * info->octets_per_byte)); + if (info->endian == BFD_ENDIAN_LITTLE) + number_to_chars_littleendian (src, inst, 4); + } + } + + if (IS_CSKY_V1 (mach_flag)) + g_opcodeP = csky_v1_opcodes; + else + g_opcodeP = csky_v2_opcodes; + + do + { + struct csky_opcode const *op; + struct csky_opcode_info const *pinfo = NULL; + int reloc; + + memset (str, 0, sizeof (str)); + op = csky_find_inst_info (&pinfo, inst, info->bytes_per_chunk); + if (!op) + { + if (IS_CSKY_V1 (mach_flag)) + info->fprintf_func (info->stream, ".short: 0x%04x", + (unsigned short)inst); + else + info->fprintf_func (info->stream, ".long: 0x%08x", + (unsigned int)inst); + return info->bytes_per_chunk; + } + + if (info->bytes_per_chunk == 2) + reloc = op->reloc16; + else + reloc = op->reloc32; + dis_info.opinfo = pinfo; + strcat (str, op->mnemonic); + + if (csky_print_operands (str, pinfo, info, inst, reloc)) + g_opcodeP++; + else + break; + } while (1); + + return info->bytes_per_chunk; +} diff --git a/opcodes/csky-opc.h b/opcodes/csky-opc.h new file mode 100644 index 0000000..e31378c --- /dev/null +++ b/opcodes/csky-opc.h @@ -0,0 +1,8127 @@ +/* Declarations for C-SKY opcode table + Copyright (C) 2007-2018 Free Software Foundation, Inc. + Contributed by C-SKY Microsystems and Mentor Graphics. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "opcode/csky.h" + +#define OP_TABLE_NUM 2 +#define MAX_OPRND_NUM 4 + +enum operand_type +{ + OPRND_TYPE_NONE = 0, + /* Control register. */ + OPRND_TYPE_CTRLREG, + /* r0 - r7. */ + OPRND_TYPE_GREG0_7, + /* r0 - r15. */ + OPRND_TYPE_GREG0_15, + /* r16 - r31. */ + OPRND_TYPE_GREG16_31, + /* r0 - r31. */ + OPRND_TYPE_AREG, + /* (rx). */ + OPRND_TYPE_AREG_WITH_BRACKET, + OPRND_TYPE_AREG_WITH_LSHIFT, + OPRND_TYPE_AREG_WITH_LSHIFT_FPU, + + OPRND_TYPE_FREG_WITH_INDEX, + /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */ + OPRND_TYPE_REG_r1a, + /* r1 only, for divs/divu in csky v1 ISA. */ + OPRND_TYPE_REG_r1b, + /* r28. */ + OPRND_TYPE_REG_r28, + OPRND_TYPE_REGr4_r7, + /* sp register with bracket. */ + OPRND_TYPE_REGbsp, + /* sp register. */ + OPRND_TYPE_REGsp, + /* Register with bracket. */ + OPRND_TYPE_REGnr4_r7, + /* Not sp register. */ + OPRND_TYPE_REGnsp, + /* Not lr register. */ + OPRND_TYPE_REGnlr, + /* Not sp/lr register. */ + OPRND_TYPE_REGnsplr, + /* hi/lo register. */ + OPRND_TYPE_REGhilo, + /* VDSP register. */ + OPRND_TYPE_VREG, + + /* cp index. */ + OPRND_TYPE_CPIDX, + /* cp regs. */ + OPRND_TYPE_CPREG, + /* cp cregs. */ + OPRND_TYPE_CPCREG, + /* fpu regs. */ + OPRND_TYPE_FREG, + /* fpu even regs. */ + OPRND_TYPE_FEREG, + /* Float round mode. */ + OPRND_TYPE_RM, + /* PSR bits. */ + OPRND_TYPE_PSR_BITS_LIST, + + /* Constant. */ + OPRND_TYPE_CONSTANT, + /* Floating Constant. */ + OPRND_TYPE_FCONSTANT, + /* Extern lrw constant. */ + OPRND_TYPE_ELRW_CONSTANT, + /* [label]. */ + OPRND_TYPE_LABEL_WITH_BRACKET, + /* The operand is the same as first reg. It is a dummy reg that doesn't + appear in the binary code of the instruction. It is also used by + the disassembler. + For example: bclri rz, rz, imm5 -> bclri rz, imm5. */ + OPRND_TYPE_DUMMY_REG, + /* The type of the operand is same as the first operand. If the value + of the operand is same as the first operand, we can use a 16-bit + instruction to represent the opcode. + For example: addc r1, r1, r2 -> addc16 r1, r2. */ + OPRND_TYPE_2IN1_DUMMY, + /* Output a reg same as the first reg. + For example: addc r17, r1 -> addc32 r17, r17, r1. + The old "addc" cannot be represented by a 16-bit instruction because + 16-bit "addc" only supports regs from r0 to r15. So we use "addc32" + which has 3 operands, and duplicate the first operand to the second. */ + OPRND_TYPE_DUP_GREG0_7, + OPRND_TYPE_DUP_GREG0_15, + OPRND_TYPE_DUP_AREG, + /* Immediate. */ + OPRND_TYPE_IMM1b, + OPRND_TYPE_IMM2b, + OPRND_TYPE_IMM3b, + OPRND_TYPE_IMM4b, + OPRND_TYPE_IMM5b, + OPRND_TYPE_IMM7b, + OPRND_TYPE_IMM8b, + OPRND_TYPE_IMM12b, + OPRND_TYPE_IMM15b, + OPRND_TYPE_IMM16b, + OPRND_TYPE_IMM18b, + OPRND_TYPE_IMM32b, + /* Immediate left shift 2 bits. */ + OPRND_TYPE_IMM7b_LS2, + OPRND_TYPE_IMM8b_LS2, + /* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */ + OPRND_TYPE_IMM5b_1_31, + OPRND_TYPE_IMM5b_7_31, + /* Operand type for rori and rotri. */ + OPRND_TYPE_IMM5b_RORI, + OPRND_TYPE_IMM5b_POWER, + OPRND_TYPE_IMM5b_7_31_POWER, + OPRND_TYPE_IMM5b_BMASKI, + OPRND_TYPE_IMM8b_BMASKI, + /* For v2 movih. */ + OPRND_TYPE_IMM16b_MOVIH, + /* For v2 ori. */ + OPRND_TYPE_IMM16b_ORI, + /* For v2 ld/st. */ + OPRND_TYPE_IMM_LDST, + OPRND_TYPE_IMM_FLDST, + OPRND_TYPE_IMM2b_JMPIX, + /* Offset for bloop. */ + OPRND_TYPE_BLOOP_OFF4b, + OPRND_TYPE_BLOOP_OFF12b, + /* Offset for jump. */ + OPRND_TYPE_OFF8b, + OPRND_TYPE_OFF10b, + OPRND_TYPE_OFF11b, + OPRND_TYPE_OFF16b, + OPRND_TYPE_OFF16b_LSL1, + OPRND_TYPE_OFF26b, + /* An immediate or label. */ + OPRND_TYPE_IMM_OFF18b, + /* Offset immediate. */ + OPRND_TYPE_OIMM3b, + OPRND_TYPE_OIMM4b, + OPRND_TYPE_OIMM5b, + OPRND_TYPE_OIMM8b, + OPRND_TYPE_OIMM12b, + OPRND_TYPE_OIMM16b, + OPRND_TYPE_OIMM18b, + /* For csky v2 idly. */ + OPRND_TYPE_OIMM5b_IDLY, + /* For v2 bmaski. */ + OPRND_TYPE_OIMM5b_BMASKI, + /* Constants. */ + OPRND_TYPE_CONST1, + /* PC relative offset. */ + OPRND_TYPE_PCR_OFFSET_16K, + OPRND_TYPE_PCR_OFFSET_64K, + OPRND_TYPE_PCR_OFFSET_64M, + OPRND_TYPE_CPFUNC, + OPRND_TYPE_GOT_PLT, + OPRND_TYPE_REGLIST_LDM, + OPRND_TYPE_REGLIST_DASH, + OPRND_TYPE_FREGLIST_DASH, + OPRND_TYPE_REGLIST_COMMA, + OPRND_TYPE_REGLIST_DASH_COMMA, + OPRND_TYPE_BRACKET, + OPRND_TYPE_ABRACKET, + OPRND_TYPE_JBTF, + OPRND_TYPE_JBR, + OPRND_TYPE_JBSR, + OPRND_TYPE_UNCOND10b, + OPRND_TYPE_UNCOND16b, + OPRND_TYPE_COND10b, + OPRND_TYPE_COND16b, + OPRND_TYPE_JCOMPZ, + OPRND_TYPE_LSB2SIZE, + OPRND_TYPE_MSB2SIZE, + OPRND_TYPE_LSB, + OPRND_TYPE_MSB, + /* Single float and double float. */ + OPRND_TYPE_SFLOAT, + OPRND_TYPE_DFLOAT, +}; + +/* Operand descriptors. */ +struct operand +{ + /* Mask for suboperand. */ + unsigned int mask; + /* Suboperand type. */ + enum operand_type type; + /* Operand shift. */ + int shift; +}; + +struct soperand +{ + /* Mask for operand. */ + unsigned int mask; + /* Operand type. */ + enum operand_type type; + /* Operand shift. */ + int shift; + /* Suboperand. */ + struct operand subs[3]; +}; + +union csky_operand +{ + struct operand oprnds[5]; + struct suboperand1 + { + struct operand oprnd; + struct soperand soprnd; + } soprnd1; + struct suboperand2 + { + struct soperand soprnd; + struct operand oprnd; + } soprnd2; +}; + +/* Describe a single instruction encoding. */ +struct csky_opcode_info +{ + /* How many operands. */ + long operand_num; + /* The instruction opcode. */ + unsigned int opcode; + /* Operand information. */ + union csky_operand oprnd; +}; + +/* C-SKY instruction description. Each mnemonic can have multiple + 16-bit and 32-bit encodings. */ +struct csky_opcode +{ + /* The instruction name. */ + const char *mnemonic; + /* Whether this is an unconditional control transfer instruction, + for the purposes of placing literal pools after it. + 0 = no, 1 = within function, 2 = end of function. + See check_literals in gas/config/tc-csky.c. */ + int transfer; + /* Encodings for 16-bit opcodes. */ + struct csky_opcode_info op16[OP_TABLE_NUM]; + /* Encodings for 32-bit opcodes. */ + struct csky_opcode_info op32[OP_TABLE_NUM]; + /* Instruction set flag. */ + unsigned int isa_flag16; + unsigned int isa_flag32; + /* Whether this insn needs relocation, 0: no, !=0: yes. */ + signed int reloc16; + signed int reloc32; + /* Whether this insn needs relaxation, 0: no, != 0: yes. */ + signed int relax; + /* Worker function to call when this instruction needs special assembler + handling. */ + bfd_boolean (*work)(void); +}; + +/* The following are the opcodes used in relax/fix process. */ +#define CSKYV1_INST_JMPI 0x7000 +#define CSKYV1_INST_ADDI 0x2000 +#define CSKYV1_INST_SUBI 0x2400 +#define CSKYV1_INST_LDW 0x8000 +#define CSKYV1_INST_STW 0x9000 +#define CSKYV1_INST_BSR 0xf800 +#define CSKYV1_INST_LRW 0x7000 +#define CSKYV1_INST_ADDU 0x1c00 +#define CSKYV1_INST_JMP 0x00c0 +#define CSKYV1_INST_MOV_R1_RX 0x1201 +#define CSKYV1_INST_MOV_RX_R1 0x1210 + +#define CSKYV2_INST_BT16 0x0800 +#define CSKYV2_INST_BF16 0x0c00 +#define CSKYV2_INST_BT32 0xe8600000 +#define CSKYV2_INST_BF32 0xe8400000 +#define CSKYV2_INST_BR32 0xe8000000 +#define CSKYV2_INST_NOP 0x6c03 +#define CSKYV2_INST_MOVI16 0x3000 +#define CSKYV2_INST_MOVI32 0xea000000 +#define CSKYV2_INST_MOVIH 0xea200000 +#define CSKYV2_INST_LRW16 0x1000 +#define CSKYV2_INST_LRW32 0xea800000 +#define CSKYV2_INST_BSR32 0xe0000000 +#define CSKYV2_INST_BR32 0xe8000000 +#define CSKYV2_INST_FLRW 0xf4003800 +#define CSKYV2_INST_JMPI32 0xeac00000 +#define CSKYV2_INST_JSRI32 0xeae00000 +#define CSKYV2_INST_JSRI_TO_LRW 0xea9a0000 +#define CSKYV2_INST_JSR_R26 0xe8fa0000 +#define CSKYV2_INST_MOV_R0_R0 0xc4004820 + +#define OPRND_SHIFT_0_BIT 0 +#define OPRND_SHIFT_1_BIT 1 +#define OPRND_SHIFT_2_BIT 2 +#define OPRND_SHIFT_3_BIT 3 +#define OPRND_SHIFT_4_BIT 4 + +#define OPRND_MASK_NONE 0x0 +#define OPRND_MASK_0_1 0x3 +#define OPRND_MASK_0_2 0x7 +#define OPRND_MASK_0_3 0xf +#define OPRND_MASK_0_4 0x1f +#define OPRND_MASK_0_7 0xff +#define OPRND_MASK_0_8 0x1ff +#define OPRND_MASK_0_9 0x3ff +#define OPRND_MASK_0_10 0x7ff +#define OPRND_MASK_0_11 0xfff +#define OPRND_MASK_0_14 0x7fff +#define OPRND_MASK_0_15 0xffff +#define OPRND_MASK_0_17 0x3ffff +#define OPRND_MASK_0_25 0x3ffffff +#define OPRND_MASK_2_4 0x1c +#define OPRND_MASK_2_5 0x3c +#define OPRND_MASK_3_7 0xf8 +#define OPRND_MASK_4 0x10 +#define OPRND_MASK_4_6 0x70 +#define OPRND_MASK_4_7 0xf0 +#define OPRND_MASK_4_8 0x1f0 +#define OPRND_MASK_4_10 0x7f0 +#define OPRND_MASK_5 0x20 +#define OPRND_MASK_5_6 0x60 +#define OPRND_MASK_5_7 0xe0 +#define OPRND_MASK_5_8 0x1e0 +#define OPRND_MASK_5_9 0x3e0 +#define OPRND_MASK_6_9 0x3c0 +#define OPRND_MASK_6_10 0x7c0 +#define OPRND_MASK_8_9 0x300 +#define OPRND_MASK_8_10 0x700 +#define OPRND_MASK_8_11 0xf00 +#define OPRND_MASK_9_10 0x600 +#define OPRND_MASK_9_12 0x1e00 +#define OPRND_MASK_10_11 0xc00 +#define OPRND_MASK_10_14 0x7c00 +#define OPRND_MASK_12_15 0xf000 +#define OPRND_MASK_13_17 0x3e000 +#define OPRND_MASK_16_19 0xf0000 +#define OPRND_MASK_16_20 0x1f0000 +#define OPRND_MASK_16_25 0x3ff0000 +#define OPRND_MASK_21_24 0x1e00000 +#define OPRND_MASK_21_25 0x3e00000 +#define OPRND_MASK_25 0x2000000 +#define OPRND_MASK_RSV 0xffffffff +#define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24 +#define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25 +#define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20 +#define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10 +#define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9 +#define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20 +#define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8 +#define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24 +#define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9 +#define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25 +#define OPRND_MASK_4_7or21_24 OPRND_MASK_4_7 | OPRND_MASK_21_24 +#define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25 +#define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10 +#define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25 +#define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24 +#define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25 +#define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25 +#define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24 + +#define OPERAND_INFO(mask, type, shift) \ + {OPRND_MASK_##mask, OPRND_TYPE_##type, shift} + +#define OPCODE_INFO_NONE() \ + {-2, 0, \ + {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} + +/* Here and in subsequent macros, the "oprnd" arguments are the + parenthesized arglist to the OPERAND_INFO macro above. */ +#define OPCODE_INFO(num, op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ + {num, op, \ + {OPERAND_INFO oprnd1, OPERAND_INFO oprnd2, OPERAND_INFO oprnd3, \ + OPERAND_INFO oprnd4, OPERAND_INFO oprnd5}} + +#define OPCODE_INFO0(op) \ + {0, op, \ + {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define OPCODE_INFO1(op, oprnd) \ + {1, op, \ + {{OPERAND_INFO oprnd, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define OPCODE_INFO2(op, oprnd1, oprnd2) \ + {2, op, \ + {{OPERAND_INFO oprnd1, \ + OPERAND_INFO oprnd2, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define OPCODE_INFO3(op, oprnd1, oprnd2, oprnd3) \ + {3, op, \ + {{OPERAND_INFO oprnd1, \ + OPERAND_INFO oprnd2, \ + OPERAND_INFO oprnd3, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define OPCODE_INFO4(op, oprnd1, oprnd2, oprnd3, oprnd4) \ + {4, op, \ + {{OPERAND_INFO oprnd1, \ + OPERAND_INFO oprnd2, \ + OPERAND_INFO oprnd3, \ + OPERAND_INFO oprnd4, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define OPCODE_INFO_LIST(op, oprnd) \ + {-1, op, \ + {{OPERAND_INFO oprnd, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) , \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define OPCODE_INFO5(op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ + {5, op, \ + {{OPERAND_INFO oprnd1, \ + OPERAND_INFO oprnd2, \ + OPERAND_INFO oprnd3, \ + OPERAND_INFO oprnd4, \ + OPERAND_INFO oprnd5}}} + +#define BRACKET_OPRND(oprnd1, oprnd2) \ + OPERAND_INFO (RSV, BRACKET, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO oprnd1, \ + OPERAND_INFO oprnd2, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) +#define ABRACKET_OPRND(oprnd1, oprnd2) \ + OPERAND_INFO (RSV, ABRACKET, OPRND_SHIFT_0_BIT), \ + OPERAND_INFO oprnd1, \ + OPERAND_INFO oprnd2, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) + +#define SOPCODE_INFO1(op, soprnd) \ + {1, op, \ + {{soprnd, \ + OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} +#define SOPCODE_INFO2(op, oprnd, soprnd) \ + {2, op, \ + {{OPERAND_INFO oprnd, soprnd}}} + + +/* Before using the opcode-defining macros, there need to be + #defines for _TRANSFER, _RELOC16, _RELOC32, and _RELAX. See + below. */ +/* FIXME: it is a wart that these parameters are not explicit. */ + +#define OP16(mnem, opcode16, isa) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + isa, 0, _RELOC16, 0, _RELAX, NULL} + +#ifdef BUILD_AS + +#define OP16_WITH_WORK(mnem, opcode16, isa, work) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + isa, 0, _RELOC16, 0, _RELAX, work} +#define OP32_WITH_WORK(mnem, opcode32, isa, work) \ + {mnem, _TRANSFER, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + 0, isa, 0, _RELOC32, _RELAX, work} +#define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} +#define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ + {mnem, _TRANSFER, \ + {opcode16a, opcode16b}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} +#define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ + {mnem, _TRANSFER, \ + {opcode16a, opcode16b}, \ + {opcode32a, opcode32b}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} +#define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ + {mnem, _TRANSFER, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + {opcode32a, opcode32b}, \ + 0, isa, 0, _RELOC32, _RELAX, work} + +#else /* ifdef BUILD_AS */ + +#define OP16_WITH_WORK(mnem, opcode16, isa, work) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + isa, 0, _RELOC16, 0, _RELAX, NULL} +#define OP32_WITH_WORK(mnem, opcode32, isa, work) \ + {mnem, _TRANSFER, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + 0, isa, 0, _RELOC32, _RELAX, NULL} +#define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} +#define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ + {mnem, _TRANSFER, \ + {opcode16a, opcode16b}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} +#define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ + {mnem, _TRANSFER, \ + {opcode16a, opcode16b}, \ + {opcode32a, opcode32b}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} +#define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ + {mnem, _TRANSFER, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + {opcode32a, opcode32b}, \ + 0, isa, 0, _RELOC32, _RELAX, NULL} + +#endif /* ifdef BUILD_AS */ + +#define DOP16(mnem, opcode16_1, opcode16_2, isa) \ + {mnem, _TRANSFER, \ + {opcode16_1, opcode16_2}, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + isa, 0, _RELOC16, 0, _RELAX, NULL} +#define OP32(mnem, opcode32, isa) \ + {mnem, _TRANSFER, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + 0, isa, 0, _RELOC32, _RELAX, NULL} +#define DOP32(mnem, opcode32a, opcode32b, isa) \ + {mnem, _TRANSFER, \ + {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ + {opcode32a, opcode32b}, \ + 0, isa, 0, _RELOC32, _RELAX, NULL} +#define OP16_OP32(mnem, opcode16, isa16, opcode32, isa32) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} +#define DOP16_OP32(mnem, opcode16a, opcode16b, isa16, opcode32, isa32) \ + {mnem, _TRANSFER, \ + {opcode16a, opcode16b}, \ + {opcode32, OPCODE_INFO_NONE ()}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} +#define OP16_DOP32(mnem, opcode16, isa16, opcode32a, opcode32b, isa32) \ + {mnem, _TRANSFER, \ + {opcode16, OPCODE_INFO_NONE ()}, \ + {opcode32a, opcode32b}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} +#define DOP16_DOP32(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32) \ + {mnem, _TRANSFER, \ + {opcode16a, opcode16b}, \ + {opcode32a, opcode32b}, \ + isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} + + +/* Register names and numbers. */ +#define V1_REG_SP 0 +#define V1_REG_LR 15 + +struct csky_reg +{ + const char *name; + int index; + int flag; +}; + +const char *csky_general_reg[] = +{ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", + NULL, +}; + +/* TODO: optimize. */ +const char *cskyv2_general_alias_reg[] = +{ + "a0", "a1", "a2", "a3", "l0", "l1", "l2", "l3", + "l4", "l5", "l6", "l7", "t0", "t1", "sp", "lr", + "l8", "l9", "t2", "t3", "t4", "t5", "t6", "t7", + "t8", "t9", "r26", "r27", "rdb", "gb", "r30", "r31", + NULL, +}; + +/* TODO: optimize. */ +const char *cskyv1_general_alias_reg[] = +{ + "sp", "r1", "a0", "a1", "a2", "a3", "a4", "a5", + "fp", "l0", "l1", "l2", "l3", "l4", "gb", "lr", + NULL, +}; + +/* TODO: optimize. */ +const char *csky_fpu_reg[] = +{ + "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", + "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", + "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", + NULL, +}; + +/* Control Registers. */ +struct csky_reg csky_ctrl_regs[] = +{ + {"psr", 0, 0}, {"vbr", 1, 0}, {"epsr", 2, 0}, {"fpsr", 3, 0}, + {"epc", 4, 0}, {"fpc", 5, 0}, {"ss0", 6, 0}, {"ss1", 7, 0}, + {"ss2", 8, 0}, {"ss3", 9, 0}, {"ss4", 10, 0}, {"gcr", 11, 0}, + {"gsr", 12, 0}, {"cpuidr", 13, 0}, {"dcsr", 14, 0}, {"cwr", 15, 0}, + {"cfr", 16, 0}, {"ccr", 17, 0}, {"capr", 19, 0}, {"pacr", 20, 0}, + {"rid", 21, 0}, {"sedcr", 8, CSKY_ISA_TRUST}, {"sepcr", 9, CSKY_ISA_TRUST}, + {NULL, 0, 0} +}; + +const char *csky_cp_idx[] = +{ + "cp0", "cp1", "cp2", "cp3", "cp4", "cp5", "cp6", "cp7", + "cp8", "cp9", "cp10", "cp11", "cp12", "cp13", "cp14", "cp15", + "cp16", "cp17", "cp18", "cp19", "cp20", + NULL, +}; + +const char *csky_cp_reg[] = +{ + "cpr0", "cpr1", "cpr2", "cpr3", "cpr4", "cpr5", "cpr6", "cpr7", + "cpr8", "cpr9", "cpr10", "cpr11", "cpr12", "cpr13", "cpr14", "cpr15", + "cpr16", "cpr17", "cpr18", "cpr19", "cpr20", "cpr21", "cpr22", "cpr23", + "cpr24", "cpr25", "cpr26", "cpr27", "cpr28", "cpr29", "cpr30", "cpr31", + "cpr32", "cpr33", "cpr34", "cpr35", "cpr36", "cpr37", "cpr38", "cpr39", + "cpr40", "cpr41", "cpr42", "cpr43", "cpr44", "cpr45", "cpr46", "cpr47", + "cpr48", "cpr49", "cpr50", "cpr51", "cpr52", "cpr53", "cpr54", "cpr55", + "cpr56", "cpr57", "cpr58", "cpr59", "cpr60", "cpr61", "cpr62", "cpr63", + NULL, +}; + +const char *csky_cp_creg[] = +{ + "cpcr0", "cpcr1", "cpcr2", "cpcr3", + "cpcr4", "cpcr5", "cpcr6", "cpcr7", + "cpcr8", "cpcr9", "cpcr10", "cpcr11", + "cpcr12", "cpcr13", "cpcr14", "cpcr15", + "cpcr16", "cpcr17", "cpcr18", "cpcr19", + "cpcr20", "cpcr21", "cpcr22", "cpcr23", + "cpcr24", "cpcr25", "cpcr26", "cpcr27", + "cpcr28", "cpcr29", "cpcr30", "cpcr31", + "cpcr32", "cpcr33", "cpcr34", "cpcr35", + "cpcr36", "cpcr37", "cpcr38", "cpcr39", + "cpcr40", "cpcr41", "cpcr42", "cpcr43", + "cpcr44", "cpcr45", "cpcr46", "cpcr47", + "cpcr48", "cpcr49", "cpcr50", "cpcr51", + "cpcr52", "cpcr53", "cpcr54", "cpcr55", + "cpcr56", "cpcr57", "cpcr58", "cpcr59", + "cpcr60", "cpcr61", "cpcr62", "cpcr63", + NULL, +}; + +struct psrbit +{ + int value; + int isa; + const char *name; +}; +const struct psrbit cskyv1_psr_bits[] = +{ + {1, 0, "ie"}, + {2, 0, "fe"}, + {4, 0, "ee"}, + {8, 0, "af"}, + {0, 0, NULL}, +}; +const struct psrbit cskyv2_psr_bits[] = +{ + {8, 0, "ee"}, + {4, 0, "ie"}, + {2, 0, "fe"}, + {1, 0, "af"}, + {0x10, CSKY_ISA_TRUST, "sie"}, + {0, 0, NULL}, +}; + + +/* C-SKY V1 opcodes. */ +const struct csky_opcode csky_v1_opcodes[] = +{ +#define _TRANSFER 0 +#define _RELOC16 0 +#define _RELOC32 0 +#define _RELAX 0 + OP16 ("bkpt", + OPCODE_INFO0 (0x0000), + CSKYV1_ISA_E1), + OP16 ("sync", + OPCODE_INFO0 (0x0001), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 2 + OP16 ("rfi", + OPCODE_INFO0 (0x0003), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 + OP16 ("stop", + OPCODE_INFO0 (0x0004), + CSKYV1_ISA_E1), + OP16 ("wait", + OPCODE_INFO0 (0x0005), + CSKYV1_ISA_E1), + OP16 ("doze", + OPCODE_INFO0 (0x0006), + CSKYV1_ISA_E1), + OP16 ("idly4", + OPCODE_INFO0 (0x0007), + CSKYV1_ISA_E1), + OP16 ("trap", + OPCODE_INFO1 (0x0008, + (0_1, IMM2b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mvtc", + OPCODE_INFO0 (0x000c), + CSKY_ISA_DSP), + OP16 ("cprc", + OPCODE_INFO0 (0x000d), + CSKY_ISA_CP), + OP16 ("cpseti", + OPCODE_INFO1 (0x0010, + (0_3, CPIDX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + OP16 ("mvc", + OPCODE_INFO1 (0x0020, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mvcv", + OPCODE_INFO1 (0x0030, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("ldq", + OPCODE_INFO2 (0x0040, + (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), + (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("stq", + OPCODE_INFO2 (0x0050, + (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), + (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("ldm", + OPCODE_INFO2 (0x0060, + (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), + (NONE, REGbsp, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("stm", + OPCODE_INFO2 (0x0070, + (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), + (NONE, REGbsp, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("dect", + OPCODE_INFO3 (0x0080, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0080, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("decf", + OPCODE_INFO3 (0x0090, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0090, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("inct", + OPCODE_INFO3 (0x00a0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x00a0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("incf", + OPCODE_INFO3 (0x00b0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x00b0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 2 + OP16 ("jmp", + OPCODE_INFO1 (0x00c0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 + OP16 ("jsr", + OPCODE_INFO1 (0x00d0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ff1", + OPCODE_INFO2 (0x00e0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x00e0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("brev", + OPCODE_INFO2 (0x00f0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x00f0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("xtrb3", + OPCODE_INFO2 (0x0100, + (NONE, REG_r1a, OPRND_SHIFT_0_BIT), + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0100, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("xtrb2", + OPCODE_INFO2 (0x0110, + (NONE, REG_r1a, OPRND_SHIFT_0_BIT), + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0110, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("xtrb1", + OPCODE_INFO2 (0x0120, + (NONE, REG_r1a, OPRND_SHIFT_0_BIT), + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0120, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("xtrb0", + OPCODE_INFO2 (0x0130, + (NONE, REG_r1a, OPRND_SHIFT_0_BIT), + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0130, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("zextb", + OPCODE_INFO2 (0x0140, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0140, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("sextb", + OPCODE_INFO2 (0x0150, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0150, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("zexth", + OPCODE_INFO2 (0x0160, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0160, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("sexth", + OPCODE_INFO2 (0x0170, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0170, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("declt", + OPCODE_INFO3 (0x0180, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x0180, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("tstnbz", + OPCODE_INFO1 (0x0190, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("decgt", + OPCODE_INFO3 (0x01a0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x01a0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("decne", + OPCODE_INFO3 (0x01b0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x01b0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("clrt", + OPCODE_INFO1 (0x01c0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("clrf", + OPCODE_INFO1 (0x01d0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("abs", + OPCODE_INFO2 (0x01e0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x01e0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("not", + OPCODE_INFO2 (0x01f0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x01f0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("movt", + OPCODE_INFO2 (0x0200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("mult", + OPCODE_INFO3 (0x0300, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x0300, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mac", + OPCODE_INFO2 (0x0400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC), + DOP16 ("subu", + OPCODE_INFO3 (0x0500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x0500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("sub", + OPCODE_INFO3 (0x0500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x0500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("addc", + OPCODE_INFO3 (0x0600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x0600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("subc", + OPCODE_INFO3 (0x0700, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x0700, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cprgr", + OPCODE_INFO2 (0x0800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, CPREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + OP16 ("movf", + OPCODE_INFO2 (0x0a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("lsr", + OPCODE_INFO3 (0x0b00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x0b00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cmphs", + OPCODE_INFO2 (0x0c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cmplt", + OPCODE_INFO2 (0x0d00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("tst", + OPCODE_INFO2 (0x0e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cmpne", + OPCODE_INFO2 (0x0f00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mfcr", + OPCODE_INFO2 (0x1000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("psrclr", + OPCODE_INFO_LIST (0x11f0, + (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("psrset", + OPCODE_INFO_LIST (0x11f8, + (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mov", + OPCODE_INFO2 (0x1200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("bgenr", + OPCODE_INFO2 (0x1300, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("rsub", + OPCODE_INFO3 (0x1400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ixw", + OPCODE_INFO3 (0x1500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("and", + OPCODE_INFO3 (0x1600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("xor", + OPCODE_INFO3 (0x1700, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1700, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mtcr", + OPCODE_INFO2 (0x1800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("asr", + OPCODE_INFO3 (0x1a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("lsl", + OPCODE_INFO3 (0x1b00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1b00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("addu", + OPCODE_INFO3 (0x1c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("add", + OPCODE_INFO2 (0x1c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ixh", + OPCODE_INFO3 (0x1d00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1d00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("or", + OPCODE_INFO3 (0x1e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("andn", + OPCODE_INFO3 (0x1f00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x1f00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("addi", + OPCODE_INFO3 (0x2000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x2000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cmplti", + OPCODE_INFO2 (0x2200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("subi", + OPCODE_INFO3 (0x2400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x2400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cpwgr", + OPCODE_INFO2 (0x2600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, CPREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + DOP16 ("rsubi", + OPCODE_INFO3 (0x2800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x2800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cmpnei", + OPCODE_INFO2 (0x2a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("bmaski", + OPCODE_INFO2 (0x2c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_BMASKI, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("divu", + OPCODE_INFO3 (0x2c10, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x2c10, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mflos", + OPCODE_INFO1 (0x2c20, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC_DSP), + OP16 ("mfhis", + OPCODE_INFO1 (0x2c30, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC_DSP), + OP16 ("mtlo", + OPCODE_INFO1 (0x2c40, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC_DSP), + OP16 ("mthi", + OPCODE_INFO1 (0x2c50, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC_DSP), + OP16 ("mflo", + OPCODE_INFO1 (0x2c60, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC_DSP), + OP16 ("mfhi", + OPCODE_INFO1 (0x2c70, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC_DSP), + DOP16 ("andi", + OPCODE_INFO3 (0x2e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x2e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("bclri", + OPCODE_INFO3 (0x3000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("bgeni", + OPCODE_INFO2 (0x3200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_7_31, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cpwir", + OPCODE_INFO1 (0x3200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + DOP16 ("divs", + OPCODE_INFO3 (0x3210, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3210, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("cprsr", + OPCODE_INFO1 (0x3220, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + OP16 ("cpwsr", + OPCODE_INFO1 (0x3230, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + DOP16 ("bseti", + OPCODE_INFO3 (0x3400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("btsti", + OPCODE_INFO2 (0x3600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("rotli", + OPCODE_INFO3 (0x3800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("xsr", + OPCODE_INFO3 (0x3800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x3800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("asrc", + OPCODE_INFO3 (0x3a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x3a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("asri", + OPCODE_INFO3 (0x3a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("lslc", + OPCODE_INFO3 (0x3c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x3c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("lsli", + OPCODE_INFO3 (0x3c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("lsrc", + OPCODE_INFO3 (0x3e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x3e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("lsri", + OPCODE_INFO3 (0x3e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("ldex", + SOPCODE_INFO2 (0x4000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKY_ISA_MP), + OP16 ("ldex.w", + SOPCODE_INFO2 (0x4000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKY_ISA_MP), + OP16 ("ldwex", + SOPCODE_INFO2 (0x4000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKY_ISA_MP), + OP16 ("stex", + SOPCODE_INFO2 (0x5000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKY_ISA_MP), + OP16 ("stex.w", + SOPCODE_INFO2 (0x5000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKY_ISA_MP), + OP16 ("stwex", + SOPCODE_INFO2 (0x5000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKY_ISA_MP), + OP16 ("omflip0", + OPCODE_INFO2 (0x4000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC), + OP16 ("omflip1", + OPCODE_INFO2 (0x4100, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC), + OP16 ("omflip2", + OPCODE_INFO2 (0x4200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC), + OP16 ("omflip3", + OPCODE_INFO2 (0x4300, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MAC), + OP16 ("muls", + OPCODE_INFO2 (0x5000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulsa", + OPCODE_INFO2 (0x5100, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulss", + OPCODE_INFO2 (0x5200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulu", + OPCODE_INFO2 (0x5400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulua", + OPCODE_INFO2 (0x5500, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulus", + OPCODE_INFO2 (0x5600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("vmulsh", + OPCODE_INFO2 (0x5800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("vmulsha", + OPCODE_INFO2 (0x5900, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("vmulshs", + OPCODE_INFO2 (0x5a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("vmulsw", + OPCODE_INFO2 (0x5c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("vmulswa", + OPCODE_INFO2 (0x5d00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("vmulsws", + OPCODE_INFO2 (0x5e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("movi", + OPCODE_INFO2 (0x6000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_10, IMM7b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("mulsh", + OPCODE_INFO3 (0x6800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x6800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("mulsh.h", + OPCODE_INFO3 (0x6800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x6800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("mulsha", + OPCODE_INFO2 (0x6900, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulshs", + OPCODE_INFO2 (0x6a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("cprcr", + OPCODE_INFO2 (0x6b00, + (0_2, GREG0_7, OPRND_SHIFT_0_BIT), + (3_7, CPCREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), + OP16 ("mulsw", + OPCODE_INFO2 (0x6c00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulswa", + OPCODE_INFO2 (0x6d00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("mulsws", + OPCODE_INFO2 (0x6e00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16 ("cpwcr", + OPCODE_INFO2 (0x6f00, + (0_2, GREG0_7, OPRND_SHIFT_0_BIT), + (3_7, CPCREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_CP), +#undef _RELOC16 +#define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM8BY4 +#undef _TRANSFER +#define _TRANSFER 1 + OP16 ("jmpi", + OPCODE_INFO1 (0x7000, + (0_7, OFF8b, OPRND_SHIFT_2_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 + OP16 ("jsri", + OPCODE_INFO1 (0x7f00, + (0_7, OFF8b, OPRND_SHIFT_2_BIT)), + CSKYV1_ISA_E1), + OP16_WITH_WORK ("lrw", + OPCODE_INFO2 (0x7000, + (8_11, REGnsplr, OPRND_SHIFT_0_BIT), + (0_7, CONSTANT, OPRND_SHIFT_2_BIT)), + CSKYV1_ISA_E1, + v1_work_lrw), +#undef _RELOC16 +#define _RELOC16 0 + DOP16 ("ld.w", + SOPCODE_INFO2 (0x8000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), + OPCODE_INFO2 (0x8000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ldw", + SOPCODE_INFO2 (0x8000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), + OPCODE_INFO2 (0x8000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ld", + SOPCODE_INFO2 (0x8000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), + OPCODE_INFO2 (0x8000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("st.w", + SOPCODE_INFO2 (0x9000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), + OPCODE_INFO2 (0x9000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("stw", + SOPCODE_INFO2 (0x9000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), + OPCODE_INFO2 (0x9000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("st", + SOPCODE_INFO2 (0x9000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), + OPCODE_INFO2 (0x9000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ld.b", + SOPCODE_INFO2 (0xa000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + OPCODE_INFO2 (0xa000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ldb", + SOPCODE_INFO2 (0xa000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + OPCODE_INFO2 (0xa000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("st.b", + SOPCODE_INFO2 (0xb000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + OPCODE_INFO2 (0xb000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("stb", + SOPCODE_INFO2 (0xb000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), + OPCODE_INFO2 (0xb000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ld.h", + SOPCODE_INFO2 (0xc000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), + OPCODE_INFO2 (0xc000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("ldh", + SOPCODE_INFO2 (0xc000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), + OPCODE_INFO2 (0xc000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("st.h", + SOPCODE_INFO2 (0xd000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), + OPCODE_INFO2 (0xd000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + DOP16 ("sth", + SOPCODE_INFO2 (0xd000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), + OPCODE_INFO2 (0xd000, + (8_11, GREG0_15, OPRND_SHIFT_0_BIT), + (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + +#undef _RELOC16 +#define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM11BY2 + OP16 ("bt", + OPCODE_INFO1 (0xe000, + (0_10, OFF11b, OPRND_SHIFT_1_BIT)), + CSKYV1_ISA_E1), + OP16 ("bf", + OPCODE_INFO1 (0xe800, + (0_10, OFF11b, OPRND_SHIFT_1_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 1 + OP16 ("br", + OPCODE_INFO1 (0xf000, + (0_10, OFF11b, OPRND_SHIFT_1_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 + OP16 ("bsr", + OPCODE_INFO1 (0xf800, + (0_10, OFF11b, OPRND_SHIFT_1_BIT)), + CSKYV1_ISA_E1), +#undef _RELOC16 +#define _RELOC16 0 + +#undef _RELAX +#define _RELAX 1 + OP16 ("jbt", + OPCODE_INFO1 (0xe000, + (0_10, JBTF, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("jbf", + OPCODE_INFO1 (0xe800, + (0_10, JBTF, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 1 + OP16 ("jbr", + OPCODE_INFO1 (0xf000, + (0_10, JBR, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 +#undef _RELAX +#define _RELAX 0 + + OP16_WITH_WORK ("jbsr", + OPCODE_INFO1 (0xf800, + (0_10, JBSR, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1, + v1_work_jbsr), + + /* The following are aliases for other instructions. */ + /* rts -> jmp r15. */ +#undef _TRANSFER +#define _TRANSFER 2 + OP16 ("rts", + OPCODE_INFO0 (0x00CF), + CSKYV1_ISA_E1), + OP16 ("rte", + OPCODE_INFO0 (0x0002), + CSKYV1_ISA_E1), + OP16 ("rfe", + OPCODE_INFO0 (0x0002), + CSKYV1_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 + + /* cmphs r0,r0 */ + OP16 ("setc", + OPCODE_INFO0 (0x0c00), + CSKYV1_ISA_E1), + /* cmpne r0,r0 */ + OP16 ("clrc", + OPCODE_INFO0 (0x0f00), + CSKYV1_ISA_E1), + /* cmplti rd,1 */ + OP16 ("tstle", + OPCODE_INFO1 (0x2200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* cmplei rd,X -> cmplti rd,X+1 */ + OP16 ("cmplei", + OPCODE_INFO2 (0x2200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* rsubi rd,0 */ + OP16 ("neg", + OPCODE_INFO1 (0x2800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* cmpnei rd,0. */ + OP16 ("tstne", + OPCODE_INFO1 (0x2a00, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* btsti rx,31. */ + OP16 ("tstlt", + OPCODE_INFO1 (0x37f0, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* bclri rx,log2(imm). */ + OP16 ("mclri", + OPCODE_INFO2 (0x3000, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* bgeni rx,log2(imm). */ + OP16 ("mgeni", + OPCODE_INFO2 (0x3200, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_7_31_POWER, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* bseti rx,log2(imm). */ + OP16 ("mseti", + OPCODE_INFO2 (0x3400, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* btsti rx,log2(imm). */ + OP16 ("mtsti", + OPCODE_INFO2 (0x3600, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("rori", + OPCODE_INFO2 (0x3800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + OP16 ("rotri", + OPCODE_INFO2 (0x3800, + (0_3, GREG0_15, OPRND_SHIFT_0_BIT), + (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), + CSKYV1_ISA_E1), + /* mov r0, r0. */ + OP16 ("nop", + OPCODE_INFO0 (0x1200), + CSKYV1_ISA_E1), + + /* Float instruction with work. */ + OP16_WITH_WORK ("fabss", + OPCODE_INFO3 (0xffe04400, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnegs", + OPCODE_INFO3 (0xffe04c00, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsqrts", + OPCODE_INFO3 (0xffe05400, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("frecips", + OPCODE_INFO3 (0xffe05c00, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fadds", + OPCODE_INFO4 (0xffe38000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsubs", + OPCODE_INFO4 (0xffe48000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, v1_work_fpu_fo), + OP16_WITH_WORK ("fmacs", + OPCODE_INFO4 (0xffe58000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmscs", + OPCODE_INFO4 (0xffe68000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmuls", + OPCODE_INFO4 (0xffe78000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fdivs", + OPCODE_INFO4 (0xffe88000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmacs", + OPCODE_INFO4 (0xffe98000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmscs", + OPCODE_INFO4 (0xffea8000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmuls", + OPCODE_INFO4 (0xffeb8000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (10_14, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fabsd", + OPCODE_INFO3 (0xffe04000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnegd", + OPCODE_INFO3 (0xffe04800, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsqrtd", + OPCODE_INFO3 (0xffe05000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("frecipd", + OPCODE_INFO3 (0xffe05800, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("faddd", + OPCODE_INFO4 (0xffe30000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsubd", + OPCODE_INFO4 (0xffe40000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmacd", + OPCODE_INFO4 (0xffe50000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmscd", + OPCODE_INFO4 (0xffe60000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmuld", + OPCODE_INFO4 (0xffe70000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fdivd", + OPCODE_INFO4 (0xffe80000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmacd", + OPCODE_INFO4 (0xffe90000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmscd", + OPCODE_INFO4 (0xffea0000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmuld", + OPCODE_INFO4 (0xffeb0000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fabsm", + OPCODE_INFO3 (0xffe06000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnegm", + OPCODE_INFO3 (0xffe06400, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("faddm", + OPCODE_INFO4 (0xffec0000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsubm", + OPCODE_INFO4 (0xffec8000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmacm", + OPCODE_INFO4 (0xffed8000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmscm", + OPCODE_INFO4 (0xffee0000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmulm", + OPCODE_INFO4 (0xffed0000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmacm", + OPCODE_INFO4 (0xffee8000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmscm", + OPCODE_INFO4 (0xffef0000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fnmulm", + OPCODE_INFO4 (0xffef8000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (10_14, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fcmphsd", + OPCODE_INFO3 (0xffe00800, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpltd", + OPCODE_INFO3 (0xffe00c00, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpned", + OPCODE_INFO3 (0xffe01000, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpuod", + OPCODE_INFO3 (0xffe01400, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmphss", + OPCODE_INFO3 (0xffe01800, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (5_9, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmplts", + OPCODE_INFO3 (0xffe01c00, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (5_9, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpnes", + OPCODE_INFO3 (0xffe02000, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (5_9, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpuos", + OPCODE_INFO3 (0xffe02400, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (5_9, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzhsd", + OPCODE_INFO2 (0xffe00400, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzltd", + OPCODE_INFO2 (0xffe00480, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzned", + OPCODE_INFO2 (0xffe00500, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzuod", + OPCODE_INFO2 (0xffe00580, + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzhss", + OPCODE_INFO2 (0xffe00600, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzlts", + OPCODE_INFO2 (0xffe00680, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpznes", + OPCODE_INFO2 (0xffe00700, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fcmpzuos", + OPCODE_INFO2 (0xffe00780, + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo_fc), + OP16_WITH_WORK ("fstod", + OPCODE_INFO3 (0xffe02800, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fdtos", + OPCODE_INFO3 (0xffe02c00, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsitos", + OPCODE_INFO3 (0xffe03400, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fsitod", + OPCODE_INFO3 (0xffe03000, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fuitos", + OPCODE_INFO3 (0xffe03c00, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fuitod", + OPCODE_INFO3 (0xffe03800, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fstosi", + OPCODE_INFO4 (0xffe10000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (13_17, RM, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fdtosi", + OPCODE_INFO4 (0xffe08000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (13_17, RM, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fstoui", + OPCODE_INFO4 (0xffe20000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (13_17, RM, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fdtoui", + OPCODE_INFO4 (0xffe18000, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FEREG, OPRND_SHIFT_0_BIT), + (13_17, RM, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmovd", + OPCODE_INFO3 (0xffe06800, + (5_9, FEREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmovs", + OPCODE_INFO3 (0xffe06c00, + (5_9, FREG, OPRND_SHIFT_0_BIT), + (0_4, FREG, OPRND_SHIFT_0_BIT), + (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_fo), + OP16_WITH_WORK ("fmts", + OPCODE_INFO2 (0x00000000, + (NONE, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_write), + OP16_WITH_WORK ("fmfs", + OPCODE_INFO2 (0x00000000, + (NONE, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_read), + OP16_WITH_WORK ("fmtd", + OPCODE_INFO2 (0x00000000, + (NONE, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, FEREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_writed), + OP16_WITH_WORK ("fmfd", + OPCODE_INFO2 (0x00000000, + (NONE, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, FEREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1, + v1_work_fpu_readd), + {NULL} +}; + +#undef _TRANSFER +#undef _RELOC16 +#undef _RELOC32 +#undef _RELAX + +/* C-SKY v2 opcodes. */ +const struct csky_opcode csky_v2_opcodes[] = + { +#define _TRANSFER 0 +#define _RELOC16 0 +#define _RELOC32 0 +#define _RELAX 0 + OP16 ("bkpt", + OPCODE_INFO0 (0x0000), + CSKYV2_ISA_E1), + OP16_WITH_WORK ("nie", + OPCODE_INFO0 (0x1460), + CSKYV2_ISA_E1, + v2_work_istack), + OP16_WITH_WORK ("nir", + OPCODE_INFO0 (0x1461), + CSKYV2_ISA_E1, + v2_work_istack), + OP16_WITH_WORK ("ipush", + OPCODE_INFO0 (0x1462), + CSKYV2_ISA_E1, + v2_work_istack), + OP16_WITH_WORK ("ipop", + OPCODE_INFO0 (0x1463), + CSKYV2_ISA_E1, + v2_work_istack), + OP16 ("bpop.h", + OPCODE_INFO1 (0x14a0, + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKY_ISA_JAVA), + OP16 ("bpop.w", + OPCODE_INFO1 (0x14a2, + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKY_ISA_JAVA), + OP16 ("bpush.h", + OPCODE_INFO1 (0x14e0, + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKY_ISA_JAVA), + OP16 ("bpush.w", + OPCODE_INFO1 (0x14e2, + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKY_ISA_JAVA), + OP32 ("bmset", + OPCODE_INFO0 (0xc0001020), + CSKY_ISA_JAVA), + OP32 ("bmclr", + OPCODE_INFO0 (0xc0001420), + CSKY_ISA_JAVA), + OP32 ("sce", + OPCODE_INFO1 (0xc0001820, + (21_24, IMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_MP), + OP32 ("trap", + OPCODE_INFO1 (0xc0002020, + (10_11, IMM2b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + /* Secure/nsecure world switch. */ + OP32 ("wsc", + OPCODE_INFO0 (0xc0003c20), + CSKY_ISA_TRUST), + OP32 ("mtcr", + OPCODE_INFO2 (0xc0006420, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + OP32 ("mfcr", + OPCODE_INFO2 (0xc0006020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 2 + OP32 ("rte", + OPCODE_INFO0 (0xc0004020), + CSKYV2_ISA_E1), + OP32 ("rfi", + OPCODE_INFO0 (0xc0004420), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#define _TRANSFER 0 + OP32 ("stop", + OPCODE_INFO0 (0xc0004820), + CSKYV2_ISA_E1), + OP32 ("wait", + OPCODE_INFO0 (0xc0004c20), + CSKYV2_ISA_E1), + OP32 ("doze", + OPCODE_INFO0 (0xc0005020), + CSKYV2_ISA_E1), + OP32 ("we", + OPCODE_INFO0 (0xc0005420), + CSKY_ISA_MP_1E2), + OP32 ("se", + OPCODE_INFO0 (0xc0005820), + CSKY_ISA_MP_1E2), + OP32 ("psrclr", + OPCODE_INFO_LIST (0xc0007020, + (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + OP32 ("psrset", + OPCODE_INFO_LIST (0xc0007420, + (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + DOP32 ("abs", + OPCODE_INFO2 (0xc4000200, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc4000200, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("mvc", + OPCODE_INFO1 (0xc4000500, + (0_4, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("incf", + OPCODE_INFO3 (0xc4000c20, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("movf", + OPCODE_INFO2 (0xc4000c20, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("inct", + OPCODE_INFO3 (0xc4000c40, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("movt", + OPCODE_INFO2 (0xc4000c40, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("decf", + OPCODE_INFO3 (0xc4000c80, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("dect", + OPCODE_INFO3 (0xc4000d00, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("decgt", + OPCODE_INFO3 (0xc4001020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("declt", + OPCODE_INFO3 (0xc4001040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("decne", + OPCODE_INFO3 (0xc4001080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("clrf", + OPCODE_INFO1 (0xc4002c20, + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("clrt", + OPCODE_INFO1 (0xc4002c40, + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP32 ("rotli", + OPCODE_INFO3 (0xc4004900, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004900, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("lslc", + OPCODE_INFO3 (0xc4004c20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("lsrc", + OPCODE_INFO3 (0xc4004c40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP32 ("asrc", + OPCODE_INFO3 (0xc4004c80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc4004c80, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xsr", + OPCODE_INFO3 (0xc4004d00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("bgenr", + OPCODE_INFO2 (0xc4005040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP32 ("brev", + OPCODE_INFO2 (0xc4006200, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc4006200, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("xtrb0", + OPCODE_INFO2 (0xc4007020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xtrb1", + OPCODE_INFO2 (0xc4007040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xtrb2", + OPCODE_INFO2 (0xc4007080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xtrb3", + OPCODE_INFO2 (0xc4007100, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("ff0", + OPCODE_INFO2 (0xc4007c20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP32 ("ff1", + OPCODE_INFO2 (0xc4007c40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc4007c40, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("mulu", + OPCODE_INFO2 (0xc4008820, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulua", + OPCODE_INFO2 (0xc4008840, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulus", + OPCODE_INFO2 (0xc4008880, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("muls", + OPCODE_INFO2 (0xc4008c20, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulsa", + OPCODE_INFO2 (0xc4008c40, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulss", + OPCODE_INFO2 (0xc4008c80, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulsha", + OPCODE_INFO2 (0xc4009040, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulshs", + OPCODE_INFO2 (0xc4009080, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulswa", + OPCODE_INFO2 (0xc4009440, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mulsws", + OPCODE_INFO2 (0xc4009480, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mfhis", + OPCODE_INFO1 (0xc4009820, + (0_4, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mflos", + OPCODE_INFO1 (0xc4009880, + (0_4, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mvtc", + OPCODE_INFO0 (0xc4009a00), + CSKY_ISA_DSP), + OP32 ("mfhi", + OPCODE_INFO1 (0xc4009c20, + (0_4, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mthi", + OPCODE_INFO1 (0xc4009c40, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mflo", + OPCODE_INFO1 (0xc4009c80, + (0_4, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("mtlo", + OPCODE_INFO1 (0xc4009d00, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP32 ("vmulsh", + OPCODE_INFO2 (0xc400b020, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_1E2), + OP32 ("vmulsha", + OPCODE_INFO2 (0xc400b040, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_1E2), + OP32 ("vmulshs", + OPCODE_INFO2 (0xc400b080, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_1E2), + OP32 ("vmulsw", + OPCODE_INFO2 (0xc400b420, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_1E2), + OP32 ("vmulswa", + OPCODE_INFO2 (0xc400b440, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_1E2), + OP32 ("vmulsws", + OPCODE_INFO2 (0xc400b480, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_1E2), + OP32 ("ldr.b", + SOPCODE_INFO2 (0xd0000000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("ldr.bs", + SOPCODE_INFO2 (0xd0001000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("ldr.h", + SOPCODE_INFO2 (0xd0000400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("ldr.hs", + SOPCODE_INFO2 (0xd0001400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("ldr.w", + SOPCODE_INFO2 (0xd0000800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("ldm", + OPCODE_INFO2 (0xd0001c20, + (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("ldq", + OPCODE_INFO2 (0xd0801c23, + (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("str.b", + SOPCODE_INFO2 (0xd4000000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("str.h", + SOPCODE_INFO2 (0xd4000400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("str.w", + SOPCODE_INFO2 (0xd4000800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_2E3), + OP32 ("stm", + OPCODE_INFO2 (0xd4001c20, + (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("stq", + OPCODE_INFO2 (0xd4801c23, + (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("ld.bs", + SOPCODE_INFO2 (0xd8004000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_1E2), + OP32 ("ldbs", + SOPCODE_INFO2 (0xd8004000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_1E2), + OP32 ("ld.hs", + SOPCODE_INFO2 (0xd8005000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_1E2), + OP32 ("ldhs", + SOPCODE_INFO2 (0xd8005000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_1E2), + OP32 ("ld.d", + SOPCODE_INFO2 (0xd8003000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_3E7), + OP32 ("ldex.w", + SOPCODE_INFO2 (0xd8007000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_MP_1E2), + OP32 ("ldexw", + SOPCODE_INFO2 (0xd8007000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_MP_1E2), + OP32 ("ldex", + SOPCODE_INFO2 (0xd8007000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_MP_1E2), + OP32 ("st.d", + SOPCODE_INFO2 (0xdc003000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_3E7), + OP32 ("stex.w", + SOPCODE_INFO2 (0xdc007000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_MP_1E2), + OP32 ("stexw", + SOPCODE_INFO2 (0xdc007000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_MP_1E2), + OP32 ("stex", + SOPCODE_INFO2 (0xdc007000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_MP_1E2), + DOP32 ("andi", + OPCODE_INFO3 (0xe4002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM12b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xe4002000, + (16_20or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM12b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("andni", + OPCODE_INFO3 (0xe4003000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM12b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xori", + OPCODE_INFO3 (0xe4004000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM12b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("ins", + OPCODE_INFO4 (0xc4005c00, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9, MSB2SIZE, OPRND_SHIFT_0_BIT), + (0_4, LSB2SIZE, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#undef _RELOC32 +#define _TRANSFER 1 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 + OP32 ("jmpi", + OPCODE_INFO1 (0xeac00000, + (0_15, OFF16b, OPRND_SHIFT_2_BIT)), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#undef _RELOC32 +#define _TRANSFER 0 +#define _RELOC32 0 + + OP32 ("fadds", + OPCODE_INFO3 (0xf4000000, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fsubs", + OPCODE_INFO3 (0xf4000020, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fmovs", + OPCODE_INFO2 (0xf4000080, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fabss", + OPCODE_INFO2 (0xf40000c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fnegs", + OPCODE_INFO2 (0xf40000e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmpzhss", + OPCODE_INFO1 (0xf4000100, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmpzlss", + OPCODE_INFO1 (0xf4000120, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmpznes", + OPCODE_INFO1 (0xf4000140, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmpzuos", + OPCODE_INFO1 (0xf4000160, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmphss", + OPCODE_INFO2 (0xf4000180, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmplts", + OPCODE_INFO2 (0xf40001a0, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmpnes", + OPCODE_INFO2 (0xf40001c0, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fcmpuos", + OPCODE_INFO2 (0xf40001e0, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fmuls", + OPCODE_INFO3 (0xf4000200, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fmacs", + OPCODE_INFO3 (0xf4000280, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fmscs", + OPCODE_INFO3 (0xf40002a0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fnmacs", + OPCODE_INFO3 (0xf40002c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fnmscs", + OPCODE_INFO3 (0xf40002e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fnmuls", + OPCODE_INFO3 (0xf4000220, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fdivs", + OPCODE_INFO3 (0xf4000300, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("frecips", + OPCODE_INFO2 (0xf4000320, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fsqrts", + OPCODE_INFO2 (0xf4000340, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("faddd", + OPCODE_INFO3 (0xf4000800, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fsubd", + OPCODE_INFO3 (0xf4000820, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmovd", + OPCODE_INFO2 (0xf4000880, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fabsd", + OPCODE_INFO2 (0xf40008c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnegd", + OPCODE_INFO2 (0xf40008e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpzhsd", + OPCODE_INFO1 (0xf4000900, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpzlsd", + OPCODE_INFO1 (0xf4000920, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpzned", + OPCODE_INFO1 (0xf4000940, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpzuod", + OPCODE_INFO1 (0xf4000960, + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmphsd", + OPCODE_INFO2 (0xf4000980, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpltd", + OPCODE_INFO2 (0xf40009a0, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpned", + OPCODE_INFO2 (0xf40009c0, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fcmpuod", + OPCODE_INFO2 (0xf40009e0, + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmuld", + OPCODE_INFO3 (0xf4000a00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnmuld", + OPCODE_INFO3 (0xf4000a20, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmacd", + OPCODE_INFO3 (0xf4000a80, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmscd", + OPCODE_INFO3 (0xf4000aa0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnmacd", + OPCODE_INFO3 (0xf4000ac0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnmscd", + OPCODE_INFO3 (0xf4000ae0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdivd", + OPCODE_INFO3 (0xf4000b00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("frecipd", + OPCODE_INFO2 (0xf4000b20, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fsqrtd", + OPCODE_INFO2 (0xf4000b40, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("faddm", + OPCODE_INFO3 (0xf4001000, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fsubm", + OPCODE_INFO3 (0xf4001020, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmovm", + OPCODE_INFO2 (0xf4001080, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fabsm", + OPCODE_INFO2 (0xf40010c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnegm", + OPCODE_INFO2 (0xf40010e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmulm", + OPCODE_INFO3 (0xf4001200, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnmulm", + OPCODE_INFO3 (0xf4001220, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmacm", + OPCODE_INFO3 (0xf4001280, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmscm", + OPCODE_INFO3 (0xf40012a0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnmacm", + OPCODE_INFO3 (0xf40012c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fnmscm", + OPCODE_INFO3 (0xf40012e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT), + (21_24, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstosi.rn", + OPCODE_INFO2 (0xf4001800, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstosi.rz", + OPCODE_INFO2 (0xf4001820, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstosi.rpi", + OPCODE_INFO2 (0xf4001840, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstosi.rni", + OPCODE_INFO2 (0xf4001860, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstoui.rn", + OPCODE_INFO2 (0xf4001880, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstoui.rz", + OPCODE_INFO2 (0xf40018a0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstoui.rpi", + OPCODE_INFO2 (0xf40018c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstoui.rni", + OPCODE_INFO2 (0xf40018e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fdtosi.rn", + OPCODE_INFO2 (0xf4001900, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtosi.rz", + OPCODE_INFO2 (0xf4001920, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtosi.rpi", + OPCODE_INFO2 (0xf4001940, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtosi.rni", + OPCODE_INFO2 (0xf4001960, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtoui.rn", + OPCODE_INFO2 (0xf4001980, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtoui.rz", + OPCODE_INFO2 (0xf40019a0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtoui.rpi", + OPCODE_INFO2 (0xf40019c0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtoui.rni", + OPCODE_INFO2 (0xf40019e0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fsitos", + OPCODE_INFO2 (0xf4001a00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fuitos", + OPCODE_INFO2 (0xf4001a20, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fsitod", + OPCODE_INFO2 (0xf4001a80, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fuitod", + OPCODE_INFO2 (0xf4001aa0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fdtos", + OPCODE_INFO2 (0xf4001ac0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstod", + OPCODE_INFO2 (0xf4001ae0, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmfvrh", + OPCODE_INFO2 (0xf4001b00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmfvrl", + OPCODE_INFO2 (0xf4001b20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19, FREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fmtvrh", + OPCODE_INFO2 (0xf4001b40, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fmtvrl", + OPCODE_INFO2 (0xf4001b60, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("flds", + SOPCODE_INFO2 (0xf4002000, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_FLOAT_E1), + OP32 ("fldd", + SOPCODE_INFO2 (0xf4002100, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fldm", + SOPCODE_INFO2 (0xf4002200, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fsts", + SOPCODE_INFO2 (0xf4002400, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_FLOAT_E1), + OP32 ("fstd", + SOPCODE_INFO2 (0xf4002500, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstm", + SOPCODE_INFO2 (0xf4002600, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fldrs", + SOPCODE_INFO2 (0xf4002800, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_FLOAT_E1), + OP32 ("fstrs", + SOPCODE_INFO2 (0xf4002c00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_FLOAT_E1), + OP32 ("fldrd", + SOPCODE_INFO2 (0xf4002900, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fldrm", + SOPCODE_INFO2 (0xf4002a00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstrd", + SOPCODE_INFO2 (0xf4002d00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstrm", + SOPCODE_INFO2 (0xf4002e00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_FLOAT_1E2), + OP32 ("fldms", + OPCODE_INFO2 (0xf4003000, + (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fldmd", + OPCODE_INFO2 (0xf4003100, + (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fldmm", + OPCODE_INFO2 (0xf4003200, + (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstms", + OPCODE_INFO2 (0xf4003400, + (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_E1), + OP32 ("fstmd", + OPCODE_INFO2 (0xf4003500, + (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + OP32 ("fstmm", + OPCODE_INFO2 (0xf4003600, + (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_FLOAT_1E2), + DOP32 ("sync", + OPCODE_INFO1 (0xc0000420, + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO0 (0xc0000420), + CSKYV2_ISA_E1), + DOP32 ("idly", + OPCODE_INFO1 (0xc0001c20, + (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)), + OPCODE_INFO0 (0xc0601c20), + CSKYV2_ISA_E1), + +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM18BY2 + OP32 ("grs", + OPCODE_INFO2 (0xcc0c0000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, IMM_OFF18b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), +#undef _RELOC32 +#define _RELOC32 0 + DOP32 ("ixh", + OPCODE_INFO3 (0xc4000820, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000820, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP32 ("ixw", + OPCODE_INFO3 (0xc4000840, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000840, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("ixd", + OPCODE_INFO3 (0xc4000880, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP32 ("divu", + OPCODE_INFO3 (0xc4008020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4008020, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP32 ("divs", + OPCODE_INFO3 (0xc4008040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4008040, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("pldr", + SOPCODE_INFO1 (0xd8006000, + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_CACHE), + OP32 ("pldw", + SOPCODE_INFO1 (0xdc006000, + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKY_ISA_CACHE), + OP32 ("cprgr", + SOPCODE_INFO2 (0xfc000000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), + (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP32 ("cpwgr", + SOPCODE_INFO2 (0xfc001000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), + (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP32 ("cprcr", + SOPCODE_INFO2 (0xfc002000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), + (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP32 ("cpwcr", + SOPCODE_INFO2 (0xfc003000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), + (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP32 ("cprc", + SOPCODE_INFO1 (0xfc004000, + ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), + (0_11, IMM12b, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP32 ("cpop", + SOPCODE_INFO1 (0xfc008000, + ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), + (0_14or16_20 , IMM15b, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + + OP16_OP32 ("push", + OPCODE_INFO_LIST (0x14c0, + (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO_LIST (0xebe00000, + (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#define _TRANSFER 2 + OP16_OP32 ("pop", + OPCODE_INFO_LIST (0x1480, + (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO_LIST (0xebc00000, + (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#define _TRANSFER 0 + OP16_OP32 ("movi", + OPCODE_INFO2 (0x3000, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_7, IMM8b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xea000000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, IMM16b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + /* bmaski will transfer to movi when imm < 17. */ + OP16_OP32 ("bmaski", + OPCODE_INFO2 (0x3000, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_7, IMM8b_BMASKI, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, + OPCODE_INFO2 (0xc4005020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b_BMASKI, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("cmphsi", + OPCODE_INFO2 (0x3800, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xeb000000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("cmplti", + OPCODE_INFO2 (0x3820, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xeb200000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("cmpnei", + OPCODE_INFO2 (0x3840, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xeb400000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, IMM16b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), +#undef _TRANSFER +#define _TRANSFER 1 + OP16_OP32 ("jmpix", + OPCODE_INFO2 (0x38e0, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_JAVA, + OPCODE_INFO2 (0xe9e00000, + (16_20, GREG0_7, OPRND_SHIFT_0_BIT), + (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_JAVA), +#undef _TRANSFER +#define _TRANSFER 0 + DOP16_DOP32 ("bclri", + OPCODE_INFO3 (0x3880, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x3880, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002820, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002820, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("bseti", + OPCODE_INFO3 (0x38a0, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x38a0, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002840, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002840, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32_WITH_WORK ("btsti", + OPCODE_INFO2 (0x38c0, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4002880, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, v2_work_btsti), + DOP16_DOP32 ("lsli", + OPCODE_INFO3 (0x4000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x4000, + (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004820, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004820, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("lsri", + OPCODE_INFO3 (0x4800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0x4800, + (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004840, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004840, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("asri", + OPCODE_INFO3 (0x5000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004880, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("addc", + OPCODE_INFO2 (0x6001, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6001, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4000040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000040, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("subc", + OPCODE_INFO2 (0x6003, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6003, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4000100, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000100, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("cmphs", + OPCODE_INFO2 (0x6400, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT), + (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4000420, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16_OP32 ("cmplt", + OPCODE_INFO2 (0x6401, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT), + (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4000440, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16_OP32 ("cmpne", + OPCODE_INFO2 (0x6402, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT), + (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4000480, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16_OP32 ("mvcv", + OPCODE_INFO1 (0x6403, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xc4000600, + (0_4, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP16_DOP32 ("and", + OPCODE_INFO2 (0x6800, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6800, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002020, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("andn", + OPCODE_INFO2 (0x6801, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6801, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002040, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("tst", + OPCODE_INFO2 (0x6802, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT), + (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4002080, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16_OP32 ("tstnbz", + OPCODE_INFO1 (0x6803, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xc4002100, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP16_DOP32 ("or", + OPCODE_INFO2 (0x6c00, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6c00, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002420, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002420, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("xor", + OPCODE_INFO2 (0x6c01, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6c01, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002440, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002440, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("nor", + OPCODE_INFO2 (0x6c02, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x6c02, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4002480, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4002480, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("mov", + OPCODE_INFO2 (0x6c03, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4004820, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("nop", + OPCODE_INFO0 (0x6c03), + CSKYV2_ISA_E1, + OPCODE_INFO0 (0xc4004820), + CSKYV2_ISA_E1), + DOP16_DOP32 ("lsl", + OPCODE_INFO2 (0x7000, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x7000, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004020, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("lsr", + OPCODE_INFO2 (0x7001, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x7001, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004040, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("asr", + OPCODE_INFO2 (0x7002, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x7002, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004080, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("rotl", + OPCODE_INFO2 (0x7003, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x7003, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4004100, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004100, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP16_DOP32 ("zextb", + OPCODE_INFO2 (0x7400, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x7400, + (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc40054e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc40054e0, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP16_DOP32 ("zexth", + OPCODE_INFO2 (0x7401, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x7401, + (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc40055e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc40055e0, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP16_DOP32 ("sextb", + OPCODE_INFO2 (0x7402, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x7402, + (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc40058e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc40058e0, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP16_DOP32 ("sexth", + OPCODE_INFO2 (0x7403, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0x7403, + (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc40059e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc40059e0, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("zext", + OPCODE_INFO4 (0xc4005400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9, IMM5b, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("sext", + OPCODE_INFO4 (0xc4005800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (5_9, IMM5b, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#define _TRANSFER 2 + OP16_OP32 ("rts", + OPCODE_INFO0 (0x783c), + CSKYV2_ISA_E1, + OPCODE_INFO0 (0xe8cf0000), + CSKYV2_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 1 + OP16_OP32 ("jmp", + OPCODE_INFO1 (0x7800, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xe8c00000, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _TRANSFER +#define _TRANSFER 0 + OP16_OP32 ("revb", + OPCODE_INFO2 (0x7802, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, + OPCODE_INFO2 (0xc4006080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16_OP32 ("revh", + OPCODE_INFO2 (0x7803, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, + OPCODE_INFO2 (0xc4006100, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16_OP32 ("jsr", + OPCODE_INFO1 (0x7bc1, + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xe8e00000, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP16_DOP32 ("mult", + OPCODE_INFO2 (0x7c00, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x7c00, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4008420, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4008420, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16 ("mul", + OPCODE_INFO2 (0x7c00, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + DOP16_DOP32 ("mulsh", + OPCODE_INFO2 (0x7c01, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x7c01, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), + (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3, + OPCODE_INFO3 (0xc4009020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4009020, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP16 ("muls.h", + OPCODE_INFO2 (0x7c01, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP32 ("mulsw", + OPCODE_INFO3 (0xc4009420, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4009420, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP), + OP16_OP32 ("ld.b", + SOPCODE_INFO2 (0x8000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP16_OP32 ("ldb", + SOPCODE_INFO2 (0x8000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP16_OP32 ("st.b", + SOPCODE_INFO2 (0xa000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + OP16_OP32 ("stb", + SOPCODE_INFO2 (0xa000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), + CSKYV2_ISA_E1), + + OP16_OP32 ("ld.h", + SOPCODE_INFO2 (0x8800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8001000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1), + OP16_OP32 ("ldh", + SOPCODE_INFO2 (0x8800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8001000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1), + OP16_OP32 ("st.h", + SOPCODE_INFO2 (0xa800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc001000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1), + OP16_OP32 ("sth", + SOPCODE_INFO2 (0xa800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc001000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), + CSKYV2_ISA_E1), + DOP16_OP32 ("ld.w", + SOPCODE_INFO2 (0x9000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), + SOPCODE_INFO2 (0x9800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1), + DOP16_OP32 ("ldw", + SOPCODE_INFO2 (0x9000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), + SOPCODE_INFO2 (0x9800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1), + DOP16_OP32 ("ld", + SOPCODE_INFO2 (0x9000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), + SOPCODE_INFO2 (0x9800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xd8002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1), + DOP16_OP32 ("st.w", + SOPCODE_INFO2 (0xb000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), + SOPCODE_INFO2 (0xb800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1), + DOP16_OP32 ("stw", + SOPCODE_INFO2 (0xb000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), + SOPCODE_INFO2 (0xb800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1), + DOP16_OP32 ("st", + SOPCODE_INFO2 (0xb000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), + SOPCODE_INFO2 (0xb800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1, + SOPCODE_INFO2 (0xdc002000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), + CSKYV2_ISA_E1), +#ifdef BUILD_AS + DOP16_DOP32_WITH_WORK ("addi", + OPCODE_INFO2 (0x2000, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x2000, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xe4000000, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0xe4000000, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, + v2_work_addi), +#else + DOP16 ("addi", + OPCODE_INFO2 (0x2000, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x5802, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + DOP16 ("addi", + OPCODE_INFO3 (0x1800, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_7, IMM8b_LS2, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x1400, + (NONE, REGsp, OPRND_SHIFT_0_BIT), + (NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + DOP32 ("addi", + OPCODE_INFO3 (0xe4000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0xcc1c0000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (NONE, REG_r28, OPRND_SHIFT_0_BIT), + (0_17, OIMM18b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), +#endif +#ifdef BUILD_AS + DOP16_DOP32_WITH_WORK ("subi", + OPCODE_INFO2 (0x2800, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x2800, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xe4001000, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0xe4001000, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, IMM32b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, v2_work_subi), +#else + DOP16 ("subi", + OPCODE_INFO2 (0x2800, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x5803, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), + OP32 ("subi", + OPCODE_INFO3 (0xe4001000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP16 ("subi", + OPCODE_INFO3 (0x1420, + (NONE, REGsp, OPRND_SHIFT_0_BIT), + (NONE, REGsp, OPRND_SHIFT_0_BIT), + (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1), +#endif + DOP16_DOP32_WITH_WORK ("addu", + OPCODE_INFO2 (0x6000, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x5800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4000020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000020, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + v2_work_add_sub), + DOP16_DOP32_WITH_WORK ("add", + OPCODE_INFO2 (0x6000, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x5800, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4000020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000020, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + v2_work_add_sub), + DOP16_DOP32_WITH_WORK ("subu", + OPCODE_INFO2 (0x6002, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x5801, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4000080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000080, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + v2_work_add_sub), + DOP16_DOP32_WITH_WORK ("sub", + OPCODE_INFO2 (0x6002, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + OPCODE_INFO3 (0x5801, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO3 (0xc4000080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000080, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + v2_work_add_sub), + OP32_WITH_WORK ("fmovis", + OPCODE_INFO2 (0xf4001c00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (4_7or16_24, SFLOAT, OPRND_SHIFT_2_BIT)), + CSKY_ISA_FLOAT_1E3, + float_work_fmovi), + OP32_WITH_WORK ("fmovid", + OPCODE_INFO2 (0xf4001e00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (4_7or16_24, DFLOAT, OPRND_SHIFT_2_BIT)), + CSKY_ISA_FLOAT_3E4, + float_work_fmovi), +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM26BY2 + OP32 ("bsr", + OPCODE_INFO1 (0xe0000000, + (0_25, OFF26b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1), +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18 + OP32 ("lrs.b", + OPCODE_INFO2 (0xcc000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("srs.b", + OPCODE_INFO2 (0xcc100000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 + OP32 ("lrs.h", + OPCODE_INFO2 (0xcc040000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("srs.h", + OPCODE_INFO2 (0xcc140000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 + OP32 ("flrws", + OPCODE_INFO2 (0xf4003800, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), + CSKY_ISA_FLOAT_1E3), + OP32 ("flrwd", + OPCODE_INFO2 (0xf4003900, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), + CSKY_ISA_FLOAT_3E4), +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 + OP32_WITH_WORK ("lrs.w", + OPCODE_INFO2 (0xcc080000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3, + v2_work_lrsrsw), + OP32_WITH_WORK ("srs.w", + OPCODE_INFO2 (0xcc180000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3, + v2_work_lrsrsw), + +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 + OP32_WITH_WORK ("jsri", + OPCODE_INFO1 (0xeae00000, + (0_15, OFF16b, OPRND_SHIFT_2_BIT)), + CSKYV2_ISA_2E3, + v2_work_jsri), +#undef _RELOC32 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY2 + OP32 ("bez", + OPCODE_INFO2 (0xe9000000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), + OP32 ("bnez", + OPCODE_INFO2 (0xe9200000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), + OP32 ("bhz", + OPCODE_INFO2 (0xe9400000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), + OP32 ("blsz", + OPCODE_INFO2 (0xe9600000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), + OP32 ("blz", + OPCODE_INFO2 (0xe9800000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), + OP32 ("bhsz", + OPCODE_INFO2 (0xe9a00000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_2E3), +#undef _RELAX +#undef _RELOC16 +#undef _TRANSFER +#define _TRANSFER 1 +#define _RELAX 1 +#define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM10BY2 + OP16_OP32 ("br", + OPCODE_INFO1 (0x0400, + (0_9, UNCOND10b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xe8000000, + (0_15, UNCOND16b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1), +#undef _TRANSFER +#define _TRANSFER 0 + OP16_OP32 ("bt", + OPCODE_INFO1 (0x0800, + (0_9, COND10b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xe8600000, + (0_15, COND16b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_1E2), + OP16_OP32 ("bf", + OPCODE_INFO1 (0x0c00, + (0_9, COND10b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xe8400000, + (0_15, COND16b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_1E2), +#undef _RELOC16 +#undef _RELOC32 +#undef _RELAX +#define _RELOC16 0 +#define _RELOC32 0 +#define _RELAX 0 +#undef _TRANSFER +#define _TRANSFER 1 + OP16_WITH_WORK ("jbr", + OPCODE_INFO1 (0x0400, + (0_10, UNCOND10b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + v2_work_jbr), +#undef _TRANSFER +#define _TRANSFER 0 + OP16_WITH_WORK ("jbt", + OPCODE_INFO1 (0x0800, + (0_10, COND10b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + v2_work_jbtf), + OP16_WITH_WORK ("jbf", + OPCODE_INFO1 (0x0c00, + (0_10, COND10b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + v2_work_jbtf), + OP32_WITH_WORK ("jbsr", + OPCODE_INFO1 (0xe0000000, + (0_25, OFF26b, OPRND_SHIFT_1_BIT)), + CSKYV2_ISA_E1, + v2_work_jbsr), + OP32_WITH_WORK ("movih", + OPCODE_INFO2 (0xea200000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, IMM16b_MOVIH, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, + v2_work_movih), + OP32_WITH_WORK ("ori", + OPCODE_INFO3 (0xec000000, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, IMM16b_ORI, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2, + v2_work_ori), + DOP32_WITH_WORK ("bgeni", + OPCODE_INFO2 (0xea000000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4, IMM4b, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xea200000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + v2_work_bgeni), +#undef _RELOC16 +#undef _RELOC32 +#define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM7BY4 +#define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 + DOP16_OP32_WITH_WORK ("lrw", + OPCODE_INFO2 (0x1000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4or8_9, CONSTANT, OPRND_SHIFT_2_BIT)), + OPCODE_INFO2 (0x0000, + (5_7, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4or8_9, ELRW_CONSTANT, OPRND_SHIFT_2_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xea800000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, CONSTANT, OPRND_SHIFT_2_BIT)), + CSKYV2_ISA_E1, + v2_work_lrw), +#undef _RELOC16 +#undef _RELOC32 +#define _RELOC16 0 +#define _RELOC32 0 + +#undef _RELAX +#define _RELAX 1 + OP32 ("jbez", + OPCODE_INFO2 (0xe9000000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("jbnez", + OPCODE_INFO2 (0xe9200000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("jbhz", + OPCODE_INFO2 (0xe9400000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("jblsz", + OPCODE_INFO2 (0xe9600000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("jblz", + OPCODE_INFO2 (0xe9800000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + OP32 ("jbhsz", + OPCODE_INFO2 (0xe9a00000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), +#undef _RELAX +#define _RELAX 0 + + /* The followings are enhance DSP instructions. */ + OP32_WITH_WORK ("bloop", + OPCODE_INFO3 (0xe9c00000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT), + (12_15, BLOOP_OFF4b, OPRND_SHIFT_1_BIT)), + CSKY_ISA_DSP_ENHANCE, + dsp_work_bloop), + /* The followings are ld/st instructions. */ + OP32 ("ldbi.b", + OPCODE_INFO2 (0xd0008000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbi.h", + OPCODE_INFO2 (0xd0008400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbi.w", + OPCODE_INFO2 (0xd0008800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pldbi.d", + OPCODE_INFO2 (0xd0008c00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbi.hs", + OPCODE_INFO2 (0xd0009000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbi.bs", + OPCODE_INFO2 (0xd0009400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("stbi.b", + OPCODE_INFO2 (0xd4008000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("stbi.h", + OPCODE_INFO2 (0xd4008400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("stbi.w", + OPCODE_INFO2 (0xd4008800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbir.b", + OPCODE_INFO3 (0xd000a000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbir.h", + OPCODE_INFO3 (0xd000a400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbir.w", + OPCODE_INFO3 (0xd000a800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pldbir.d", + OPCODE_INFO3 (0xd000ac00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbir.bs", + OPCODE_INFO3 (0xd000b000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("ldbir.hs", + OPCODE_INFO3 (0xd000b400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("stbir.b", + OPCODE_INFO3 (0xd400a000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("stbir.h", + OPCODE_INFO3 (0xd400a400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("stbir.w", + OPCODE_INFO3 (0xd400a800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + /* The followings are add/sub instructions. */ + OP32 ("padd.8", + OPCODE_INFO3 (0xf800c040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("padd.16", + OPCODE_INFO3 (0xf800c000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("padd.u8.s", + OPCODE_INFO3 (0xf800c140, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("padd.s8.s", + OPCODE_INFO3 (0xf800c1c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("padd.u16.s", + OPCODE_INFO3 (0xf800c100, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("padd.s16.s", + OPCODE_INFO3 (0xf800c180, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("add.u32.s", + OPCODE_INFO3 (0xf800c120, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("add.s32.s", + OPCODE_INFO3 (0xf800c1a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psub.8", + OPCODE_INFO3 (0xf800c440, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psub.16", + OPCODE_INFO3 (0xf800c400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psub.u8.s", + OPCODE_INFO3 (0xf800c540, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psub.s8.s", + OPCODE_INFO3 (0xf800c5c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psub.u16.s", + OPCODE_INFO3 (0xf800c500, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psub.s16.s", + OPCODE_INFO3 (0xf800c580, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("sub.u32.s", + OPCODE_INFO3 (0xf800c520, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("sub.s32.s", + OPCODE_INFO3 (0xf800c5a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("paddh.u8", + OPCODE_INFO3 (0xf800c240, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("paddh.s8", + OPCODE_INFO3 (0xf800c2c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("paddh.u16", + OPCODE_INFO3 (0xf800c200, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("paddh.s16", + OPCODE_INFO3 (0xf800c280, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("addh.u32", + OPCODE_INFO3 (0xf800c220, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("addh.s32", + OPCODE_INFO3 (0xf800c2a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psubh.u8", + OPCODE_INFO3 (0xf800c640, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psubh.s8", + OPCODE_INFO3 (0xf800c6c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psubh.u16", + OPCODE_INFO3 (0xf800c600, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psubh.s16", + OPCODE_INFO3 (0xf800c680, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("subh.u32", + OPCODE_INFO3 (0xf800c620, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("subh.s32", + OPCODE_INFO3 (0xf800c6a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("add.64", + OPCODE_INFO3 (0xf800c060, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("sub.64", + OPCODE_INFO3 (0xf800c460, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("add.u64.s", + OPCODE_INFO3 (0xf800c160, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("add.s64.s", + OPCODE_INFO3 (0xf800c1e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("sub.u64.s", + OPCODE_INFO3 (0xf800c560, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("sub.s64.s", + OPCODE_INFO3 (0xf800c5e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + /* The following are comparison instructions. */ + OP32 ("pasx.16", + OPCODE_INFO3 (0xf800c860, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psax.16", + OPCODE_INFO3 (0xf800cc60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasx.u16.s", + OPCODE_INFO3 (0xf800c960, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasx.s16.s", + OPCODE_INFO3 (0xf800c9e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psax.u16.s", + OPCODE_INFO3 (0xf800cd60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psax.s16.s", + OPCODE_INFO3 (0xf800cde0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasxh.u16", + OPCODE_INFO3 (0xf800ca60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasxh.s16", + OPCODE_INFO3 (0xf800cae0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psaxh.u16", + OPCODE_INFO3 (0xf800ce60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psaxh.s16", + OPCODE_INFO3 (0xf800cee0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmpne.8", + OPCODE_INFO3 (0xf800c840, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmpne.16", + OPCODE_INFO3 (0xf800c800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmphs.u8", + OPCODE_INFO3 (0xf800c940, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmphs.s8", + OPCODE_INFO3 (0xf800c9c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmphs.u16", + OPCODE_INFO3 (0xf800c900, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmphs.s16", + OPCODE_INFO3 (0xf800c980, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmplt.u8", + OPCODE_INFO3 (0xf800ca40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmplt.s8", + OPCODE_INFO3 (0xf800cac0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmplt.u16", + OPCODE_INFO3 (0xf800ca00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pcmplt.s16", + OPCODE_INFO3 (0xf800ca80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmax.u8", + OPCODE_INFO3 (0xf800cc40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmax.s8", + OPCODE_INFO3 (0xf800ccc0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmax.u16", + OPCODE_INFO3 (0xf800cc00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmax.s16", + OPCODE_INFO3 (0xf800cc80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("max.u32", + OPCODE_INFO3 (0xf800cc20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("max.s32", + OPCODE_INFO3 (0xf800cca0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmin.u8", + OPCODE_INFO3 (0xf800cd40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmin.s8", + OPCODE_INFO3 (0xf800cdc0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmin.u16", + OPCODE_INFO3 (0xf800cd00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmin.s16", + OPCODE_INFO3 (0xf800cd80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("min.u32", + OPCODE_INFO3 (0xf800cd20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("min.s32", + OPCODE_INFO3 (0xf800cda0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("sel", + OPCODE_INFO4 (0xf8009000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT), + (5_9, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + /* The followings are miscs. */ + OP32 ("psabsa.u8", + OPCODE_INFO3 (0xf800e040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("psabsaa.u8", + OPCODE_INFO3 (0xf800e140, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("divul", + OPCODE_INFO3 (0xf800e260, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("divsl", + OPCODE_INFO3 (0xf800e2e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaca.s8", + OPCODE_INFO3 (0xf800e4c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + /* The followings are shift instructions. */ + OP32 ("asri.s32.r", + OPCODE_INFO3 (0xf800d1a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("asr.s32.r", + OPCODE_INFO3 (0xf800d1e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("lsri.u32.r", + OPCODE_INFO3 (0xf800d320, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("lsr.u32.r", + OPCODE_INFO3 (0xf800d360, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("lsli.u32.s", + OPCODE_INFO3 (0xf800d520, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("lsli.s32.s", + OPCODE_INFO3 (0xf800d5a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("lsl.u32.s", + OPCODE_INFO3 (0xf800d560, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("lsl.s32.s", + OPCODE_INFO3 (0xf800d5e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasri.s16", + OPCODE_INFO3 (0xf800d080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasr.s16", + OPCODE_INFO3 (0xf800d0c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasri.s16.r", + OPCODE_INFO3 (0xf800d180, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pasr.s16.r", + OPCODE_INFO3 (0xf800d1c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsri.u16", + OPCODE_INFO3 (0xf800d200, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsr.u16", + OPCODE_INFO3 (0xf800d240, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsri.u16.r", + OPCODE_INFO3 (0xf800d300, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsr.u16.r", + OPCODE_INFO3 (0xf800d340, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsli.u16", + OPCODE_INFO3 (0xf800d400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsl.u16", + OPCODE_INFO3 (0xf800d440, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsli.u16.s", + OPCODE_INFO3 (0xf800d500, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsli.s16.s", + OPCODE_INFO3 (0xf800d580, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsl.u16.s", + OPCODE_INFO3 (0xf800d540, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("plsl.s16.s", + OPCODE_INFO3 (0xf800d5c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + /* The following are package & unpackage instructions. */ + OP32 ("pkg", + OPCODE_INFO5 (0xf800a000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (5_8, IMM4b, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT), + (9_12, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("dexti", + OPCODE_INFO4 (0xf8009800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT), + (5_9, IMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("dext", + OPCODE_INFO4 (0xf8009c00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT), + (5_9, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pkgll", + OPCODE_INFO3 (0xf800d840, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pkghh", + OPCODE_INFO3 (0xf800d860, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pext.u8.e", + OPCODE_INFO2 (0xf800d900, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pext.s8.e", + OPCODE_INFO2 (0xf800d980, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pextx.u8.e", + OPCODE_INFO2 (0xf800d920, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pextx.s8.e", + OPCODE_INFO2 (0xf800d9a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("narl", + OPCODE_INFO3 (0xf800da00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("narh", + OPCODE_INFO3 (0xf800da20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("narlx", + OPCODE_INFO3 (0xf800da40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("narhx", + OPCODE_INFO3 (0xf800da60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("clipi.u32", + OPCODE_INFO3 (0xf800db00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("clipi.s32", + OPCODE_INFO3 (0xf800db80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("clip.u32", + OPCODE_INFO3 (0xf800db20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("clip.s32", + OPCODE_INFO3 (0xf800dba0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pclipi.u16", + OPCODE_INFO3 (0xf800db40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pclipi.s16", + OPCODE_INFO3 (0xf800dbc0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pclip.u16", + OPCODE_INFO3 (0xf800db60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pclip.s16", + OPCODE_INFO3 (0xf800dbe0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pabs.s8.s", + OPCODE_INFO2 (0xf800dc80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pabs.s16.s", + OPCODE_INFO2 (0xf800dca0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("abs.s32.s", + OPCODE_INFO2 (0xf800dcc0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pneg.s8.s", + OPCODE_INFO2 (0xf800dd80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pneg.s16.s", + OPCODE_INFO2 (0xf800dda0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("neg.s32.s", + OPCODE_INFO2 (0xf800ddc0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("dup.8", + OPCODE_INFO3 (0xf800de00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6, IMM2b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("dup.16", + OPCODE_INFO3 (0xf800df00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6, IMM1b, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + /* The followings are multiplication instructions. */ + OP32 ("mul.u32", + OPCODE_INFO3 (0xf8008000, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_3E3R1), + OP32 ("mul.s32", + OPCODE_INFO3 (0xf8008200, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_3E3R1), + OP32 ("mula.u32", + OPCODE_INFO3 (0xf8008080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_3E3R1), + OP32 ("mula.s32", + OPCODE_INFO3 (0xf8008280, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_3E3R1), + OP32 ("mula.32.l", + OPCODE_INFO3 (0xf8008440, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_3E3R1), + OP32 ("mulall.s16.s", + OPCODE_INFO3 (0xf80081a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_3E3R1), + OP32 ("muls.u32", + OPCODE_INFO3 (0xf80080c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("muls.s32", + OPCODE_INFO3 (0xf80082c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mula.u32.s", + OPCODE_INFO3 (0xf8008180, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mula.s32.s", + OPCODE_INFO3 (0xf8008380, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("muls.u32.s", + OPCODE_INFO3 (0xf80081c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("muls.s32.s", + OPCODE_INFO3 (0xf80083c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mul.s32.h", + OPCODE_INFO3 (0xf8008400, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mul.s32.rh", + OPCODE_INFO3 (0xf8008600, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmul.s32.h", + OPCODE_INFO3 (0xf8008500, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmul.s32.rh", + OPCODE_INFO3 (0xf8008700, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mula.s32.hs", + OPCODE_INFO3 (0xf8008580, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("muls.s32.hs", + OPCODE_INFO3 (0xf80085c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mula.s32.rhs", + OPCODE_INFO3 (0xf8008780, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("muls.s32.rhs", + OPCODE_INFO3 (0xf80087c0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulxl.s32", + OPCODE_INFO3 (0xf8008800, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulxl.s32.r", + OPCODE_INFO3 (0xf8008a00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulxh.s32", + OPCODE_INFO3 (0xf8008c00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulxh.s32.r", + OPCODE_INFO3 (0xf8008e00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulxl.s32", + OPCODE_INFO3 (0xf8008900, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulxl.s32.r", + OPCODE_INFO3 (0xf8008b00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulxh.s32", + OPCODE_INFO3 (0xf8008d00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulxh.s32.r", + OPCODE_INFO3 (0xf8008f00, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaxl.s32.s", + OPCODE_INFO3 (0xf8008980, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaxl.s32.rs", + OPCODE_INFO3 (0xf8008b80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaxh.s32.s", + OPCODE_INFO3 (0xf8008d80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaxh.s32.rs", + OPCODE_INFO3 (0xf8008f80, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulll.s16", + OPCODE_INFO3 (0xf8008020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulhh.s16", + OPCODE_INFO3 (0xf8008260, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulhl.s16", + OPCODE_INFO3 (0xf8008220, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulll.s16", + OPCODE_INFO3 (0xf8008120, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulhh.s16", + OPCODE_INFO3 (0xf8008360, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("rmulhl.s16", + OPCODE_INFO3 (0xf8008320, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulahh.s16.s", + OPCODE_INFO3 (0xf80083e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulahl.s16.s", + OPCODE_INFO3 (0xf80083a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulall.s16.e", + OPCODE_INFO3 (0xf80080a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulahh.s16.e", + OPCODE_INFO3 (0xf80082e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulahl.s16.e", + OPCODE_INFO3 (0xf80080e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmul.u16", + OPCODE_INFO3 (0xf80084a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmulx.u16", + OPCODE_INFO3 (0xf80084e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmul.s16", + OPCODE_INFO3 (0xf8008420, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("pmulx.s16", + OPCODE_INFO3 (0xf8008460, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("prmul.s16", + OPCODE_INFO3 (0xf8008520, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("prmulx.s16", + OPCODE_INFO3 (0xf8008560, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("prmul.s16.h", + OPCODE_INFO3 (0xf80085a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("prmul.s16.rh", + OPCODE_INFO3 (0xf80087a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("prmulx.s16.h", + OPCODE_INFO3 (0xf80085e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("prmulx.s16.rh", + OPCODE_INFO3 (0xf80087e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulca.s16.s", + OPCODE_INFO3 (0xf8008920, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulcax.s16.s", + OPCODE_INFO3 (0xf8008960, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulcs.s16", + OPCODE_INFO3 (0xf8008a20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulcsr.s16", + OPCODE_INFO3 (0xf8008a60, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulcsx.s16", + OPCODE_INFO3 (0xf8008c20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaca.s16.s", + OPCODE_INFO3 (0xf80089a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacax.s16.s", + OPCODE_INFO3 (0xf80089e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacs.s16.s", + OPCODE_INFO3 (0xf8008ba0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacsr.s16.s", + OPCODE_INFO3 (0xf8008be0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacsx.s16.s", + OPCODE_INFO3 (0xf8008da0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulsca.s16.s", + OPCODE_INFO3 (0xf8008de0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulscax.s16.s", + OPCODE_INFO3 (0xf8008fa0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulaca.s16.e", + OPCODE_INFO3 (0xf80088a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacax.s16.e", + OPCODE_INFO3 (0xf80088e0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacs.s16.e", + OPCODE_INFO3 (0xf8008aa0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacsr.s16.e", + OPCODE_INFO3 (0xf8008ae0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulacsx.s16.e", + OPCODE_INFO3 (0xf8008ca0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulsca.s16.e", + OPCODE_INFO3 (0xf8008ce0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + OP32 ("mulscax.s16.e", + OPCODE_INFO3 (0xf8008ea0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_DSP_ENHANCE), + + /* The followings are vdsp instructions for ck810. */ + OP32 ("vdup.8", + OPCODE_INFO2 (0xf8000e80, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdup.16", + OPCODE_INFO2 (0xf8100e80, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdup.32", + OPCODE_INFO2 (0xfa000e80, + (0_3, FREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmfvr.u8", + OPCODE_INFO2 (0xf8001200, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmfvr.u16", + OPCODE_INFO2 (0xf8001220, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmfvr.u32", + OPCODE_INFO2 (0xf8001240, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmfvr.s8", + OPCODE_INFO2 (0xf8001280, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmfvr.s16", + OPCODE_INFO2 (0xf80012a0, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmtvr.u8", + OPCODE_INFO2 (0xf8001300, + (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmtvr.u16", + OPCODE_INFO2 (0xf8001320, + (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmtvr.u32", + OPCODE_INFO2 (0xf8001340, + (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vldd.8", + SOPCODE_INFO2 (0xf8002000, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldd.16", + SOPCODE_INFO2 (0xf8002100, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldd.32", + SOPCODE_INFO2 (0xf8002200, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldq.8", + SOPCODE_INFO2 (0xf8002400, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldq.16", + SOPCODE_INFO2 (0xf8002500, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldq.32", + SOPCODE_INFO2 (0xf8002600, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstd.8", + SOPCODE_INFO2 (0xf8002800, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstd.16", + SOPCODE_INFO2 (0xf8002900, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstd.32", + SOPCODE_INFO2 (0xf8002a00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstq.8", + SOPCODE_INFO2 (0xf8002c00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstq.16", + SOPCODE_INFO2 (0xf8002d00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstq.32", + SOPCODE_INFO2 (0xf8002e00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldrd.8", + SOPCODE_INFO2 (0xf8003000, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldrd.16", + SOPCODE_INFO2 (0xf8003100, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldrd.32", + SOPCODE_INFO2 (0xf8003200, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldrq.8", + SOPCODE_INFO2 (0xf8003400, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldrq.16", + SOPCODE_INFO2 (0xf8003500, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vldrq.32", + SOPCODE_INFO2 (0xf8003600, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstrd.8", + SOPCODE_INFO2 (0xf8003800, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstrd.16", + SOPCODE_INFO2 (0xf8003900, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstrd.32", + SOPCODE_INFO2 (0xf8003a00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstrq.8", + SOPCODE_INFO2 (0xf8003c00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstrq.16", + SOPCODE_INFO2 (0xf8003d00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vstrq.32", + SOPCODE_INFO2 (0xf8003e00, + (0_3, FREG, OPRND_SHIFT_0_BIT), + BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), + (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), + CSKY_ISA_VDSP), + OP32 ("vmov", + OPCODE_INFO2 (0xf8000c00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.eu8", + OPCODE_INFO2 (0xf8000060, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.eu16", + OPCODE_INFO2 (0xf8100060, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.es8", + OPCODE_INFO2 (0xf8000070, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.es16", + OPCODE_INFO2 (0xf8100070, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.eu8", + OPCODE_INFO2 (0xf8000c20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.eu16", + OPCODE_INFO2 (0xf8100c20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.es8", + OPCODE_INFO2 (0xf8000c30, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.es16", + OPCODE_INFO2 (0xf8100c30, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u16.l", + OPCODE_INFO2 (0xf8100d00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u32.l", + OPCODE_INFO2 (0xfa000d00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s16.l", + OPCODE_INFO2 (0xf8100d10, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s32.l", + OPCODE_INFO2 (0xfa000d10, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u16.sl", + OPCODE_INFO2 (0xf8100d40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u32.sl", + OPCODE_INFO2 (0xfa000d40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s16.sl", + OPCODE_INFO2 (0xf8100d50, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s32.sl", + OPCODE_INFO2 (0xfa000d50, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u16.h", + OPCODE_INFO2 (0xf8100d60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u32.h", + OPCODE_INFO2 (0xfa000d60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s16.h", + OPCODE_INFO2 (0xf8100d70, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s32.h", + OPCODE_INFO2 (0xfa000d70, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u16.rh", + OPCODE_INFO2 (0xf8100d80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.u32.rh", + OPCODE_INFO2 (0xfa000d80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s16.rh", + OPCODE_INFO2 (0xf8100d90, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmov.s32.rh", + OPCODE_INFO2 (0xfa000d90, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vstou.u16.sl", + OPCODE_INFO2 (0xf8100dc0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vstou.u32.sl", + OPCODE_INFO2 (0xfa000dc0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vstou.s16.sl", + OPCODE_INFO2 (0xf8100dd0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vstou.s32.sl", + OPCODE_INFO2 (0xfa000dd0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vrev.8", + OPCODE_INFO2 (0xf8000e60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vrev.16", + OPCODE_INFO2 (0xf8100e60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vrev.32", + OPCODE_INFO2 (0xfa000e60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcnt1.8", + OPCODE_INFO2 (0xf8000ea0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vclz.8", + OPCODE_INFO2 (0xf8000ec0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vclz.16", + OPCODE_INFO2 (0xf8100ec0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vclz.32", + OPCODE_INFO2 (0xfa000ec0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcls.u8", + OPCODE_INFO2 (0xf8000ee0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcls.u16", + OPCODE_INFO2 (0xf8100ee0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcls.u32", + OPCODE_INFO2 (0xfa000ee0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcls.s8", + OPCODE_INFO2 (0xf8000ef0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcls.s16", + OPCODE_INFO2 (0xf8100ef0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcls.s32", + OPCODE_INFO2 (0xfa000ef0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.s8", + OPCODE_INFO2 (0xf8001010, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.s16", + OPCODE_INFO2 (0xf8101010, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.s32", + OPCODE_INFO2 (0xfa001010, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.u8.s", + OPCODE_INFO2 (0xf8001040, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.u16.s", + OPCODE_INFO2 (0xf8101040, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.u32.s", + OPCODE_INFO2 (0xfa001040, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.s8.s", + OPCODE_INFO2 (0xf8001050, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.s16.s", + OPCODE_INFO2 (0xf8101050, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vabs.s32.s", + OPCODE_INFO2 (0xfa001050, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.u8", + OPCODE_INFO2 (0xf8001080, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.u16", + OPCODE_INFO2 (0xf8101080, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.u32", + OPCODE_INFO2 (0xfa001080, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.s8", + OPCODE_INFO2 (0xf8001090, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.s16", + OPCODE_INFO2 (0xf8101090, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.s32", + OPCODE_INFO2 (0xfa001090, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.u8.s", + OPCODE_INFO2 (0xf80010c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.u16.s", + OPCODE_INFO2 (0xf81010c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.u32.s", + OPCODE_INFO2 (0xfa0010c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.s8.s", + OPCODE_INFO2 (0xf80010d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.s16.s", + OPCODE_INFO2 (0xf81010d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vneg.s32.s", + OPCODE_INFO2 (0xfa0010d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphsz.u8", + OPCODE_INFO2 (0xf8000880, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphsz.u16", + OPCODE_INFO2 (0xf8100880, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphsz.u32", + OPCODE_INFO2 (0xfa000880, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphsz.s8", + OPCODE_INFO2 (0xf8000890, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphsz.s16", + OPCODE_INFO2 (0xf8100890, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphsz.s32", + OPCODE_INFO2 (0xfa000890, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpltz.u8", + OPCODE_INFO2 (0xf80008a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpltz.u16", + OPCODE_INFO2 (0xf81008a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpltz.u32", + OPCODE_INFO2 (0xfa0008a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpltz.s8", + OPCODE_INFO2 (0xf80008b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpltz.s16", + OPCODE_INFO2 (0xf81008b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpltz.s32", + OPCODE_INFO2 (0xfa0008b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpnez.u8", + OPCODE_INFO2 (0xf80008c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpnez.u16", + OPCODE_INFO2 (0xf81008c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpnez.u32", + OPCODE_INFO2 (0xfa0008c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpnez.s8", + OPCODE_INFO2 (0xf80008d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpnez.s16", + OPCODE_INFO2 (0xf81008d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpnez.s32", + OPCODE_INFO2 (0xfa0008d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtrch.8", + OPCODE_INFO3 (0xf8000f40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtrch.16", + OPCODE_INFO3 (0xf8100f40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtrch.32", + OPCODE_INFO3 (0xfa000f40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtrcl.8", + OPCODE_INFO3 (0xf8000f60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtrcl.16", + OPCODE_INFO3 (0xf8100f60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtrcl.32", + OPCODE_INFO3 (0xfa000f60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.u8", + OPCODE_INFO3 (0xf8000000, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.u16", + OPCODE_INFO3 (0xf8100000, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.u32", + OPCODE_INFO3 (0xfa000000, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.s8", + OPCODE_INFO3 (0xf8000010, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.s16", + OPCODE_INFO3 (0xf8100010, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.s32", + OPCODE_INFO3 (0xfa000010, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.eu8", + OPCODE_INFO3 (0xf8000020, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.eu16", + OPCODE_INFO3 (0xf8100020, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.es8", + OPCODE_INFO3 (0xf8000030, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.es16", + OPCODE_INFO3 (0xf8100030, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.u8", + OPCODE_INFO3 (0xf8000040, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.u16", + OPCODE_INFO3 (0xf8100040, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.u32", + OPCODE_INFO3 (0xfa000040, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.s8", + OPCODE_INFO3 (0xf8000050, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.s16", + OPCODE_INFO3 (0xf8100050, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcadd.s32", + OPCODE_INFO3 (0xfa000050, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xu16.sl", + OPCODE_INFO3 (0xf8100140, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xu32.sl", + OPCODE_INFO3 (0xfa000140, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xs16.sl", + OPCODE_INFO3 (0xf8100150, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xs32.sl", + OPCODE_INFO3 (0xfa000150, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xu16", + OPCODE_INFO3 (0xf8100160, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xu32", + OPCODE_INFO3 (0xfa000160, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xs16", + OPCODE_INFO3 (0xf8100170, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.xs32", + OPCODE_INFO3 (0xfa000170, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.u8", + OPCODE_INFO3 (0xf8000180, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.u16", + OPCODE_INFO3 (0xf8100180, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.u32", + OPCODE_INFO3 (0xfa000180, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.s8", + OPCODE_INFO3 (0xf8000190, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.s16", + OPCODE_INFO3 (0xf8100190, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.s32", + OPCODE_INFO3 (0xfa000190, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.u8.r", + OPCODE_INFO3 (0xf80001a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.u16.r", + OPCODE_INFO3 (0xf81001a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.u32.r", + OPCODE_INFO3 (0xfa0001a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.s8.r", + OPCODE_INFO3 (0xf80001b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.s16.r", + OPCODE_INFO3 (0xf81001b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vaddh.s32.r", + OPCODE_INFO3 (0xfa0001b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.u8.s", + OPCODE_INFO3 (0xf80001c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.u16.s", + OPCODE_INFO3 (0xf81001c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.u32.s", + OPCODE_INFO3 (0xfa0001c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.s8.s", + OPCODE_INFO3 (0xf80001d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.s16.s", + OPCODE_INFO3 (0xf81001d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vadd.s32.s", + OPCODE_INFO3 (0xfa0001d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.u8", + OPCODE_INFO3 (0xf8000200, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.u16", + OPCODE_INFO3 (0xf8100200, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.u32", + OPCODE_INFO3 (0xfa000200, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.s8", + OPCODE_INFO3 (0xf8000210, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.s16", + OPCODE_INFO3 (0xf8100210, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.s32", + OPCODE_INFO3 (0xfa000210, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.eu8", + OPCODE_INFO3 (0xf8000220, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.eu16", + OPCODE_INFO3 (0xf8100220, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.eu32", + OPCODE_INFO3 (0xfa000220, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.es8", + OPCODE_INFO3 (0xf8000230, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.es16", + OPCODE_INFO3 (0xf8100230, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.es32", + OPCODE_INFO3 (0xfa000230, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.u8", + OPCODE_INFO3 (0xf8000240, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.u16", + OPCODE_INFO3 (0xf8100240, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.u32", + OPCODE_INFO3 (0xfa000240, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.s8", + OPCODE_INFO3 (0xf8000250, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.s16", + OPCODE_INFO3 (0xf8100250, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.s32", + OPCODE_INFO3 (0xfa000250, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.eu8", + OPCODE_INFO3 (0xf8000260, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.eu16", + OPCODE_INFO3 (0xf8100260, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.es8", + OPCODE_INFO3 (0xf8000270, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabs.es16", + OPCODE_INFO3 (0xf8100270, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.u8", + OPCODE_INFO3 (0xf8000280, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.u16", + OPCODE_INFO3 (0xf8100280, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.u32", + OPCODE_INFO3 (0xfa000280, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.s8", + OPCODE_INFO3 (0xf8000290, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.s16", + OPCODE_INFO3 (0xf8100290, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.s32", + OPCODE_INFO3 (0xfa000290, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.eu8", + OPCODE_INFO3 (0xf80002a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.eu16", + OPCODE_INFO3 (0xf81002a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.es8", + OPCODE_INFO3 (0xf80002b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsabsa.es16", + OPCODE_INFO3 (0xf81002b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.xu16", + OPCODE_INFO3 (0xf8100360, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.xu32", + OPCODE_INFO3 (0xfa000360, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.xs16", + OPCODE_INFO3 (0xf8100370, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.xs32", + OPCODE_INFO3 (0xfa000370, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.u8", + OPCODE_INFO3 (0xf8000380, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.u16", + OPCODE_INFO3 (0xf8100380, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.u32", + OPCODE_INFO3 (0xfa000380, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.s8", + OPCODE_INFO3 (0xf8000390, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.s16", + OPCODE_INFO3 (0xf8100390, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.s32", + OPCODE_INFO3 (0xfa000390, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.u8.r", + OPCODE_INFO3 (0xf80003a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.u16.r", + OPCODE_INFO3 (0xf81003a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.u32.r", + OPCODE_INFO3 (0xfa0003a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.s8.r", + OPCODE_INFO3 (0xf80003b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.s16.r", + OPCODE_INFO3 (0xf81003b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsubh.s32.r", + OPCODE_INFO3 (0xfa0003b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.u8.s", + OPCODE_INFO3 (0xf80003c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.u16.s", + OPCODE_INFO3 (0xf81003c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.u32.s", + OPCODE_INFO3 (0xfa0003c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.s8.s", + OPCODE_INFO3 (0xf80003d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.s16.s", + OPCODE_INFO3 (0xf81003d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vsub.s32.s", + OPCODE_INFO3 (0xfa0003d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.u8", + OPCODE_INFO3 (0xf8000400, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.u16", + OPCODE_INFO3 (0xf8100400, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.u32", + OPCODE_INFO3 (0xfa000400, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.s8", + OPCODE_INFO3 (0xf8000410, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.s16", + OPCODE_INFO3 (0xf8100410, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.s32", + OPCODE_INFO3 (0xfa000410, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.eu8", + OPCODE_INFO3 (0xf8000420, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.eu16", + OPCODE_INFO3 (0xf8100420, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.es8", + OPCODE_INFO3 (0xf8000430, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmul.es16", + OPCODE_INFO3 (0xf8100430, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.u8", + OPCODE_INFO3 (0xf8000440, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.u16", + OPCODE_INFO3 (0xf8100440, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.u32", + OPCODE_INFO3 (0xfa000440, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.s8", + OPCODE_INFO3 (0xf8000450, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.s16", + OPCODE_INFO3 (0xf8100450, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.s32", + OPCODE_INFO3 (0xfa000450, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.eu8", + OPCODE_INFO3 (0xf8000460, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.eu16", + OPCODE_INFO3 (0xf8100460, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.eu32", + OPCODE_INFO3 (0xfa000460, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.es8", + OPCODE_INFO3 (0xf8000470, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.es16", + OPCODE_INFO3 (0xf8100470, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmula.es32", + OPCODE_INFO3 (0xfa000470, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.u8", + OPCODE_INFO3 (0xf8000480, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.u16", + OPCODE_INFO3 (0xf8100480, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.u32", + OPCODE_INFO3 (0xfa000480, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.s8", + OPCODE_INFO3 (0xf8000490, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.s16", + OPCODE_INFO3 (0xf8100490, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.s32", + OPCODE_INFO3 (0xfa000490, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.eu8", + OPCODE_INFO3 (0xf80004a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.eu16", + OPCODE_INFO3 (0xf81004a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.es8", + OPCODE_INFO3 (0xf80004b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmuls.es16", + OPCODE_INFO3 (0xf81004b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.u8", + OPCODE_INFO3 (0xf8000680, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.u16", + OPCODE_INFO3 (0xf8100680, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.u32", + OPCODE_INFO3 (0xfa000680, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s8", + OPCODE_INFO3 (0xf8000690, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s16", + OPCODE_INFO3 (0xf8100690, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s32", + OPCODE_INFO3 (0xfa000690, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.u8.r", + OPCODE_INFO3 (0xf80006c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.u16.r", + OPCODE_INFO3 (0xf81006c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.u32.r", + OPCODE_INFO3 (0xfa0006c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s8.r", + OPCODE_INFO3 (0xf80006d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s16.r", + OPCODE_INFO3 (0xf81006d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshr.s32.r", + OPCODE_INFO3 (0xfa0006d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.u8", + OPCODE_INFO3 (0xf8000780, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.u16", + OPCODE_INFO3 (0xf8100780, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.u32", + OPCODE_INFO3 (0xfa000780, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.s8", + OPCODE_INFO3 (0xf8000790, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.s16", + OPCODE_INFO3 (0xf8100790, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.s32", + OPCODE_INFO3 (0xfa000790, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.u8.s", + OPCODE_INFO3 (0xf80007c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.u16.s", + OPCODE_INFO3 (0xf81007c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.u32.s", + OPCODE_INFO3 (0xfa0007c0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.s8.s", + OPCODE_INFO3 (0xf80007d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.s16.s", + OPCODE_INFO3 (0xf81007d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vshl.s32.s", + OPCODE_INFO3 (0xfa0007d0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphs.u8", + OPCODE_INFO3 (0xf8000800, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphs.u16", + OPCODE_INFO3 (0xf8100800, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphs.u32", + OPCODE_INFO3 (0xfa000800, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphs.s8", + OPCODE_INFO3 (0xf8000810, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphs.s16", + OPCODE_INFO3 (0xf8100810, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmphs.s32", + OPCODE_INFO3 (0xfa000810, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmplt.u8", + OPCODE_INFO3 (0xf8000820, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmplt.u16", + OPCODE_INFO3 (0xf8100820, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmplt.u32", + OPCODE_INFO3 (0xfa000820, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmplt.s8", + OPCODE_INFO3 (0xf8000830, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmplt.s16", + OPCODE_INFO3 (0xf8100830, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmplt.s32", + OPCODE_INFO3 (0xfa000830, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpne.u8", + OPCODE_INFO3 (0xf8000840, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpne.u16", + OPCODE_INFO3 (0xf8100840, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpne.u32", + OPCODE_INFO3 (0xfa000840, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpne.s8", + OPCODE_INFO3 (0xf8000850, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpne.s16", + OPCODE_INFO3 (0xf8100850, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmpne.s32", + OPCODE_INFO3 (0xfa000850, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmax.u8", + OPCODE_INFO3 (0xf8000900, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmax.u16", + OPCODE_INFO3 (0xf8100900, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmax.u32", + OPCODE_INFO3 (0xfa000900, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmax.s8", + OPCODE_INFO3 (0xf8000910, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmax.s16", + OPCODE_INFO3 (0xf8100910, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmax.s32", + OPCODE_INFO3 (0xfa000910, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmin.u8", + OPCODE_INFO3 (0xf8000920, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmin.u16", + OPCODE_INFO3 (0xf8100920, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmin.u32", + OPCODE_INFO3 (0xfa000920, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmin.s8", + OPCODE_INFO3 (0xf8000930, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmin.s16", + OPCODE_INFO3 (0xf8100930, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vmin.s32", + OPCODE_INFO3 (0xfa000930, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmax.u8", + OPCODE_INFO3 (0xf8000980, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmax.u16", + OPCODE_INFO3 (0xf8100980, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmax.u32", + OPCODE_INFO3 (0xfa000980, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmax.s8", + OPCODE_INFO3 (0xf8000990, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmax.s16", + OPCODE_INFO3 (0xf8100990, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmax.s32", + OPCODE_INFO3 (0xfa000990, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmin.u8", + OPCODE_INFO3 (0xf80009a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmin.u16", + OPCODE_INFO3 (0xf81009a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmin.u32", + OPCODE_INFO3 (0xfa0009a0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmin.s8", + OPCODE_INFO3 (0xf80009b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmin.s16", + OPCODE_INFO3 (0xf81009b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vcmin.s32", + OPCODE_INFO3 (0xfa0009b0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vand.8", + OPCODE_INFO3 (0xf8000a00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vand.16", + OPCODE_INFO3 (0xf8100a00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vand.32", + OPCODE_INFO3 (0xfa000a00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vandn.8", + OPCODE_INFO3 (0xf8000a20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vandn.16", + OPCODE_INFO3 (0xf8100a20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vandn.32", + OPCODE_INFO3 (0xfa000a20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vor.8", + OPCODE_INFO3 (0xf8000a40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vor.16", + OPCODE_INFO3 (0xf8100a40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vor.32", + OPCODE_INFO3 (0xfa000a40, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vnor.8", + OPCODE_INFO3 (0xf8000a60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vnor.16", + OPCODE_INFO3 (0xf8100a60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vnor.32", + OPCODE_INFO3 (0xfa000a60, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vxor.8", + OPCODE_INFO3 (0xf8000a80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vxor.16", + OPCODE_INFO3 (0xf8100a80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vxor.32", + OPCODE_INFO3 (0xfa000a80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtst.8", + OPCODE_INFO3 (0xf8000b20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtst.16", + OPCODE_INFO3 (0xf8100b20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vtst.32", + OPCODE_INFO3 (0xfa000b20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vbpermz.8", + OPCODE_INFO3 (0xf8000f00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vbpermz.16", + OPCODE_INFO3 (0xf8100f00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vbpermz.32", + OPCODE_INFO3 (0xfa000f00, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vbperm.8", + OPCODE_INFO3 (0xf8000f20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vbperm.16", + OPCODE_INFO3 (0xf8100f20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vbperm.32", + OPCODE_INFO3 (0xfa000f20, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdch.8", + OPCODE_INFO3 (0xf8000fc0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdch.16", + OPCODE_INFO3 (0xf8100fc0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdch.32", + OPCODE_INFO3 (0xfa000fc0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdcl.8", + OPCODE_INFO3 (0xf8000fe0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdcl.16", + OPCODE_INFO3 (0xf8100fe0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vdcl.32", + OPCODE_INFO3 (0xfa000fe0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vich.8", + OPCODE_INFO3 (0xf8000f80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vich.16", + OPCODE_INFO3 (0xf8100f80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vich.32", + OPCODE_INFO3 (0xfa000f80, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vicl.8", + OPCODE_INFO3 (0xf8000fa0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vicl.16", + OPCODE_INFO3 (0xf8100fa0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + OP32 ("vicl.32", + OPCODE_INFO3 (0xfa000fa0, + (0_3, VREG, OPRND_SHIFT_0_BIT), + (16_19, VREG, OPRND_SHIFT_0_BIT), + (21_24, VREG, OPRND_SHIFT_0_BIT)), + CSKY_ISA_VDSP), + + /* The following are aliases for other instructions. */ + /* setc -> cmphs r0, r0 */ + OP16 ("setc", + OPCODE_INFO0 (0x6400), + CSKYV2_ISA_E1), + /* clrc -> cmpne r0, r0 */ + OP16 ("clrc", + OPCODE_INFO0 (0x6402), + CSKYV2_ISA_E1), + /* tstlt rd -> btsti rd,31 */ + OP32 ("tstlt", + OPCODE_INFO1 (0xc7e02880, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + /* idly4 -> idly 4 */ + OP32 ("idly4", + OPCODE_INFO0 (0xc0601c20), + CSKYV2_ISA_E1), + /* rsub rz, ry, rx -> subu rz, rx, ry */ + DOP32 ("rsub", + OPCODE_INFO3 (0xc4000080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4000080, + (0_4or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKYV2_ISA_1E2), + /* cmplei rd,X -> cmplti rd,X+1 */ + OP16_OP32 ("cmplei", + OPCODE_INFO2 (0x3820, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT), + (0_4, IMM5b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xeb200000, + (16_20, AREG, OPRND_SHIFT_0_BIT), + (0_15, IMM16b, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + /* cmpls -> cmphs */ + OP16_OP32 ("cmpls", + OPCODE_INFO2 (0x6400, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4000420, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + /* cmpgt -> cmplt */ + OP16_OP32 ("cmpgt", + OPCODE_INFO2 (0x6401, + (6_9, GREG0_15, OPRND_SHIFT_0_BIT), + (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4000440, + (21_25, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + /* tstle rd -> cmplti rd,1 */ + OP16_OP32 ("tstle", + OPCODE_INFO1 (0x3820, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xeb200000, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + /* tstne rd -> cmpnei rd,0 */ + OP16_OP32 ("tstne", + OPCODE_INFO1 (0x3840, + (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO1 (0xeb400000, + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + /* rotri rz, rx, imm5 -> rotli rz, rx, 32-imm5 */ + DOP32 ("rotri", + OPCODE_INFO3 (0xc4004900, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004900, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + DOP32 ("rori", + OPCODE_INFO3 (0xc4004900, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), + OPCODE_INFO2 (0xc4004900, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), + (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3), + + /* rotlc rd -> addc rd, rd/ addc rd, rd, rd */ + OP16_OP32_WITH_WORK ("rotlc", + OPCODE_INFO2 (0x6001, + (NONE, GREG0_15, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4000040, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, CONST1, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_2E3, + v2_work_rotlc), + /* not rd -> nor rd, rd, not rz, rx -> nor rz, rx, rx */ + OP16_OP32_WITH_WORK ("not", + OPCODE_INFO1 (0x6c02, + (NONE, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, + OPCODE_INFO2 (0xc4002480, + (NONE, AREG, OPRND_SHIFT_0_BIT), + (NONE, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_E1, v2_work_not), + + /* Special force 32 bits instruction. */ + OP32 ("xtrb0.32", + OPCODE_INFO2 (0xc4007020, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xtrb1.32", + OPCODE_INFO2 (0xc4007040, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xtrb2.32", + OPCODE_INFO2 (0xc4007080, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("xtrb3.32", + OPCODE_INFO2 (0xc4007100, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + OP32 ("ff0.32", + OPCODE_INFO2 (0xc4007c20, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + DOP32 ("ff1.32", + OPCODE_INFO2 (0xc4007c40, + (0_4, AREG, OPRND_SHIFT_0_BIT), + (16_20, AREG, OPRND_SHIFT_0_BIT)), + OPCODE_INFO1 (0xc4007c40, + (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), + CSKYV2_ISA_1E2), + {NULL} + }; diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index c8fda59..c594182 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -33,6 +33,7 @@ #define ARCH_cr16 #define ARCH_cris #define ARCH_crx +#define ARCH_csky #define ARCH_d10v #define ARCH_d30v #define ARCH_dlx @@ -164,6 +165,12 @@ disassembler (enum bfd_architecture a, disassemble = print_insn_crx; break; #endif +#ifdef ARCH_csky + case bfd_arch_csky: + disassemble = csky_get_disassembler (abfd); + break; +#endif + #ifdef ARCH_d10v case bfd_arch_d10v: disassemble = print_insn_d10v; @@ -590,6 +597,13 @@ disassemble_init_for_target (struct disassemble_info * info) info->disassembler_needs_relocs = TRUE; break; #endif +#ifdef ARCH_csky + case bfd_arch_csky: + info->symbol_is_valid = csky_symbol_is_valid; + info->disassembler_needs_relocs = TRUE; + break; +#endif + #ifdef ARCH_ia64 case bfd_arch_ia64: info->skip_zeroes = 16; diff --git a/opcodes/disassemble.h b/opcodes/disassemble.h index 0457344..104ba4a 100644 --- a/opcodes/disassemble.h +++ b/opcodes/disassemble.h @@ -32,6 +32,7 @@ extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); extern int print_insn_big_score (bfd_vma, disassemble_info *); extern int print_insn_cr16 (bfd_vma, disassemble_info *); extern int print_insn_crx (bfd_vma, disassemble_info *); +extern int print_insn_csky (bfd_vma, disassemble_info *); extern int print_insn_d10v (bfd_vma, disassemble_info *); extern int print_insn_d30v (bfd_vma, disassemble_info *); extern int print_insn_dlx (bfd_vma, disassemble_info *); @@ -100,5 +101,6 @@ extern int print_insn_z80 (bfd_vma, disassemble_info *); extern int print_insn_z8001 (bfd_vma, disassemble_info *); extern int print_insn_z8002 (bfd_vma, disassemble_info *); +extern disassembler_ftype csky_get_disassembler (bfd *); extern disassembler_ftype rl78_get_disassembler (bfd *); #endif /* DISASSEMBLE_H */ |