diff options
| -rw-r--r-- | gas/ChangeLog | 11 | ||||
| -rw-r--r-- | gas/NEWS | 2 | ||||
| -rw-r--r-- | gas/config/tc-m68k.c | 187 | ||||
| -rw-r--r-- | gas/doc/c-m68k.texi | 474 |
4 files changed, 644 insertions, 30 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 732d48c..b96e4f5 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,16 @@ Thu Jan 2 13:37:29 1997 Ian Lance Taylor <ian@cygnus.com> + Based on patch from Ronald F. Guilmette <rfg@monkeys.com>: + * config/tc-m68k.c (m68k_index_width_default): New static + variable. + (m68k_ip): Use m68k_index_width_default to set the size of a base + register whose size was not given. + (md_longopts): Add --base-size-default-16 and + --base-size-default-32. + (md_parse_option): Handle new options. + (md_show_usage): Mention new options. + * doc/c-m68k.texi (M68K-Opts): Document new options. + * doc/c-mips.texi: Mention ISA level 4, and the -mips16 option. * configure.in: Recognize mips-*-linux* target. @@ -8,6 +8,8 @@ Motorola ColdFire 5200 support added (configure for m68k and use -m5200). Alpha/VMS support added. +m68k options --base-size-default-16 and --base-size-default-32 added. + Changes in 2.7: The PowerPC assembler now allows the use of symbolic register names (r0, etc.) diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index 9c5c9ab..70a4d70 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -1,5 +1,6 @@ /* tc-m68k.c -- Assemble for the m68k family - Copyright (C) 1987, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc. + Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1997 + Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -95,6 +96,10 @@ static int m68k_quick = 1; be 32 bits. */ static int m68k_rel32 = 1; +/* The default width to use for an index register when using a base + displacement. */ +static enum m68k_size m68k_index_width_default = SIZE_LONG; + /* Its an arbitrary name: This means I don't approve of it */ /* See flames below */ static struct obstack robyn; @@ -1046,6 +1051,96 @@ m68k_ip (instring) } break; + case '<': + switch (opP->mode) + { + case DREG: + case AREG: + case FPREG: + case CONTROL: + case IMMED: + case ADEC: + case REGLST: + losing++; + break; + default: + break; + } + break; + + case '>': + switch (opP->mode) + { + case DREG: + case AREG: + case FPREG: + case CONTROL: + case IMMED: + case AINC: + case REGLST: + losing++; + break; + case ABSL: + break; + default: + if (opP->reg == PC + || opP->reg == ZPC) + losing++; + break; + } + break; + + case 'm': + switch (opP->mode) + { + case DREG: + case AREG: + case AINDR: + case AINC: + case ADEC: + break; + default: + losing++; + } + break; + + case 'n': + switch (opP->mode) + { + case DISP: + break; + default: + losing++; + } + break; + + case 'o': + switch (opP->mode) + { + case BASE: + case ABSL: + case IMMED: + break; + default: + losing++; + } + break; + + case 'p': + switch (opP->mode) + { + case DREG: + case AREG: + case AINDR: + case AINC: + case ADEC: + case DISP: + break; + default: + losing++; + } + break; + case '#': if (opP->mode != IMMED) losing++; @@ -1639,6 +1734,12 @@ m68k_ip (instring) case '?': case '/': case '`': + case '<': + case '>': + case 'm': + case 'n': + case 'o': + case 'p': #ifndef NO_68851 case '|': #endif @@ -1890,8 +1991,9 @@ m68k_ip (instring) { nextword |= (opP->index.reg - DATA) << 12; - if (opP->index.size == SIZE_UNSPEC - || opP->index.size == SIZE_LONG) + if (opP->index.size == SIZE_LONG + || (opP->index.size == SIZE_UNSPEC + && m68k_index_width_default == SIZE_LONG)) nextword |= 0x800; if ((opP->index.scale != 1 @@ -3501,6 +3603,39 @@ md_begin () #endif } +static void +select_control_regs () +{ + /* Note which set of "movec" control registers is available. */ + switch (cpu_of_arch (current_architecture)) + { + case m68000: + control_regs = m68000_control_regs; + break; + case m68010: + control_regs = m68010_control_regs; + break; + case m68020: + case m68030: + control_regs = m68020_control_regs; + break; + case m68040: + control_regs = m68040_control_regs; + break; + case m68060: + control_regs = m68060_control_regs; + break; + case cpu32: + control_regs = cpu32_control_regs; + break; + case mcf5200: + control_regs = mcf5200_control_regs; + break; + default: + abort (); + } +} + void m68k_init_after_args () { @@ -3565,33 +3700,7 @@ m68k_init_after_args () #endif /* Note which set of "movec" control registers is available. */ - switch (cpu_of_arch (current_architecture)) - { - case m68000: - control_regs = m68000_control_regs; - break; - case m68010: - control_regs = m68010_control_regs; - break; - case m68020: - case m68030: - control_regs = m68020_control_regs; - break; - case m68040: - control_regs = m68040_control_regs; - break; - case m68060: - control_regs = m68060_control_regs; - break; - case cpu32: - control_regs = cpu32_control_regs; - break; - case mcf5200: - control_regs = mcf5200_control_regs; - break; - default: - abort (); - } + select_control_regs (); if (cpu_of_arch (current_architecture) < m68020) md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0; @@ -4640,6 +4749,9 @@ mri_chip () current_architecture |= m68851; *input_line_pointer = c; } + + /* Update info about available control registers. */ + select_control_regs (); } /* The MRI CHIP pseudo-op. */ @@ -6250,6 +6362,10 @@ struct option md_longopts[] = { OPTION_REGISTER_PREFIX_OPTIONAL}, #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2) {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR}, +#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3) + {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16}, +#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4) + {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32}, {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof(md_longopts); @@ -6382,6 +6498,14 @@ md_parse_option (c, arg) } break; + case OPTION_BASE_SIZE_DEFAULT_16: + m68k_index_width_default = SIZE_WORD; + break; + + case OPTION_BASE_SIZE_DEFAULT_32: + m68k_index_width_default = SIZE_LONG; + break; + default: return 0; } @@ -6412,6 +6536,9 @@ md_show_usage (stream) --register-prefix-optional\n\ recognize register names without prefix character\n\ --bitwise-or do not treat `|' as a comment character\n"); + fprintf (stream, "\ +--base-size-default-16 base reg without size is 16 bits\n\ +--base-size-default-32 base reg without size is 32 bits (default)\n"); } #ifdef TEST2 diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi new file mode 100644 index 0000000..1137e6a --- /dev/null +++ b/gas/doc/c-m68k.texi @@ -0,0 +1,474 @@ +@c Copyright (C) 1991, 92, 93, 94, 95, 96, 1997 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC +@page +@node M68K-Dependent +@chapter M680x0 Dependent Features +@end ifset +@ifclear GENERIC +@node Machine Dependencies +@chapter M680x0 Dependent Features +@end ifclear + +@cindex M680x0 support +@menu +* M68K-Opts:: M680x0 Options +* M68K-Syntax:: Syntax +* M68K-Moto-Syntax:: Motorola Syntax +* M68K-Float:: Floating Point +* M68K-Directives:: 680x0 Machine Directives +* M68K-opcodes:: Opcodes +@end menu + +@node M68K-Opts +@section M680x0 Options + +@cindex options, M680x0 +@cindex M680x0 options +The Motorola 680x0 version of @code{@value{AS}} has a few machine +dependent options. + +@cindex @samp{-l} option, M680x0 +You can use the @samp{-l} option to shorten the size of references to undefined +symbols. If you do not use the @samp{-l} option, references to undefined +symbols are wide enough for a full @code{long} (32 bits). (Since +@code{@value{AS}} cannot know where these symbols end up, @code{@value{AS}} can +only allocate space for the linker to fill in later. Since @code{@value{AS}} +does not know how far away these symbols are, it allocates as much space as it +can.) If you use this option, the references are only one word wide (16 bits). +This may be useful if you want the object file to be as small as possible, and +you know that the relevant symbols are always less than 17 bits away. + +@cindex @samp{--register-prefix-optional} option, M680x0 +For some configurations, especially those where the compiler normally +does not prepend an underscore to the names of user variables, the +assembler requires a @samp{%} before any use of a register name. This +is intended to let the assembler distinguish between C variables and +functions named @samp{a0} through @samp{a7}, and so on. The @samp{%} is +always accepted, but is not required for certain configurations, notably +@samp{sun3}. The @samp{--register-prefix-optional} option may be used +to permit omitting the @samp{%} even for configurations for which it is +normally required. If this is done, it will generally be impossible to +refer to C variables and functions with the same names as register +names. + +@cindex @samp{--bitwise-or} option, M680x0 +Normally the character @samp{|} is treated as a comment character, which +means that it can not be used in expressions. The @samp{--bitwise-or} +option turns @samp{|} into a normal character. In this mode, you must +either use C style comments, or start comments with a @samp{#} character +at the beginning of a line. + +@cindex @samp{--base-size-default-16} +@cindex @samp{--base-size-default-32} +If you use an addressing mode with a base register without specifying +the size, @code{@value{AS}} will normally use the full 32 bit value. +For example, the addressing mode @samp{%a0@@(%d0)} is equivalent to +@samp{%a0@@(%d0:l)}. You may use the @samp{--base-size-default-16} +option to tell @code{@value{AS}} to default to using the 16 bit value. +In this case, @samp{%a0@@(%d0)} is equivalent to @samp{%a0@@(%d0:w)}. +You may use the @samp{--base-size-default-32} option to restore the +default behaviour. + +@cindex @samp{-m68000} and related options +@cindex architecture options, M680x0 +@cindex M680x0 architecture options +@code{@value{AS}} can assemble code for several different members of the +Motorola 680x0 family. The default depends upon how @code{@value{AS}} +was configured when it was built; normally, the default is to assemble +code for the 68020 microprocessor. The following options may be used to +change the default. These options control which instructions and +addressing modes are permitted. The members of the 680x0 family are +very similar. For detailed information about the differences, see the +Motorola manuals. + +@table @samp +@item -m68000 +@itemx -m68008 +@itemx -m68302 +Assemble for the 68000. @samp{-m68008} and @samp{-m68302} are synonyms +for @samp{-m68000}, since the chips are the same from the point of view +of the assembler. + +@item -m68010 +Assemble for the 68010. + +@item -m68020 +Assemble for the 68020. This is normally the default. + +@item -m68030 +Assemble for the 68030. + +@item -m68040 +Assemble for the 68040. + +@item -m68060 +Assemble for the 68060. + +@item -mcpu32 +@itemx -m68331 +@itemx -m68332 +@itemx -m68333 +@itemx -m68340 +@itemx -m68360 +Assemble for the CPU32 family of chips. + +@item -m5200 +Assemble for the ColdFire family of chips. + +@item -m68881 +@itemx -m68882 +Assemble 68881 floating point instructions. This is the default for the +68020, 68030, and the CPU32. The 68040 and 68060 always support +floating point instructions. + +@item -mno-68881 +Do not assemble 68881 floating point instructions. This is the default +for 68000 and the 68010. The 68040 and 68060 always support floating +point instructions, even if this option is used. + +@item -m68851 +Assemble 68851 MMU instructions. This is the default for the 68020, +68030, and 68060. The 68040 accepts a somewhat different set of MMU +instructions; @samp{-m68851} and @samp{-m68040} should not be used +together. + +@item -mno-68851 +Do not assemble 68851 MMU instructions. This is the default for the +68000, 68010, and the CPU32. The 68040 accepts a somewhat different set +of MMU instructions. +@end table + +@node M68K-Syntax +@section Syntax + +@cindex @sc{mit} +This syntax for the Motorola 680x0 was developed at @sc{mit}. + +@cindex M680x0 syntax +@cindex syntax, M680x0 +@cindex M680x0 size modifiers +@cindex size modifiers, M680x0 +The 680x0 version of @code{@value{AS}} uses instructions names and +syntax compatible with the Sun assembler. Intervening periods are +ignored; for example, @samp{movl} is equivalent to @samp{mov.l}. + +In the following table @var{apc} stands for any of the address registers +(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the +zero-address relative to the program counter (@samp{%zpc}), a suppressed +address register (@samp{%za0} through @samp{%za7}), or it may be omitted +entirely. The use of @var{size} means one of @samp{w} or @samp{l}, and +it may be omitted, along with the leading colon, unless a scale is also +specified. The use of @var{scale} means one of @samp{1}, @samp{2}, +@samp{4}, or @samp{8}, and it may always be omitted along with the +leading colon. + +@cindex M680x0 addressing modes +@cindex addressing modes, M680x0 +The following addressing modes are understood: +@table @dfn +@item Immediate +@samp{#@var{number}} + +@item Data Register +@samp{%d0} through @samp{%d7} + +@item Address Register +@samp{%a0} through @samp{%a7}@* +@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer. @code{%a6} +is also known as @samp{%fp}, the Frame Pointer. + +@item Address Register Indirect +@samp{%a0@@} through @samp{%a7@@} + +@item Address Register Postincrement +@samp{%a0@@+} through @samp{%a7@@+} + +@item Address Register Predecrement +@samp{%a0@@-} through @samp{%a7@@-} + +@item Indirect Plus Offset +@samp{@var{apc}@@(@var{number})} + +@item Index +@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})} + +The @var{number} may be omitted. + +@item Postindex +@samp{@var{apc}@@(@var{number})@@(@var{onumber},@var{register}:@var{size}:@var{scale})} + +The @var{onumber} or the @var{register}, but not both, may be omitted. + +@item Preindex +@samp{@var{apc}@@(@var{number},@var{register}:@var{size}:@var{scale})@@(@var{onumber})} + +The @var{number} may be omitted. Omitting the @var{register} produces +the Postindex addressing mode. + +@item Absolute +@samp{@var{symbol}}, or @samp{@var{digits}}, optionally followed by +@samp{:b}, @samp{:w}, or @samp{:l}. +@end table + +@node M68K-Moto-Syntax +@section Motorola Syntax + +@cindex Motorola syntax for the 680x0 +@cindex alternate syntax for the 680x0 + +The standard Motorola syntax for this chip differs from the syntax +already discussed (@pxref{M68K-Syntax,,Syntax}). @code{@value{AS}} can +accept Motorola syntax for operands, even if @sc{mit} syntax is used for +other operands in the same instruction. The two kinds of syntax are +fully compatible. + +In the following table @var{apc} stands for any of the address registers +(@samp{%a0} through @samp{%a7}), the program counter (@samp{%pc}), the +zero-address relative to the program counter (@samp{%zpc}), or a +suppressed address register (@samp{%za0} through @samp{%za7}). The use +of @var{size} means one of @samp{w} or @samp{l}, and it may always be +omitted along with the leading dot. The use of @var{scale} means one of +@samp{1}, @samp{2}, @samp{4}, or @samp{8}, and it may always be omitted +along with the leading asterisk. + +The following additional addressing modes are understood: + +@table @dfn +@item Address Register Indirect +@samp{(%a0)} through @samp{(%a7)}@* +@samp{%a7} is also known as @samp{%sp}, i.e. the Stack Pointer. @code{%a6} +is also known as @samp{%fp}, the Frame Pointer. + +@item Address Register Postincrement +@samp{(%a0)+} through @samp{(%a7)+} + +@item Address Register Predecrement +@samp{-(%a0)} through @samp{-(%a7)} + +@item Indirect Plus Offset +@samp{@var{number}(@var{%a0})} through @samp{@var{number}(@var{%a7})}, +or @samp{@var{number}(@var{%pc})}. + +The @var{number} may also appear within the parentheses, as in +@samp{(@var{number},@var{%a0})}. When used with the @var{pc}, the +@var{number} may be omitted (with an address register, omitting the +@var{number} produces Address Register Indirect mode). + +@item Index +@samp{@var{number}(@var{apc},@var{register}.@var{size}*@var{scale})} + +The @var{number} may be omitted, or it may appear within the +parentheses. The @var{apc} may be omitted. The @var{register} and the +@var{apc} may appear in either order. If both @var{apc} and +@var{register} are address registers, and the @var{size} and @var{scale} +are omitted, then the first register is taken as the base register, and +the second as the index register. + +@item Postindex +@samp{([@var{number},@var{apc}],@var{register}.@var{size}*@var{scale},@var{onumber})} + +The @var{onumber}, or the @var{register}, or both, may be omitted. +Either the @var{number} or the @var{apc} may be omitted, but not both. + +@item Preindex +@samp{([@var{number},@var{apc},@var{register}.@var{size}*@var{scale}],@var{onumber})} + +The @var{number}, or the @var{apc}, or the @var{register}, or any two of +them, may be omitted. The @var{onumber} may be omitted. The +@var{register} and the @var{apc} may appear in either order. If both +@var{apc} and @var{register} are address registers, and the @var{size} +and @var{scale} are omitted, then the first register is taken as the +base register, and the second as the index register. +@end table + +@node M68K-Float +@section Floating Point + +@cindex floating point, M680x0 +@cindex M680x0 floating point +Packed decimal (P) format floating literals are not supported. +Feel free to add the code! + +The floating point formats generated by directives are these. + +@table @code +@cindex @code{float} directive, M680x0 +@item .float +@code{Single} precision floating point constants. + +@cindex @code{double} directive, M680x0 +@item .double +@code{Double} precision floating point constants. + +@cindex @code{extend} directive M680x0 +@cindex @code{ldouble} directive M680x0 +@item .extend +@itemx .ldouble +@code{Extended} precision (@code{long double}) floating point constants. +@end table + +@node M68K-Directives +@section 680x0 Machine Directives + +@cindex M680x0 directives +@cindex directives, M680x0 +In order to be compatible with the Sun assembler the 680x0 assembler +understands the following directives. + +@table @code +@cindex @code{data1} directive, M680x0 +@item .data1 +This directive is identical to a @code{.data 1} directive. + +@cindex @code{data2} directive, M680x0 +@item .data2 +This directive is identical to a @code{.data 2} directive. + +@cindex @code{even} directive, M680x0 +@item .even +This directive is a special case of the @code{.align} directive; it +aligns the output to an even byte boundary. + +@cindex @code{skip} directive, M680x0 +@item .skip +This directive is identical to a @code{.space} directive. +@end table + +@need 2000 +@node M68K-opcodes +@section Opcodes + +@cindex M680x0 opcodes +@cindex opcodes, M680x0 +@cindex instruction set, M680x0 +@c doc@cygnus.com: I don't see any point in the following +@c paragraph. Bugs are bugs; how does saying this +@c help anyone? +@ignore +Danger: Several bugs have been found in the opcode table (and +fixed). More bugs may exist. Be careful when using obscure +instructions. +@end ignore + +@menu +* M68K-Branch:: Branch Improvement +* M68K-Chars:: Special Characters +@end menu + +@node M68K-Branch +@subsection Branch Improvement + +@cindex pseudo-opcodes, M680x0 +@cindex M680x0 pseudo-opcodes +@cindex branch improvement, M680x0 +@cindex M680x0 branch improvement +Certain pseudo opcodes are permitted for branch instructions. +They expand to the shortest branch instruction that reach the +target. Generally these mnemonics are made by substituting @samp{j} for +@samp{b} at the start of a Motorola mnemonic. + +The following table summarizes the pseudo-operations. A @code{*} flags +cases that are more fully described after the table: + +@smallexample + Displacement + +------------------------------------------------- + | 68020 68000/10 +Pseudo-Op |BYTE WORD LONG LONG non-PC relative + +------------------------------------------------- + jbsr |bsrs bsr bsrl jsr jsr + jra |bras bra bral jmp jmp +* jXX |bXXs bXX bXXl bNXs;jmpl bNXs;jmp +* dbXX |dbXX dbXX dbXX; bra; jmpl +* fjXX |fbXXw fbXXw fbXXl fbNXw;jmp + +XX: condition +NX: negative of condition XX + +@end smallexample +@center @code{*}---see full description below + +@table @code +@item jbsr +@itemx jra +These are the simplest jump pseudo-operations; they always map to one +particular machine instruction, depending on the displacement to the +branch target. + +@item j@var{XX} +Here, @samp{j@var{XX}} stands for an entire family of pseudo-operations, +where @var{XX} is a conditional branch or condition-code test. The full +list of pseudo-ops in this family is: +@smallexample + jhi jls jcc jcs jne jeq jvc + jvs jpl jmi jge jlt jgt jle +@end smallexample + +For the cases of non-PC relative displacements and long displacements on +the 68000 or 68010, @code{@value{AS}} issues a longer code fragment in terms of +@var{NX}, the opposite condition to @var{XX}. For example, for the +non-PC relative case: +@smallexample + j@var{XX} foo +@end smallexample +gives +@smallexample + b@var{NX}s oof + jmp foo + oof: +@end smallexample + +@item db@var{XX} +The full family of pseudo-operations covered here is +@smallexample + dbhi dbls dbcc dbcs dbne dbeq dbvc + dbvs dbpl dbmi dbge dblt dbgt dble + dbf dbra dbt +@end smallexample + +Other than for word and byte displacements, when the source reads +@samp{db@var{XX} foo}, @code{@value{AS}} emits +@smallexample + db@var{XX} oo1 + bra oo2 + oo1:jmpl foo + oo2: +@end smallexample + +@item fj@var{XX} +This family includes +@smallexample + fjne fjeq fjge fjlt fjgt fjle fjf + fjt fjgl fjgle fjnge fjngl fjngle fjngt + fjnle fjnlt fjoge fjogl fjogt fjole fjolt + fjor fjseq fjsf fjsne fjst fjueq fjuge + fjugt fjule fjult fjun +@end smallexample + +For branch targets that are not PC relative, @code{@value{AS}} emits +@smallexample + fb@var{NX} oof + jmp foo + oof: +@end smallexample +when it encounters @samp{fj@var{XX} foo}. + +@end table + +@node M68K-Chars +@subsection Special Characters + +@cindex special characters, M680x0 +@cindex M680x0 immediate character +@cindex immediate character, M680x0 +@cindex M680x0 line comment character +@cindex line comment character, M680x0 +@cindex comments, M680x0 +The immediate character is @samp{#} for Sun compatibility. The +line-comment character is @samp{|} (unless the @samp{--bitwise-or} +option is used). If a @samp{#} appears at the beginning of a line, it +is treated as a comment unless it looks like @samp{# line file}, in +which case it is treated normally. + |