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-rw-r--r--gas/config/tc-i386.c52
-rw-r--r--gas/testsuite/gas/i386/x86-64-inval-avx512f.l6
-rw-r--r--gas/testsuite/gas/i386/x86-64-inval-avx512f.s3
-rw-r--r--opcodes/i386-opc.tbl16
-rw-r--r--opcodes/i386-tbl.h16
5 files changed, 72 insertions, 21 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index a84e999..1e580b9 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -172,7 +172,7 @@ static void optimize_imm (void);
static bool optimize_disp (const insn_template *t);
static const insn_template *match_template (char);
static int check_string (void);
-static int process_suffix (void);
+static int process_suffix (const insn_template *);
static int check_byte_reg (void);
static int check_long_reg (void);
static int check_qword_reg (void);
@@ -6949,7 +6949,7 @@ md_assemble (char *line)
if (use_unaligned_vector_move)
encode_with_unaligned_vector_move ();
- if (!process_suffix ())
+ if (!process_suffix (t))
return;
/* Check if IP-relative addressing requirements can be satisfied. */
@@ -8361,12 +8361,16 @@ check_VecOperands (const insn_template *t)
if (operand_type_check (i.types[op], disp)
&& i.op[op].disps->X_op == O_constant)
{
+ /* Make sure to leave i.types[op].bitfield.disp8 alone upon
+ secondary invocations of match_template(). */
if (fits_in_disp8 (i.op[op].disps->X_add_number))
{
- i.types[op].bitfield.disp8 = 1;
+ if (!i.tm.mnem_off)
+ i.types[op].bitfield.disp8 = 1;
return 0;
}
- i.types[op].bitfield.disp8 = 0;
+ if (!i.tm.mnem_off)
+ i.types[op].bitfield.disp8 = 0;
}
}
@@ -9184,6 +9188,11 @@ match_template (char mnem_suffix)
return NULL;
}
+ /* Don't emit diagnostics or install the template when one was already
+ installed, i.e. when called from process_suffix(). */
+ if (i.tm.mnem_off)
+ return t;
+
if (!quiet_warnings)
{
if (!intel_syntax
@@ -9290,7 +9299,7 @@ check_string (void)
}
static int
-process_suffix (void)
+process_suffix (const insn_template *t)
{
bool is_movx = false;
@@ -9465,6 +9474,39 @@ process_suffix (void)
if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
suffixes |= 1 << 5;
+ /* Operand size may be ambiguous only across multiple templates. Avoid
+ the extra effort though if we already know that multiple suffixes /
+ operand sizes are allowed. Also limit this to non-SIMD operand sizes
+ (i.e. ones expressable via suffixes) for now.
+ There's one special case though that needs excluding: Insns taking
+ Disp<N> operands also match templates permitting BaseIndex. JMP in
+ particular would thus wrongly trigger the check further down. Cover
+ JUMP_DWORD insns here as well, just in case. */
+ if (i.tm.opcode_modifier.jump != JUMP
+ && i.tm.opcode_modifier.jump != JUMP_DWORD)
+ while (!(suffixes & (suffixes - 1)))
+ {
+ /* Sadly check_VecOperands(), running ahead of install_template(),
+ may update i.memshift. Save and restore the value here. */
+ unsigned int memshift = i.memshift;
+
+ current_templates.start = t + 1;
+ t = match_template (0);
+ i.memshift = memshift;
+ if (t == NULL)
+ break;
+ if (!t->opcode_modifier.no_bsuf)
+ suffixes |= 1 << 0;
+ if (!t->opcode_modifier.no_wsuf)
+ suffixes |= 1 << 1;
+ if (!t->opcode_modifier.no_lsuf)
+ suffixes |= 1 << 2;
+ if (!t->opcode_modifier.no_ssuf)
+ suffixes |= 1 << 4;
+ if (flag_code == CODE_64BIT && !t->opcode_modifier.no_qsuf)
+ suffixes |= 1 << 5;
+ }
+
/* For [XYZ]MMWORD operands inspect operand sizes. While generally
also suitable for AT&T syntax mode, it was requested that this be
restricted to just Intel syntax. */
diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx512f.l b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l
index 634683f..8eb8b7e 100644
--- a/gas/testsuite/gas/i386/x86-64-inval-avx512f.l
+++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l
@@ -41,6 +41,8 @@
.*:58: Error: .*
.*:61: Error: .*unsupported broadcast for `vdpbf16ps'
.*:62: Error: .*unsupported broadcast for `vcvtne2ps2bf16'
+.*:64: Error: .* `vcvtusi2sd'
+.*:65: Error: .* `vcvtusi2sd'
GAS LISTING .*
@@ -107,3 +109,7 @@ GAS LISTING .*
[ ]*60[ ]+\.att_syntax prefix
[ ]*61[ ]+vdpbf16ps 8\(%rax\)\{1to8\}, %zmm2, %zmm2
[ ]*62[ ]+vcvtne2ps2bf16 8\(%rax\)\{1to8\}, %zmm2, %zmm2
+[ ]*63[ ]*
+[ ]*64[ ]+vcvtusi2sdq %eax, %xmm0, %xmm0
+[ ]*65[ ]+vcvtusi2sdl %rax, \{rn-sae\}, %xmm0, %xmm0
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx512f.s b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s
index 934e906..731f2ca 100644
--- a/gas/testsuite/gas/i386/x86-64-inval-avx512f.s
+++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s
@@ -60,3 +60,6 @@ _start:
.att_syntax prefix
vdpbf16ps 8(%rax){1to8}, %zmm2, %zmm2
vcvtne2ps2bf16 8(%rax){1to8}, %zmm2, %zmm2
+
+ vcvtusi2sdq %eax, %xmm0, %xmm0
+ vcvtusi2sdl %rax, {rn-sae}, %xmm0, %xmm0
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index faaa92c..b2c5075 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -2372,14 +2372,14 @@ vcvts<sdh>2usi, 0x<sdh:spfx>79, <sdh:cpu>, Modrm|EVexLIG|<sdh:spc1>|Disp8MemShif
vcvtsd2ss, 0xF25A, AVX512F, Modrm|EVexLIG|Masking|Space0F|Src1VVVV|VexW1|Disp8MemShift=3|NoSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
-vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_qSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_qSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtsi2sd, 0xF22A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_qSuf|No_sSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_qSuf|No_sSuf|IntelSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtusi2sd, 0xF27B, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
vcvtsi2ss, 0xF32A, AVX512F, Modrm|EVexLIG|Space0F|Src1VVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 76cdfd9..e9a5d69 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -22785,7 +22785,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtsi2sd, 0x2a, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 0, 0, 7, 0, 2, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -22797,7 +22797,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtsi2sd, 0x2a, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 1, 1, 7, 0, 2, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -22809,7 +22809,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtsi2sd, 0x2a, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 0, 0, 7, 0, 1, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -22821,7 +22821,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtsi2sd, 0x2a, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 1, 1, 7, 0, 1, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -34883,7 +34883,7 @@ static const insn_template i386_optab[] =
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0,
0, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtusi2sd, 0x7b, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 0, 0, 7, 0, 2, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -34895,7 +34895,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtusi2sd, 0x7b, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 1, 1, 7, 0, 2, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -34907,7 +34907,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtusi2sd, 0x7b, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 0, 0, 7, 0, 1, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
@@ -34919,7 +34919,7 @@ static const insn_template i386_optab[] =
{ { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1, 0, 0, 0, 0, 0 } } } },
{ MN_vcvtusi2sd, 0x7b, 3, SPACE_0F, None,
- { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 1, 0, 3, 0, 0, 4, 0, 0, 1, 1, 7, 0, 1, 0, 0, 0,
0, 0 },
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
generated by cgit v1.1 at 2024-11-28 09:36:52 +0000