diff options
| -rw-r--r-- | gas/config/tc-aarch64.c | 1 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 1 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
3 files changed, 5 insertions, 0 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 539bfa2..6a8ebe4 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7666,6 +7666,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto sys_reg_ins; case AARCH64_OPND_SYSREG_TLBI: + case AARCH64_OPND_SYSREG_TLBIP: inst.base.operands[i].sysins_op = parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh); sys_reg_ins: diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index b81475f..768caec 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -566,6 +566,7 @@ enum aarch64_opnd AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */ AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */ AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */ + AARCH64_OPND_SYSREG_TLBIP, /* System register <tlbip_op> operand. */ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */ AARCH64_OPND_BARRIER, /* Barrier operand. */ AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ec14e4b..bb8f343 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4218,6 +4218,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), + D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)), V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), @@ -6351,6 +6352,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an instruction cache maintenance operation specifier") \ Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ "a TBL invalidation operation specifier") \ + Y(SYSTEM, sysins_op, "SYSREG_TLBIP", 0, F(), \ + "a 128-bit TBL invalidation operation specifier") \ Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \ "a Speculation Restriction option name (RCTX)") \ Y(SYSTEM, barrier, "BARRIER", 0, F(), \ |