diff options
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l | 1 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s | 33 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-fmemidx.d | 32 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-fmemidx.s | 32 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 16 |
5 files changed, 58 insertions, 56 deletions
diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l index ef28f04..33cddac 100644 --- a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.l @@ -1,4 +1,5 @@ .*: Assembler messages: +.*: Error: illegal operands `th.flrd a0,a1,a2,0' .*: Error: improper immediate value \(18446744073709551615\) .*: Error: improper immediate value \(4\) .*: Error: improper immediate value \(18446744073709551615\) diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s index e486c6a..8c6ee0c 100644 --- a/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx-fail.s @@ -1,17 +1,18 @@ target: - th.flrd a0, a1, a2, -1 - th.flrd a0, a1, a2, 4 - th.flrw a0, a1, a2, -1 - th.flrw a0, a1, a2, 4 - th.flurd a0, a1, a2, -1 - th.flurd a0, a1, a2, 4 - th.flurw a0, a1, a2, -1 - th.flurw a0, a1, a2, 4 - th.fsrd a0, a1, a2, -1 - th.fsrd a0, a1, a2, 4 - th.fsrw a0, a1, a2, -1 - th.fsrw a0, a1, a2, 4 - th.fsurd a0, a1, a2, -1 - th.fsurd a0, a1, a2, 4 - th.fsurw a0, a1, a2, -1 - th.fsurw a0, a1, a2, 4 + th.flrd a0, a1, a2, 0 + th.flrd fa0, a1, a2, -1 + th.flrd fa0, a1, a2, 4 + th.flrw fa0, a1, a2, -1 + th.flrw fa0, a1, a2, 4 + th.flurd fa0, a1, a2, -1 + th.flurd fa0, a1, a2, 4 + th.flurw fa0, a1, a2, -1 + th.flurw fa0, a1, a2, 4 + th.fsrd fa0, a1, a2, -1 + th.fsrd fa0, a1, a2, 4 + th.fsrw fa0, a1, a2, -1 + th.fsrw fa0, a1, a2, 4 + th.fsurd fa0, a1, a2, -1 + th.fsurd fa0, a1, a2, 4 + th.fsurw fa0, a1, a2, -1 + th.fsurw fa0, a1, a2, 4 diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.d b/gas/testsuite/gas/riscv/x-thead-fmemidx.d index dfa477c..e8d53a3 100644 --- a/gas/testsuite/gas/riscv/x-thead-fmemidx.d +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.d @@ -7,19 +7,19 @@ Disassembly of section .text: 0+000 <target>: -[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+a0,a1,a2,3 -[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,0 -[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+a0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+60c5e50b[ ]+th.flrd[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+66c5e50b[ ]+th.flrd[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5e50b[ ]+th.flrw[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+46c5e50b[ ]+th.flrw[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+70c5e50b[ ]+th.flurd[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+76c5e50b[ ]+th.flurd[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5e50b[ ]+th.flurw[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+56c5e50b[ ]+th.flurw[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+60c5f50b[ ]+th.fsrd[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+66c5f50b[ ]+th.fsrd[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+40c5f50b[ ]+th.fsrw[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+46c5f50b[ ]+th.fsrw[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+70c5f50b[ ]+th.fsurd[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+76c5f50b[ ]+th.fsurd[ ]+fa0,a1,a2,3 +[ ]+[0-9a-f]+:[ ]+50c5f50b[ ]+th.fsurw[ ]+fa0,a1,a2,0 +[ ]+[0-9a-f]+:[ ]+56c5f50b[ ]+th.fsurw[ ]+fa0,a1,a2,3 diff --git a/gas/testsuite/gas/riscv/x-thead-fmemidx.s b/gas/testsuite/gas/riscv/x-thead-fmemidx.s index 0d70bb7..f26bdc3 100644 --- a/gas/testsuite/gas/riscv/x-thead-fmemidx.s +++ b/gas/testsuite/gas/riscv/x-thead-fmemidx.s @@ -1,17 +1,17 @@ target: - th.flrd a0, a1, a2, 0 - th.flrd a0, a1, a2, 3 - th.flrw a0, a1, a2, 0 - th.flrw a0, a1, a2, 3 - th.flurd a0, a1, a2, 0 - th.flurd a0, a1, a2, 3 - th.flurw a0, a1, a2, 0 - th.flurw a0, a1, a2, 3 - th.fsrd a0, a1, a2, 0 - th.fsrd a0, a1, a2, 3 - th.fsrw a0, a1, a2, 0 - th.fsrw a0, a1, a2, 3 - th.fsurd a0, a1, a2, 0 - th.fsurd a0, a1, a2, 3 - th.fsurw a0, a1, a2, 0 - th.fsurw a0, a1, a2, 3 + th.flrd fa0, a1, a2, 0 + th.flrd fa0, a1, a2, 3 + th.flrw fa0, a1, a2, 0 + th.flrw fa0, a1, a2, 3 + th.flurd fa0, a1, a2, 0 + th.flurd fa0, a1, a2, 3 + th.flurw fa0, a1, a2, 0 + th.flurw fa0, a1, a2, 3 + th.fsrd fa0, a1, a2, 0 + th.fsrd fa0, a1, a2, 3 + th.fsrw fa0, a1, a2, 0 + th.fsrw fa0, a1, a2, 3 + th.fsurd fa0, a1, a2, 0 + th.fsurd fa0, a1, a2, 3 + th.fsurw fa0, a1, a2, 0 + th.fsurw fa0, a1, a2, 3 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 4029c18..599486f 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1922,14 +1922,14 @@ const struct riscv_opcode riscv_opcodes[] = {"th.mvnez", 0, INSN_CLASS_XTHEADCONDMOV, "d,s,t", MATCH_TH_MVNEZ, MASK_TH_MVNEZ, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadFMemIdx instructions. */ -{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, -{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, -{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, -{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, -{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, -{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, -{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, -{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "d,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, +{"th.flrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRD, MASK_TH_FLRD, match_opcode, 0}, +{"th.flrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLRW, MASK_TH_FLRW, match_opcode, 0}, +{"th.flurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURD, MASK_TH_FLURD, match_opcode, 0}, +{"th.flurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FLURW, MASK_TH_FLURW, match_opcode, 0}, +{"th.fsrd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRD, MASK_TH_FSRD, match_opcode, 0}, +{"th.fsrw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSRW, MASK_TH_FSRW, match_opcode, 0}, +{"th.fsurd", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURD, MASK_TH_FSURD, match_opcode, 0}, +{"th.fsurw", 0, INSN_CLASS_XTHEADFMEMIDX, "D,s,t,Xu2@25", MATCH_TH_FSURW, MASK_TH_FSURW, match_opcode, 0}, /* Vendor-specific (T-Head) XTheadMemIdx instructions. */ {"th.ldia", 64, INSN_CLASS_XTHEADMEMIDX, "d,(s),Xs5@20,Xu2@25", MATCH_TH_LDIA, MASK_TH_LDIA, match_th_load_inc, 0}, |