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-rw-r--r--binutils/ChangeLog7
-rw-r--r--binutils/testsuite/binutils-all/mips/mips.exp1
-rw-r--r--binutils/testsuite/binutils-all/mips/mips16-undecoded.d168
-rw-r--r--binutils/testsuite/binutils-all/mips/mips16-undecoded.s198
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/mips-dis.c6
6 files changed, 383 insertions, 2 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index b4f5286..89d8767 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,10 @@
+2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
+
+ * testsuite/binutils-all/mips/mips16-undecoded.d: New test.
+ * testsuite/binutils-all/mips/mips16-undecoded.s: New test
+ source.
+ * testsuite/binutils-all/mips/mips.exp: Run the new test.
+
2016-04-04 Nick Clifton <nickc@redhat.com>
PR 19872
diff --git a/binutils/testsuite/binutils-all/mips/mips.exp b/binutils/testsuite/binutils-all/mips/mips.exp
index 4fbb030..5c93959 100644
--- a/binutils/testsuite/binutils-all/mips/mips.exp
+++ b/binutils/testsuite/binutils-all/mips/mips.exp
@@ -22,4 +22,5 @@ if ![istarget mips*-*-*] {
if [is_elf_format] {
run_dump_test "mixed-mips16"
run_dump_test "mixed-micromips"
+ run_dump_test "mips16-undecoded"
}
diff --git a/binutils/testsuite/binutils-all/mips/mips16-undecoded.d b/binutils/testsuite/binutils-all/mips/mips16-undecoded.d
new file mode 100644
index 0000000..42a5cdf
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-undecoded.d
@@ -0,0 +1,168 @@
+#PROG: objcopy
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS16 undecoded extended instruction field disassembly
+#as: -32
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f008 0211 addiu v0,sp,16401
+[0-9a-f]+ <[^>]*> f008 0211 addiu v0,sp,16401
+[0-9a-f]+ <[^>]*> f008 0231 addiu v0,sp,16401
+[0-9a-f]+ <[^>]*> f008 0251 addiu v0,sp,16401
+[0-9a-f]+ <[^>]*> f008 0291 addiu v0,sp,16401
+[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004024 <foo\+0x4024>
+[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004028 <foo\+0x4028>
+[0-9a-f]+ <[^>]*> f008 0a31 la v0,0000402c <foo\+0x402c>
+[0-9a-f]+ <[^>]*> f008 0a51 la v0,00004030 <foo\+0x4030>
+[0-9a-f]+ <[^>]*> f008 0a91 la v0,00004034 <foo\+0x4034>
+[0-9a-f]+ <[^>]*> f008 1011 b 0000804e <foo\+0x804e>
+[0-9a-f]+ <[^>]*> f008 1011 b 00008052 <foo\+0x8052>
+[0-9a-f]+ <[^>]*> f008 1031 b 00008056 <foo\+0x8056>
+[0-9a-f]+ <[^>]*> f008 1051 b 0000805a <foo\+0x805a>
+[0-9a-f]+ <[^>]*> f008 1091 b 0000805e <foo\+0x805e>
+[0-9a-f]+ <[^>]*> f008 1111 b 00008062 <foo\+0x8062>
+[0-9a-f]+ <[^>]*> f008 1211 b 00008066 <foo\+0x8066>
+[0-9a-f]+ <[^>]*> f008 1411 b 0000806a <foo\+0x806a>
+[0-9a-f]+ <[^>]*> f008 2211 beqz v0,0000806e <foo\+0x806e>
+[0-9a-f]+ <[^>]*> f008 2211 beqz v0,00008072 <foo\+0x8072>
+[0-9a-f]+ <[^>]*> f008 2231 beqz v0,00008076 <foo\+0x8076>
+[0-9a-f]+ <[^>]*> f008 2251 beqz v0,0000807a <foo\+0x807a>
+[0-9a-f]+ <[^>]*> f008 2291 beqz v0,0000807e <foo\+0x807e>
+[0-9a-f]+ <[^>]*> f008 2a11 bnez v0,00008082 <foo\+0x8082>
+[0-9a-f]+ <[^>]*> f008 2a11 bnez v0,00008086 <foo\+0x8086>
+[0-9a-f]+ <[^>]*> f008 2a31 bnez v0,0000808a <foo\+0x808a>
+[0-9a-f]+ <[^>]*> f008 2a51 bnez v0,0000808e <foo\+0x808e>
+[0-9a-f]+ <[^>]*> f008 2a91 bnez v0,00008092 <foo\+0x8092>
+[0-9a-f]+ <[^>]*> f008 4a11 addiu v0,16401
+[0-9a-f]+ <[^>]*> f008 4a11 addiu v0,16401
+[0-9a-f]+ <[^>]*> f008 4a31 addiu v0,16401
+[0-9a-f]+ <[^>]*> f008 4a51 addiu v0,16401
+[0-9a-f]+ <[^>]*> f008 4a91 addiu v0,16401
+[0-9a-f]+ <[^>]*> f008 5211 slti v0,16401
+[0-9a-f]+ <[^>]*> f008 5211 slti v0,16401
+[0-9a-f]+ <[^>]*> f008 5231 slti v0,16401
+[0-9a-f]+ <[^>]*> f008 5251 slti v0,16401
+[0-9a-f]+ <[^>]*> f008 5291 slti v0,16401
+[0-9a-f]+ <[^>]*> f008 5a11 sltiu v0,16401
+[0-9a-f]+ <[^>]*> f008 5a11 sltiu v0,16401
+[0-9a-f]+ <[^>]*> f008 5a31 sltiu v0,16401
+[0-9a-f]+ <[^>]*> f008 5a51 sltiu v0,16401
+[0-9a-f]+ <[^>]*> f008 5a91 sltiu v0,16401
+[0-9a-f]+ <[^>]*> f008 6a11 li v0,16401
+[0-9a-f]+ <[^>]*> f008 6a11 li v0,16401
+[0-9a-f]+ <[^>]*> f008 6a31 li v0,16401
+[0-9a-f]+ <[^>]*> f008 6a51 li v0,16401
+[0-9a-f]+ <[^>]*> f008 6a91 li v0,16401
+[0-9a-f]+ <[^>]*> f008 7211 cmpi v0,16401
+[0-9a-f]+ <[^>]*> f008 7211 cmpi v0,16401
+[0-9a-f]+ <[^>]*> f008 7231 cmpi v0,16401
+[0-9a-f]+ <[^>]*> f008 7251 cmpi v0,16401
+[0-9a-f]+ <[^>]*> f008 7291 cmpi v0,16401
+[0-9a-f]+ <[^>]*> f008 9211 lw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 9211 lw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 9231 lw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 9251 lw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 9291 lw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040f8 <foo\+0x40f8>
+[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040fc <foo\+0x40fc>
+[0-9a-f]+ <[^>]*> f008 b231 lw v0,00004100 <foo\+0x4100>
+[0-9a-f]+ <[^>]*> f008 b251 lw v0,00004104 <foo\+0x4104>
+[0-9a-f]+ <[^>]*> f008 b291 lw v0,00004108 <foo\+0x4108>
+[0-9a-f]+ <[^>]*> f008 d211 sw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 d211 sw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 d231 sw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 d251 sw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 d291 sw v0,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 6011 bteqz 00008136 <foo\+0x8136>
+[0-9a-f]+ <[^>]*> f008 6011 bteqz 0000813a <foo\+0x813a>
+[0-9a-f]+ <[^>]*> f008 6031 bteqz 0000813e <foo\+0x813e>
+[0-9a-f]+ <[^>]*> f008 6051 bteqz 00008142 <foo\+0x8142>
+[0-9a-f]+ <[^>]*> f008 6091 bteqz 00008146 <foo\+0x8146>
+[0-9a-f]+ <[^>]*> f008 6111 btnez 0000814a <foo\+0x814a>
+[0-9a-f]+ <[^>]*> f008 6111 btnez 0000814e <foo\+0x814e>
+[0-9a-f]+ <[^>]*> f008 6131 btnez 00008152 <foo\+0x8152>
+[0-9a-f]+ <[^>]*> f008 6151 btnez 00008156 <foo\+0x8156>
+[0-9a-f]+ <[^>]*> f008 6191 btnez 0000815a <foo\+0x815a>
+[0-9a-f]+ <[^>]*> f008 6211 sw ra,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 6211 sw ra,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 6231 sw ra,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 6251 sw ra,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 6291 sw ra,16401\(sp\)
+[0-9a-f]+ <[^>]*> f008 6311 addiu sp,16401
+[0-9a-f]+ <[^>]*> f008 6311 addiu sp,16401
+[0-9a-f]+ <[^>]*> f008 6331 addiu sp,16401
+[0-9a-f]+ <[^>]*> f008 6351 addiu sp,16401
+[0-9a-f]+ <[^>]*> f008 6391 addiu sp,16401
+[0-9a-f]+ <[^>]*> f500 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3264 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3268 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3270 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f501 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f502 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f504 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f508 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f510 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f520 3260 sll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3265 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3269 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3271 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f501 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f502 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f504 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f508 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f510 3261 dsll v0,v1,20
+[0-9a-f]+ <[^>]*> f520 3261 dsll v0,v1,52
+[0-9a-f]+ <[^>]*> f500 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3266 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f500 326a srl v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3272 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f501 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f502 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f504 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f508 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f510 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f520 3262 srl v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3267 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f500 326b sra v0,v1,20
+[0-9a-f]+ <[^>]*> f500 3273 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f501 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f502 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f504 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f508 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f510 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f520 3263 sra v0,v1,20
+[0-9a-f]+ <[^>]*> f500 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f500 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f500 e948 dsrl v0,20
+[0-9a-f]+ <[^>]*> f500 ea48 dsrl v0,20
+[0-9a-f]+ <[^>]*> f500 ec48 dsrl v0,20
+[0-9a-f]+ <[^>]*> f501 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f502 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f504 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f508 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f510 e848 dsrl v0,20
+[0-9a-f]+ <[^>]*> f520 e848 dsrl v0,52
+[0-9a-f]+ <[^>]*> f500 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f500 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f500 e953 dsra v0,20
+[0-9a-f]+ <[^>]*> f500 ea53 dsra v0,20
+[0-9a-f]+ <[^>]*> f500 ec53 dsra v0,20
+[0-9a-f]+ <[^>]*> f501 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f502 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f504 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f508 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f510 e853 dsra v0,20
+[0-9a-f]+ <[^>]*> f520 e853 dsra v0,52
+[0-9a-f]+ <[^>]*> f008 fb11 daddiu sp,16401
+[0-9a-f]+ <[^>]*> f008 fb11 daddiu sp,16401
+[0-9a-f]+ <[^>]*> f008 fb31 daddiu sp,16401
+[0-9a-f]+ <[^>]*> f008 fb51 daddiu sp,16401
+[0-9a-f]+ <[^>]*> f008 fb91 daddiu sp,16401
+ \.\.\.
diff --git a/binutils/testsuite/binutils-all/mips/mips16-undecoded.s b/binutils/testsuite/binutils-all/mips/mips16-undecoded.s
new file mode 100644
index 0000000..2736ae4
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-undecoded.s
@@ -0,0 +1,198 @@
+ .text
+ .set mips3
+ .set mips16
+ .globl foo
+ .ent foo
+foo:
+ # Individual major opcodes.
+ addiu $2, $sp, 0x4011
+ .half 0xf008, 0x0211
+ .half 0xf008, 0x0231
+ .half 0xf008, 0x0251
+ .half 0xf008, 0x0291
+
+ addiu $2, $pc, 0x4011
+ .half 0xf008, 0x0a11
+ .half 0xf008, 0x0a31
+ .half 0xf008, 0x0a51
+ .half 0xf008, 0x0a91
+
+ b . + 0x8026
+ .half 0xf008, 0x1011
+ .half 0xf008, 0x1031
+ .half 0xf008, 0x1051
+ .half 0xf008, 0x1091
+ .half 0xf008, 0x1111
+ .half 0xf008, 0x1211
+ .half 0xf008, 0x1411
+
+ beqz $2, . + 0x8026
+ .half 0xf008, 0x2211
+ .half 0xf008, 0x2231
+ .half 0xf008, 0x2251
+ .half 0xf008, 0x2291
+
+ bnez $2, . + 0x8026
+ .half 0xf008, 0x2a11
+ .half 0xf008, 0x2a31
+ .half 0xf008, 0x2a51
+ .half 0xf008, 0x2a91
+
+ addiu $2, 0x4011
+ .half 0xf008, 0x4a11
+ .half 0xf008, 0x4a31
+ .half 0xf008, 0x4a51
+ .half 0xf008, 0x4a91
+
+ slti $2, 0x4011
+ .half 0xf008, 0x5211
+ .half 0xf008, 0x5231
+ .half 0xf008, 0x5251
+ .half 0xf008, 0x5291
+
+ sltiu $2, 0x4011
+ .half 0xf008, 0x5a11
+ .half 0xf008, 0x5a31
+ .half 0xf008, 0x5a51
+ .half 0xf008, 0x5a91
+
+ li $2, 0x4011
+ .half 0xf008, 0x6a11
+ .half 0xf008, 0x6a31
+ .half 0xf008, 0x6a51
+ .half 0xf008, 0x6a91
+
+ cmpi $2, 0x4011
+ .half 0xf008, 0x7211
+ .half 0xf008, 0x7231
+ .half 0xf008, 0x7251
+ .half 0xf008, 0x7291
+
+ lw $2, 0x4011($sp)
+ .half 0xf008, 0x9211
+ .half 0xf008, 0x9231
+ .half 0xf008, 0x9251
+ .half 0xf008, 0x9291
+
+ lw $2, 0x4011($pc)
+ .half 0xf008, 0xb211
+ .half 0xf008, 0xb231
+ .half 0xf008, 0xb251
+ .half 0xf008, 0xb291
+
+ sw $2, 0x4011($sp)
+ .half 0xf008, 0xd211
+ .half 0xf008, 0xd231
+ .half 0xf008, 0xd251
+ .half 0xf008, 0xd291
+
+ # I8 major opcode.
+ bteqz . + 0x8026
+ .half 0xf008, 0x6011
+ .half 0xf008, 0x6031
+ .half 0xf008, 0x6051
+ .half 0xf008, 0x6091
+
+ btnez . + 0x8026
+ .half 0xf008, 0x6111
+ .half 0xf008, 0x6131
+ .half 0xf008, 0x6151
+ .half 0xf008, 0x6191
+
+ sw $ra, 0x4011($sp)
+ .half 0xf008, 0x6211
+ .half 0xf008, 0x6231
+ .half 0xf008, 0x6251
+ .half 0xf008, 0x6291
+
+ addiu $sp, 0x4011
+ .half 0xf008, 0x6311
+ .half 0xf008, 0x6331
+ .half 0xf008, 0x6351
+ .half 0xf008, 0x6391
+
+ # SHIFT major opcode
+ sll $2, $3, 0x14
+ .half 0xf500, 0x3260
+ .half 0xf500, 0x3264
+ .half 0xf500, 0x3268
+ .half 0xf500, 0x3270
+ .half 0xf501, 0x3260
+ .half 0xf502, 0x3260
+ .half 0xf504, 0x3260
+ .half 0xf508, 0x3260
+ .half 0xf510, 0x3260
+ .half 0xf520, 0x3260
+
+ dsll $2, $3, 0x14
+ .half 0xf500, 0x3261
+ .half 0xf500, 0x3265
+ .half 0xf500, 0x3269
+ .half 0xf500, 0x3271
+ .half 0xf501, 0x3261
+ .half 0xf502, 0x3261
+ .half 0xf504, 0x3261
+ .half 0xf508, 0x3261
+ .half 0xf510, 0x3261
+ .half 0xf520, 0x3261
+
+ srl $2, $3, 0x14
+ .half 0xf500, 0x3262
+ .half 0xf500, 0x3266
+ .half 0xf500, 0x326a
+ .half 0xf500, 0x3272
+ .half 0xf501, 0x3262
+ .half 0xf502, 0x3262
+ .half 0xf504, 0x3262
+ .half 0xf508, 0x3262
+ .half 0xf510, 0x3262
+ .half 0xf520, 0x3262
+
+ sra $2, $3, 0x14
+ .half 0xf500, 0x3263
+ .half 0xf500, 0x3267
+ .half 0xf500, 0x326b
+ .half 0xf500, 0x3273
+ .half 0xf501, 0x3263
+ .half 0xf502, 0x3263
+ .half 0xf504, 0x3263
+ .half 0xf508, 0x3263
+ .half 0xf510, 0x3263
+ .half 0xf520, 0x3263
+
+ # RR major opcode
+ dsrl $2, 0x14
+ .half 0xf500, 0xe848
+ .half 0xf500, 0xe948
+ .half 0xf500, 0xea48
+ .half 0xf500, 0xec48
+ .half 0xf501, 0xe848
+ .half 0xf502, 0xe848
+ .half 0xf504, 0xe848
+ .half 0xf508, 0xe848
+ .half 0xf510, 0xe848
+ .half 0xf520, 0xe848
+
+ dsra $2, 0x14
+ .half 0xf500, 0xe853
+ .half 0xf500, 0xe953
+ .half 0xf500, 0xea53
+ .half 0xf500, 0xec53
+ .half 0xf501, 0xe853
+ .half 0xf502, 0xe853
+ .half 0xf504, 0xe853
+ .half 0xf508, 0xe853
+ .half 0xf510, 0xe853
+ .half 0xf520, 0xe853
+
+ # I64 major opcode.
+ daddiu $sp, 0x4011
+ .half 0xf008, 0xfb11
+ .half 0xf008, 0xfb31
+ .half 0xf008, 0xfb51
+ .half 0xf008, 0xfb91
+ .end foo
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 4, 0
+ .space 16
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a91544e..4d23c24 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Mask unused extended
+ instruction bits out.
+
2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
* arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index e152876..7822295 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1894,11 +1894,13 @@ print_mips16_insn_arg (struct disassemble_info *info,
{
operand = ext_operand;
if (operand->size == 16)
- uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
+ uval = (((extend & 0x1f) << 11) | (extend & 0x7e0)
+ | (uval & 0x1f));
else if (operand->size == 15)
uval |= ((extend & 0xf) << 11) | (extend & 0x7f0);
else
- uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
+ uval = ((((extend >> 6) & 0x1f) | (extend & 0x20))
+ & ((1U << operand->size) - 1));
}
}
}
generated by cgit v1.1 at 2024-08-09 15:17:45 +0000