diff options
| -rw-r--r-- | sim/common/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/common/sim-core.c | 3 |
2 files changed, 6 insertions, 1 deletions
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index 6ffee16..8039a78 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,5 +1,9 @@ 2021-01-11 Mike Frysinger <vapier@gentoo.org> + * sim-core.c (sim_memory_map): Change %#x to PRIxTW. + +2021-01-11 Mike Frysinger <vapier@gentoo.org> + * acinclude.m4 (SIM_AC_COMMON): Delete checks for stdlib.h, string.h, strings.h, time.h, and errno.h. * callback.c, cgen-scache.c, dv-glue.c, dv-pal.c, dv-sockser.c, diff --git a/sim/common/sim-core.c b/sim/common/sim-core.c index ade345e..9b1e168 100644 --- a/sim/common/sim-core.c +++ b/sim/common/sim-core.c @@ -480,7 +480,8 @@ sim_memory_map (SIM_DESC sd) if (mapping->level != 0) continue; - entry = xasprintf ("<memory type='ram' start='%#x' length='%#x'/>\n", + entry = xasprintf ("<memory type='ram' start='%#" PRIxTW "' " + "length='%#" PRIxTW "'/>\n", mapping->base, mapping->nr_bytes); /* The sim memory map is organized by access, not by addresses. So a RWX memory map will have three independent mappings. |