diff options
25 files changed, 687 insertions, 235 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 078d925..ed7009f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,38 @@ +2008-01-22 H.J. Lu <hongjiu.lu@intel.com> + + * config/tc-i386.c (XXX_PREFIX): Moved from tc-i386.h. + (XXX_MNEM_SUFFIX): Likewise. + (END_OF_INSN): Likewise. + (templates): Likewise. + (modrm_byte): Likewise. + (rex_byte): Likewise. + (DREX_XXX): Likewise. + (drex_byte): Likewise. + (sib_byte): Likewise. + (processor_type): Likewise. + (arch_entry): Likewise. + (cpu_sub_arch_name): Remove const. + (cpu_arch): Add .vmx and .smx. + (set_cpu_arch): Append cpu_sub_arch_name. + (md_parse_option): Support -march=CPU[,+EXTENSION...]. + (md_show_usage): Updated. + + * config/tc-i386.h (XXX_PREFIX): Moved to tc-i386.c. + (XXX_MNEM_SUFFIX): Likewise. + (END_OF_INSN): Likewise. + (templates): Likewise. + (modrm_byte): Likewise. + (rex_byte): Likewise. + (DREX_XXX): Likewise. + (drex_byte): Likewise. + (sib_byte): Likewise. + (processor_type): Likewise. + (arch_entry): Likewise. + + * doc/as.texinfo: Update i386 -march option. + + * doc/c-i386.texi: Update -march= for ISA. + 2008-01-18 Bob Wilson <bob.wilson@acm.org> * config/tc-xtensa.c (xtensa_leb128): New function. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 7d37b9c..28d37a8 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -55,6 +55,128 @@ #endif #endif +/* Prefixes will be emitted in the order defined below. + WAIT_PREFIX must be the first prefix since FWAIT is really is an + instruction, and so must come before any prefixes. + The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, + LOCKREP_PREFIX. */ +#define WAIT_PREFIX 0 +#define SEG_PREFIX 1 +#define ADDR_PREFIX 2 +#define DATA_PREFIX 3 +#define LOCKREP_PREFIX 4 +#define REX_PREFIX 5 /* must come last. */ +#define MAX_PREFIXES 6 /* max prefixes per opcode */ + +/* we define the syntax here (modulo base,index,scale syntax) */ +#define REGISTER_PREFIX '%' +#define IMMEDIATE_PREFIX '$' +#define ABSOLUTE_PREFIX '*' + +/* these are the instruction mnemonic suffixes in AT&T syntax or + memory operand size in Intel syntax. */ +#define WORD_MNEM_SUFFIX 'w' +#define BYTE_MNEM_SUFFIX 'b' +#define SHORT_MNEM_SUFFIX 's' +#define LONG_MNEM_SUFFIX 'l' +#define QWORD_MNEM_SUFFIX 'q' +#define XMMWORD_MNEM_SUFFIX 'x' +/* Intel Syntax. Use a non-ascii letter since since it never appears + in instructions. */ +#define LONG_DOUBLE_MNEM_SUFFIX '\1' + +#define END_OF_INSN '\0' + +/* + 'templates' is for grouping together 'template' structures for opcodes + of the same name. This is only used for storing the insns in the grand + ole hash table of insns. + The templates themselves start at START and range up to (but not including) + END. + */ +typedef struct +{ + const template *start; + const template *end; +} +templates; + +/* 386 operand encoding bytes: see 386 book for details of this. */ +typedef struct +{ + unsigned int regmem; /* codes register or memory operand */ + unsigned int reg; /* codes register operand (or extended opcode) */ + unsigned int mode; /* how to interpret regmem & reg */ +} +modrm_byte; + +/* x86-64 extension prefix. */ +typedef int rex_byte; + +/* The SSE5 instructions have a two bit instruction modifier (OC) that + is stored in two separate bytes in the instruction. Pick apart OC + into the 2 separate bits for instruction. */ +#define DREX_OC0(x) (((x) & 1) != 0) +#define DREX_OC1(x) (((x) & 2) != 0) + +#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ +#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ + +/* OC mappings */ +#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ +#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ +#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ +#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ + +#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ +#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ + +/* Information needed to create the DREX byte in SSE5 instructions. */ +typedef struct +{ + unsigned int reg; /* register */ + unsigned int rex; /* REX flags */ + unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ + unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ +} drex_byte; + +/* 386 opcode byte to code indirect addressing. */ +typedef struct +{ + unsigned base; + unsigned index; + unsigned scale; +} +sib_byte; + +enum processor_type +{ + PROCESSOR_UNKNOWN, + PROCESSOR_I386, + PROCESSOR_I486, + PROCESSOR_PENTIUM, + PROCESSOR_PENTIUMPRO, + PROCESSOR_PENTIUM4, + PROCESSOR_NOCONA, + PROCESSOR_CORE, + PROCESSOR_CORE2, + PROCESSOR_K6, + PROCESSOR_ATHLON, + PROCESSOR_K8, + PROCESSOR_GENERIC32, + PROCESSOR_GENERIC64, + PROCESSOR_AMDFAM10 +}; + +/* x86 arch names, types and features */ +typedef struct +{ + const char *name; /* arch name */ + enum processor_type type; /* arch type */ + i386_cpu_flags flags; /* cpu feature flags */ +} +arch_entry; + static void set_code_flag (int); static void set_16bit_gcc_code_flag (int); static void set_intel_syntax (int); @@ -313,7 +435,7 @@ static int quiet_warnings = 0; /* CPU name. */ static const char *cpu_arch_name = NULL; -static const char *cpu_sub_arch_name = NULL; +static char *cpu_sub_arch_name = NULL; /* CPU feature flags. */ static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; @@ -427,92 +549,96 @@ const relax_typeS md_relax_table[] = static const arch_entry cpu_arch[] = { - {"generic32", PROCESSOR_GENERIC32, - CPU_GENERIC32_FLAGS }, - {"generic64", PROCESSOR_GENERIC64, - CPU_GENERIC64_FLAGS }, - {"i8086", PROCESSOR_UNKNOWN, - CPU_NONE_FLAGS }, - {"i186", PROCESSOR_UNKNOWN, - CPU_I186_FLAGS }, - {"i286", PROCESSOR_UNKNOWN, - CPU_I286_FLAGS }, - {"i386", PROCESSOR_I386, - CPU_I386_FLAGS }, - {"i486", PROCESSOR_I486, - CPU_I486_FLAGS }, - {"i586", PROCESSOR_PENTIUM, - CPU_I586_FLAGS }, - {"i686", PROCESSOR_PENTIUMPRO, - CPU_I686_FLAGS }, - {"pentium", PROCESSOR_PENTIUM, - CPU_I586_FLAGS }, - {"pentiumpro",PROCESSOR_PENTIUMPRO, - CPU_I686_FLAGS }, - {"pentiumii", PROCESSOR_PENTIUMPRO, - CPU_P2_FLAGS }, - {"pentiumiii",PROCESSOR_PENTIUMPRO, - CPU_P3_FLAGS }, - {"pentium4", PROCESSOR_PENTIUM4, - CPU_P4_FLAGS }, - {"prescott", PROCESSOR_NOCONA, - CPU_CORE_FLAGS }, - {"nocona", PROCESSOR_NOCONA, - CPU_NOCONA_FLAGS }, - {"yonah", PROCESSOR_CORE, - CPU_CORE_FLAGS }, - {"core", PROCESSOR_CORE, - CPU_CORE_FLAGS }, - {"merom", PROCESSOR_CORE2, - CPU_CORE2_FLAGS }, - {"core2", PROCESSOR_CORE2, - CPU_CORE2_FLAGS }, - {"k6", PROCESSOR_K6, - CPU_K6_FLAGS }, - {"k6_2", PROCESSOR_K6, - CPU_K6_2_FLAGS }, - {"athlon", PROCESSOR_ATHLON, - CPU_ATHLON_FLAGS }, - {"sledgehammer", PROCESSOR_K8, - CPU_K8_FLAGS }, - {"opteron", PROCESSOR_K8, - CPU_K8_FLAGS }, - {"k8", PROCESSOR_K8, - CPU_K8_FLAGS }, - {"amdfam10", PROCESSOR_AMDFAM10, - CPU_AMDFAM10_FLAGS }, - {".mmx", PROCESSOR_UNKNOWN, - CPU_MMX_FLAGS }, - {".sse", PROCESSOR_UNKNOWN, - CPU_SSE_FLAGS }, - {".sse2", PROCESSOR_UNKNOWN, - CPU_SSE2_FLAGS }, - {".sse3", PROCESSOR_UNKNOWN, - CPU_SSE3_FLAGS }, - {".ssse3", PROCESSOR_UNKNOWN, - CPU_SSSE3_FLAGS }, - {".sse4.1", PROCESSOR_UNKNOWN, - CPU_SSE4_1_FLAGS }, - {".sse4.2", PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS }, - {".sse4", PROCESSOR_UNKNOWN, - CPU_SSE4_2_FLAGS }, - {".3dnow", PROCESSOR_UNKNOWN, - CPU_3DNOW_FLAGS }, - {".3dnowa", PROCESSOR_UNKNOWN, - CPU_3DNOWA_FLAGS }, - {".padlock", PROCESSOR_UNKNOWN, - CPU_PADLOCK_FLAGS }, - {".pacifica", PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS }, - {".svme", PROCESSOR_UNKNOWN, - CPU_SVME_FLAGS }, - {".sse4a", PROCESSOR_UNKNOWN, - CPU_SSE4A_FLAGS }, - {".abm", PROCESSOR_UNKNOWN, - CPU_ABM_FLAGS }, - {".sse5", PROCESSOR_UNKNOWN, - CPU_SSE5_FLAGS }, + { "generic32", PROCESSOR_GENERIC32, + CPU_GENERIC32_FLAGS }, + { "generic64", PROCESSOR_GENERIC64, + CPU_GENERIC64_FLAGS }, + { "i8086", PROCESSOR_UNKNOWN, + CPU_NONE_FLAGS }, + { "i186", PROCESSOR_UNKNOWN, + CPU_I186_FLAGS }, + { "i286", PROCESSOR_UNKNOWN, + CPU_I286_FLAGS }, + { "i386", PROCESSOR_I386, + CPU_I386_FLAGS }, + { "i486", PROCESSOR_I486, + CPU_I486_FLAGS }, + { "i586", PROCESSOR_PENTIUM, + CPU_I586_FLAGS }, + { "i686", PROCESSOR_PENTIUMPRO, + CPU_I686_FLAGS }, + { "pentium", PROCESSOR_PENTIUM, + CPU_I586_FLAGS }, + { "pentiumpro", PROCESSOR_PENTIUMPRO, + CPU_I686_FLAGS }, + { "pentiumii", PROCESSOR_PENTIUMPRO, + CPU_P2_FLAGS }, + { "pentiumiii",PROCESSOR_PENTIUMPRO, + CPU_P3_FLAGS }, + { "pentium4", PROCESSOR_PENTIUM4, + CPU_P4_FLAGS }, + { "prescott", PROCESSOR_NOCONA, + CPU_CORE_FLAGS }, + { "nocona", PROCESSOR_NOCONA, + CPU_NOCONA_FLAGS }, + { "yonah", PROCESSOR_CORE, + CPU_CORE_FLAGS }, + { "core", PROCESSOR_CORE, + CPU_CORE_FLAGS }, + { "merom", PROCESSOR_CORE2, + CPU_CORE2_FLAGS }, + { "core2", PROCESSOR_CORE2, + CPU_CORE2_FLAGS }, + { "k6", PROCESSOR_K6, + CPU_K6_FLAGS }, + { "k6_2", PROCESSOR_K6, + CPU_K6_2_FLAGS }, + { "athlon", PROCESSOR_ATHLON, + CPU_ATHLON_FLAGS }, + { "sledgehammer", PROCESSOR_K8, + CPU_K8_FLAGS }, + { "opteron", PROCESSOR_K8, + CPU_K8_FLAGS }, + { "k8", PROCESSOR_K8, + CPU_K8_FLAGS }, + { "amdfam10", PROCESSOR_AMDFAM10, + CPU_AMDFAM10_FLAGS }, + { ".mmx", PROCESSOR_UNKNOWN, + CPU_MMX_FLAGS }, + { ".sse", PROCESSOR_UNKNOWN, + CPU_SSE_FLAGS }, + { ".sse2", PROCESSOR_UNKNOWN, + CPU_SSE2_FLAGS }, + { ".sse3", PROCESSOR_UNKNOWN, + CPU_SSE3_FLAGS }, + { ".ssse3", PROCESSOR_UNKNOWN, + CPU_SSSE3_FLAGS }, + { ".sse4.1", PROCESSOR_UNKNOWN, + CPU_SSE4_1_FLAGS }, + { ".sse4.2", PROCESSOR_UNKNOWN, + CPU_SSE4_2_FLAGS }, + { ".sse4", PROCESSOR_UNKNOWN, + CPU_SSE4_2_FLAGS }, + { ".vmx", PROCESSOR_UNKNOWN, + CPU_VMX_FLAGS }, + { ".smx", PROCESSOR_UNKNOWN, + CPU_SMX_FLAGS }, + { ".3dnow", PROCESSOR_UNKNOWN, + CPU_3DNOW_FLAGS }, + { ".3dnowa", PROCESSOR_UNKNOWN, + CPU_3DNOWA_FLAGS }, + { ".padlock", PROCESSOR_UNKNOWN, + CPU_PADLOCK_FLAGS }, + { ".pacifica", PROCESSOR_UNKNOWN, + CPU_SVME_FLAGS }, + { ".svme", PROCESSOR_UNKNOWN, + CPU_SVME_FLAGS }, + { ".sse4a", PROCESSOR_UNKNOWN, + CPU_SSE4A_FLAGS }, + { ".abm", PROCESSOR_UNKNOWN, + CPU_ABM_FLAGS }, + { ".sse5", PROCESSOR_UNKNOWN, + CPU_SSE5_FLAGS }, }; const pseudo_typeS md_pseudo_table[] = @@ -1653,7 +1779,16 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED) cpu_arch[i].flags); if (!UINTS_EQUAL (flags, cpu_arch_flags)) { - cpu_sub_arch_name = cpu_arch[i].name; + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (name, + cpu_arch[i].name, + NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (cpu_arch[i].name); cpu_arch_flags = flags; } *input_line_pointer = e; @@ -7049,6 +7184,7 @@ int md_parse_option (int c, char *arg) { unsigned int i; + char *arch, *next; switch (c) { @@ -7124,24 +7260,62 @@ md_parse_option (int c, char *arg) break; case OPTION_MARCH: - if (*arg == '.') - as_fatal (_("Invalid -march= option: `%s'"), arg); - for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) - { - if (strcmp (arg, cpu_arch [i].name) == 0) + arch = xstrdup (arg); + do + { + if (*arch == '.') + as_fatal (_("Invalid -march= option: `%s'"), arg); + next = strchr (arch, '+'); + if (next) + *next++ = '\0'; + for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) { - cpu_arch_isa = cpu_arch[i].type; - cpu_arch_isa_flags = cpu_arch[i].flags; - if (!cpu_arch_tune_set) + if (strcmp (arch, cpu_arch [i].name) == 0) + { + /* Processor. */ + cpu_arch_name = cpu_arch[i].name; + cpu_sub_arch_name = NULL; + cpu_arch_flags = cpu_arch[i].flags; + cpu_arch_isa = cpu_arch[i].type; + cpu_arch_isa_flags = cpu_arch[i].flags; + if (!cpu_arch_tune_set) + { + cpu_arch_tune = cpu_arch_isa; + cpu_arch_tune_flags = cpu_arch_isa_flags; + } + break; + } + else if (*cpu_arch [i].name == '.' + && strcmp (arch, cpu_arch [i].name + 1) == 0) { - cpu_arch_tune = cpu_arch_isa; - cpu_arch_tune_flags = cpu_arch_isa_flags; + /* ISA entension. */ + i386_cpu_flags flags; + flags = cpu_flags_or (cpu_arch_flags, + cpu_arch[i].flags); + if (!UINTS_EQUAL (flags, cpu_arch_flags)) + { + if (cpu_sub_arch_name) + { + char *name = cpu_sub_arch_name; + cpu_sub_arch_name = concat (name, + cpu_arch[i].name, + NULL); + free (name); + } + else + cpu_sub_arch_name = xstrdup (cpu_arch[i].name); + cpu_arch_flags = flags; + } + break; } - break; } + + if (i >= ARRAY_SIZE (cpu_arch)) + as_fatal (_("Invalid -march= option: `%s'"), arg); + + arch = next; } - if (i >= ARRAY_SIZE (cpu_arch)) - as_fatal (_("Invalid -march= option: `%s'"), arg); + while (next != NULL ); break; case OPTION_MTUNE: @@ -7226,7 +7400,16 @@ md_show_usage (stream) --divide ignored\n")); #endif fprintf (stream, _("\ - -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\ + -march=CPU[,+EXTENSION...]\n\ + generate code for CPU and EXTENSION, CPU is one of:\n\ + i386, i486, pentium, pentiumpro, pentium4, nocona,\n\ + core, core2, k6, athlon, k8, generic32, generic64\n\ + EXTENSION is combination of:\n\ + mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\ + vmx, smx, 3dnow, 3dnowa, sse4a, sse5, svme, abm,\n\ + padlock\n")); + fprintf (stream, _("\ + -mtune=CPU optimize for CPU, where CPU is one of:\n\ i386, i486, pentium, pentiumpro, pentium4, nocona,\n\ core, core2, k6, athlon, k8, generic32, generic64\n")); fprintf (stream, _("\ diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h index 1cfbd4e..aa5d13c 100644 --- a/gas/config/tc-i386.h +++ b/gas/config/tc-i386.h @@ -98,128 +98,6 @@ extern const char extra_symbol_chars[]; extern const char *i386_comment_chars; #define tc_comment_chars i386_comment_chars -/* Prefixes will be emitted in the order defined below. - WAIT_PREFIX must be the first prefix since FWAIT is really is an - instruction, and so must come before any prefixes. - The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, - LOCKREP_PREFIX. */ -#define WAIT_PREFIX 0 -#define SEG_PREFIX 1 -#define ADDR_PREFIX 2 -#define DATA_PREFIX 3 -#define LOCKREP_PREFIX 4 -#define REX_PREFIX 5 /* must come last. */ -#define MAX_PREFIXES 6 /* max prefixes per opcode */ - -/* we define the syntax here (modulo base,index,scale syntax) */ -#define REGISTER_PREFIX '%' -#define IMMEDIATE_PREFIX '$' -#define ABSOLUTE_PREFIX '*' - -/* these are the instruction mnemonic suffixes in AT&T syntax or - memory operand size in Intel syntax. */ -#define WORD_MNEM_SUFFIX 'w' -#define BYTE_MNEM_SUFFIX 'b' -#define SHORT_MNEM_SUFFIX 's' -#define LONG_MNEM_SUFFIX 'l' -#define QWORD_MNEM_SUFFIX 'q' -#define XMMWORD_MNEM_SUFFIX 'x' -/* Intel Syntax. Use a non-ascii letter since since it never appears - in instructions. */ -#define LONG_DOUBLE_MNEM_SUFFIX '\1' - -#define END_OF_INSN '\0' - -/* - 'templates' is for grouping together 'template' structures for opcodes - of the same name. This is only used for storing the insns in the grand - ole hash table of insns. - The templates themselves start at START and range up to (but not including) - END. - */ -typedef struct -{ - const template *start; - const template *end; -} -templates; - -/* 386 operand encoding bytes: see 386 book for details of this. */ -typedef struct -{ - unsigned int regmem; /* codes register or memory operand */ - unsigned int reg; /* codes register operand (or extended opcode) */ - unsigned int mode; /* how to interpret regmem & reg */ -} -modrm_byte; - -/* x86-64 extension prefix. */ -typedef int rex_byte; - -/* The SSE5 instructions have a two bit instruction modifier (OC) that - is stored in two separate bytes in the instruction. Pick apart OC - into the 2 separate bits for instruction. */ -#define DREX_OC0(x) (((x) & 1) != 0) -#define DREX_OC1(x) (((x) & 2) != 0) - -#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ -#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ - -/* OC mappings */ -#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ -#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ -#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ -#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ - -#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ -#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ - -/* Information needed to create the DREX byte in SSE5 instructions. */ -typedef struct -{ - unsigned int reg; /* register */ - unsigned int rex; /* REX flags */ - unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ - unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ -} drex_byte; - -/* 386 opcode byte to code indirect addressing. */ -typedef struct -{ - unsigned base; - unsigned index; - unsigned scale; -} -sib_byte; - -enum processor_type -{ - PROCESSOR_UNKNOWN, - PROCESSOR_I386, - PROCESSOR_I486, - PROCESSOR_PENTIUM, - PROCESSOR_PENTIUMPRO, - PROCESSOR_PENTIUM4, - PROCESSOR_NOCONA, - PROCESSOR_CORE, - PROCESSOR_CORE2, - PROCESSOR_K6, - PROCESSOR_ATHLON, - PROCESSOR_K8, - PROCESSOR_GENERIC32, - PROCESSOR_GENERIC64, - PROCESSOR_AMDFAM10 -}; - -/* x86 arch names, types and features */ -typedef struct -{ - const char *name; /* arch name */ - enum processor_type type; /* arch type */ - i386_cpu_flags flags; /* cpu feature flags */ -} -arch_entry; - /* The name of the global offset table generated by the compiler. Allow this to be overridden if need be. */ #ifndef GLOBAL_OFFSET_TABLE_NAME diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 81c105a..0520e47 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -302,7 +302,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @emph{Target i386 options:} [@b{--32}|@b{--64}] [@b{-n}] - [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] + [@b{-march}=@var{CPU}[+@var{EXTENSION}@dots{}]] [@b{-mtune}=@var{CPU}] @end ifset @ifset I960 diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 3b1a2ca..721d857 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -78,9 +78,11 @@ affect using @samp{#} for starting a comment. @cindex @samp{-march=} option, i386 @cindex @samp{-march=} option, x86-64 -@item -march=@var{CPU} -This option specifies an instruction set architecture for generating -instructions. The following architectures are recognized: +@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] +This option specifies the target processor. The assembler will +issue an error message if an attempt is made to assemble an instruction +which will not execute on the target processor. The following +processor names are recognized: @code{i8086}, @code{i186}, @code{i286}, @@ -106,7 +108,29 @@ instructions. The following architectures are recognized: @code{generic32} and @code{generic64}. -This option only affects instructions generated by the assembler. The +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics. For example, +@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and +@var{vmx}. The following extensions are currently supported: +@code{mmx}, +@code{sse}, +@code{sse2}, +@code{sse3}, +@code{ssse3}, +@code{sse4.1}, +@code{sse4.2}, +@code{sse4}, +@code{vmx}, +@code{smx}, +@code{3dnow}, +@code{3dnowa}, +@code{sse4a}, +@code{sse5}, +@code{svme}, +@code{abm} and +@code{padlock}. + +When the @code{.arch} directive is used with @option{-march}, the @code{.arch} directive will take precedent. @cindex @samp{-mtune=} option, i386 @@ -117,7 +141,8 @@ conjunction with the @option{-march} option, only instructions of the processor specified by the @option{-march} option will be generated. -Valid @var{CPU} values are identical to @option{-march=@var{CPU}}. +Valid @var{CPU} values are identical to the processor list of +@option{-march=@var{CPU}}. @cindex @samp{-mmnemonic=} option, i386 @cindex @samp{-mmnemonic=} option, x86-64 diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 5f2f9f0..dc1721c 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,25 @@ +2008-01-22 H.J. Lu <hongjiu.lu@intel.com> + + * gas/i386/arch-10-1.l: New. + * gas/i386/arch-10-1.s: Likewise. + * gas/i386/arch-10-2.l: Likewise. + * gas/i386/arch-10-2.s: Likewise. + * gas/i386/arch-10-3.l: Likewise. + * gas/i386/arch-10-3.s: Likewise. + * gas/i386/arch-10-4.l: Likewise. + * gas/i386/arch-10-4.s: Likewise. + * gas/i386/arch-10.d: Likewise. + * gas/i386/arch-10.s: Likewise. + + * gas/i386/i386.exp: Run arch-10, arch-10-1, arch-10-2, + arch-10-3 and arch-10-4. + + * gas/i386/nops-2.s: Use movsbl instead of cmove. + * gas/i386/nops-2-i386.d: Updated. + * gas/i386/nops-2-merom.d: Likewise. + * gas/i386/nops-2.d: Likewise. + * gas/i386/x86-64-nops-2.d: Likewise. + 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/prescott.s: Add tests for movddup in Intel syntax. diff --git a/gas/testsuite/gas/i386/arch-10-1.l b/gas/testsuite/gas/i386/arch-10-1.l new file mode 100644 index 0000000..c5fc40e --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-1.l @@ -0,0 +1,58 @@ +.*: Assembler messages: +.*:4: Error: .* +.*:6: Error: .* +.*:8: Error: .* +.*:10: Error: .* +.*:12: Error: .* +.*:14: Error: .* +.*:16: Error: .* +.*:18: Error: .* +.*:20: Error: .* +.*:22: Error: .* +.*:24: Error: .* +.*:26: Error: .* +.*:28: Error: .* +.*:30: Error: .* +.*:32: Error: .* +.*:34: Error: .* +.*:36: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\.include "arch-10\.s" +[ ]*1[ ]+\# Test -march= +[ ]*2[ ]+\.text +[ ]*3[ ]+\# cmov feature +[ ]*4[ ]+cmove %eax,%ebx +[ ]*5[ ]+\# MMX +[ ]*6[ ]+paddb %mm4,%mm3 +[ ]*7[ ]+\# SSE +[ ]*8[ ]+addss %xmm4,%xmm3 +[ ]*9[ ]+\# SSE2 +[ ]*10[ ]+addsd %xmm4,%xmm3 +[ ]*11[ ]+\# SSE3 +[ ]*12[ ]+addsubpd %xmm4,%xmm3 +[ ]*13[ ]+\# SSSE3 +[ ]*14[ ]+phaddw %xmm4,%xmm3 +[ ]*15[ ]+\# SSE4\.1 +[ ]*16[ ]+phminposuw %xmm1,%xmm3 +[ ]*17[ ]+\# SSE4\.2 +[ ]*18[ ]+crc32 %ecx,%ebx +[ ]*19[ ]+\# VMX +[ ]*20[ ]+vmxoff +[ ]*21[ ]+\# SMX +[ ]*22[ ]+getsec +[ ]*23[ ]+\# 3DNow +[ ]*24[ ]+pmulhrw %mm4,%mm3 +[ ]*25[ ]+\# 3DNow Extensions +[ ]*26[ ]+pswapd %mm4,%mm3 +[ ]*27[ ]+\# SSE4a +[ ]*28[ ]+insertq %xmm2,%xmm1 +[ ]*29[ ]+\# SVME +[ ]*30[ ]+vmload +[ ]*31[ ]+\# ABM +[ ]*32[ ]+lzcnt %ecx,%ebx +[ ]*33[ ]+\# SSE5 +[ ]*34[ ]+frczss %xmm2, %xmm1 +[ ]*35[ ]+\# PadLock +[ ]*36[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-1.s b/gas/testsuite/gas/i386/arch-10-1.s new file mode 100644 index 0000000..6805c7a --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-1.s @@ -0,0 +1 @@ +.include "arch-10.s" diff --git a/gas/testsuite/gas/i386/arch-10-2.l b/gas/testsuite/gas/i386/arch-10-2.l new file mode 100644 index 0000000..5c174dd --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-2.l @@ -0,0 +1,57 @@ +.*: Assembler messages: +.*:6: Error: .* +.*:8: Error: .* +.*:10: Error: .* +.*:12: Error: .* +.*:14: Error: .* +.*:16: Error: .* +.*:18: Error: .* +.*:20: Error: .* +.*:22: Error: .* +.*:24: Error: .* +.*:26: Error: .* +.*:28: Error: .* +.*:30: Error: .* +.*:32: Error: .* +.*:34: Error: .* +.*:36: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\.include "arch-10\.s" +[ ]*1[ ]+\# Test -march= +[ ]*2[ ]+\.text +[ ]*3[ ]+\# cmov feature +[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx +[ ]*5[ ]+\# MMX +[ ]*6[ ]+paddb %mm4,%mm3 +[ ]*7[ ]+\# SSE +[ ]*8[ ]+addss %xmm4,%xmm3 +[ ]*9[ ]+\# SSE2 +[ ]*10[ ]+addsd %xmm4,%xmm3 +[ ]*11[ ]+\# SSE3 +[ ]*12[ ]+addsubpd %xmm4,%xmm3 +[ ]*13[ ]+\# SSSE3 +[ ]*14[ ]+phaddw %xmm4,%xmm3 +[ ]*15[ ]+\# SSE4\.1 +[ ]*16[ ]+phminposuw %xmm1,%xmm3 +[ ]*17[ ]+\# SSE4\.2 +[ ]*18[ ]+crc32 %ecx,%ebx +[ ]*19[ ]+\# VMX +[ ]*20[ ]+vmxoff +[ ]*21[ ]+\# SMX +[ ]*22[ ]+getsec +[ ]*23[ ]+\# 3DNow +[ ]*24[ ]+pmulhrw %mm4,%mm3 +[ ]*25[ ]+\# 3DNow Extensions +[ ]*26[ ]+pswapd %mm4,%mm3 +[ ]*27[ ]+\# SSE4a +[ ]*28[ ]+insertq %xmm2,%xmm1 +[ ]*29[ ]+\# SVME +[ ]*30[ ]+vmload +[ ]*31[ ]+\# ABM +[ ]*32[ ]+lzcnt %ecx,%ebx +[ ]*33[ ]+\# SSE5 +[ ]*34[ ]+frczss %xmm2, %xmm1 +[ ]*35[ ]+\# PadLock +[ ]*36[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-2.s b/gas/testsuite/gas/i386/arch-10-2.s new file mode 100644 index 0000000..6805c7a --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-2.s @@ -0,0 +1 @@ +.include "arch-10.s" diff --git a/gas/testsuite/gas/i386/arch-10-3.l b/gas/testsuite/gas/i386/arch-10-3.l new file mode 100644 index 0000000..e628e8b --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-3.l @@ -0,0 +1,53 @@ +.*: Assembler messages: +.*:20: Error: .* +.*:22: Error: .* +.*:24: Error: .* +.*:26: Error: .* +.*:28: Error: .* +.*:30: Error: .* +.*:32: Error: .* +.*:34: Error: .* +.*:36: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\.include "arch-10\.s" +[ ]*1[ ]+\# Test -march= +[ ]*2[ ]+\.text +[ ]*3[ ]+\# cmov feature +[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx +[ ]*5[ ]+\# MMX +[ ]*6[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3 +[ ]*7[ ]+\# SSE +[ ]*8[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3 +[ ]*9[ ]+\# SSE2 +[ ]*10[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3 +[ ]*11[ ]+\# SSE3 +[ ]*12[ ]+\?\?\?\? 660FD0DC addsubpd %xmm4,%xmm3 +[ ]*13[ ]+\# SSSE3 +[ ]*14[ ]+\?\?\?\? 660F3801 phaddw %xmm4,%xmm3 +[ ]*14[ ]+DC +[ ]*15[ ]+\# SSE4\.1 +[ ]*16[ ]+\?\?\?\? 660F3841 phminposuw %xmm1,%xmm3 +[ ]*16[ ]+D9 +[ ]*17[ ]+\# SSE4\.2 +[ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx +[ ]*18[ ]+D9 +[ ]*19[ ]+\# VMX +[ ]*20[ ]+vmxoff +[ ]*21[ ]+\# SMX +[ ]*22[ ]+getsec +[ ]*23[ ]+\# 3DNow +[ ]*24[ ]+pmulhrw %mm4,%mm3 +[ ]*25[ ]+\# 3DNow Extensions +[ ]*26[ ]+pswapd %mm4,%mm3 +[ ]*27[ ]+\# SSE4a +[ ]*28[ ]+insertq %xmm2,%xmm1 +[ ]*29[ ]+\# SVME +[ ]*30[ ]+vmload +[ ]*31[ ]+\# ABM +[ ]*32[ ]+lzcnt %ecx,%ebx +[ ]*33[ ]+\# SSE5 +[ ]*34[ ]+frczss %xmm2, %xmm1 +[ ]*35[ ]+\# PadLock +[ ]*36[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-3.s b/gas/testsuite/gas/i386/arch-10-3.s new file mode 100644 index 0000000..6805c7a --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-3.s @@ -0,0 +1 @@ +.include "arch-10.s" diff --git a/gas/testsuite/gas/i386/arch-10-4.l b/gas/testsuite/gas/i386/arch-10-4.l new file mode 100644 index 0000000..670f8e7 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-4.l @@ -0,0 +1,51 @@ +.*: Assembler messages: +.*:24: Error: .* +.*:26: Error: .* +.*:28: Error: .* +.*:30: Error: .* +.*:32: Error: .* +.*:34: Error: .* +.*:36: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+\.include "arch-10\.s" +[ ]*1[ ]+\# Test -march= +[ ]*2[ ]+\.text +[ ]*3[ ]+\# cmov feature +[ ]*4[ ]+\?\?\?\? 0F44D8 cmove %eax,%ebx +[ ]*5[ ]+\# MMX +[ ]*6[ ]+\?\?\?\? 0FFCDC paddb %mm4,%mm3 +[ ]*7[ ]+\# SSE +[ ]*8[ ]+\?\?\?\? F30F58DC addss %xmm4,%xmm3 +[ ]*9[ ]+\# SSE2 +[ ]*10[ ]+\?\?\?\? F20F58DC addsd %xmm4,%xmm3 +[ ]*11[ ]+\# SSE3 +[ ]*12[ ]+\?\?\?\? 660FD0DC addsubpd %xmm4,%xmm3 +[ ]*13[ ]+\# SSSE3 +[ ]*14[ ]+\?\?\?\? 660F3801 phaddw %xmm4,%xmm3 +[ ]*14[ ]+DC +[ ]*15[ ]+\# SSE4\.1 +[ ]*16[ ]+\?\?\?\? 660F3841 phminposuw %xmm1,%xmm3 +[ ]*16[ ]+D9 +[ ]*17[ ]+\# SSE4\.2 +[ ]*18[ ]+\?\?\?\? F20F38F1 crc32 %ecx,%ebx +[ ]*18[ ]+D9 +[ ]*19[ ]+\# VMX +[ ]*20[ ]+\?\?\?\? 0F01C4 vmxoff +[ ]*21[ ]+\# SMX +[ ]*22[ ]+\?\?\?\? 0F37 getsec +[ ]*23[ ]+\# 3DNow +[ ]*24[ ]+pmulhrw %mm4,%mm3 +[ ]*25[ ]+\# 3DNow Extensions +[ ]*26[ ]+pswapd %mm4,%mm3 +[ ]*27[ ]+\# SSE4a +[ ]*28[ ]+insertq %xmm2,%xmm1 +[ ]*29[ ]+\# SVME +[ ]*30[ ]+vmload +[ ]*31[ ]+\# ABM +[ ]*32[ ]+lzcnt %ecx,%ebx +[ ]*33[ ]+\# SSE5 +[ ]*34[ ]+frczss %xmm2, %xmm1 +[ ]*35[ ]+\# PadLock +[ ]*36[ ]+xstorerng diff --git a/gas/testsuite/gas/i386/arch-10-4.s b/gas/testsuite/gas/i386/arch-10-4.s new file mode 100644 index 0000000..6805c7a --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10-4.s @@ -0,0 +1 @@ +.include "arch-10.s" diff --git a/gas/testsuite/gas/i386/arch-10.d b/gas/testsuite/gas/i386/arch-10.d new file mode 100644 index 0000000..c089b76 --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10.d @@ -0,0 +1,27 @@ +#as: -march=i686+sse4+vmx+smx+sse5+3dnowa+svme+padlock +#objdump: -dw +#name: i386 arch 10 + +.*: file format .* + +Disassembly of section .text: + +0+ <.text>: +[ ]*[a-f0-9]+: 0f 44 d8 cmove %eax,%ebx +[ ]*[a-f0-9]+: 0f fc dc paddb %mm4,%mm3 +[ ]*[a-f0-9]+: f3 0f 58 dc addss %xmm4,%xmm3 +[ ]*[a-f0-9]+: f2 0f 58 dc addsd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f d0 dc addsubpd %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 01 dc phaddw %xmm4,%xmm3 +[ ]*[a-f0-9]+: 66 0f 38 41 d9 phminposuw %xmm1,%xmm3 +[ ]*[a-f0-9]+: f2 0f 38 f1 d9 crc32l %ecx,%ebx +[ ]*[a-f0-9]+: 0f 01 c4 vmxoff +[ ]*[a-f0-9]+: 0f 37 getsec +[ ]*[a-f0-9]+: 0f 0f dc b7 pmulhrw %mm4,%mm3 +[ ]*[a-f0-9]+: 0f 0f dc bb pswapd %mm4,%mm3 +[ ]*[a-f0-9]+: f2 0f 79 ca insertq %xmm2,%xmm1 +[ ]*[a-f0-9]+: 0f 01 da vmload +[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx +[ ]*[a-f0-9]+: 0f 7a 12 ca frczss %xmm2,%xmm1 +[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng +#pass diff --git a/gas/testsuite/gas/i386/arch-10.s b/gas/testsuite/gas/i386/arch-10.s new file mode 100644 index 0000000..97478ed --- /dev/null +++ b/gas/testsuite/gas/i386/arch-10.s @@ -0,0 +1,36 @@ +# Test -march= + .text +# cmov feature +cmove %eax,%ebx +# MMX +paddb %mm4,%mm3 +# SSE +addss %xmm4,%xmm3 +# SSE2 +addsd %xmm4,%xmm3 +# SSE3 +addsubpd %xmm4,%xmm3 +# SSSE3 +phaddw %xmm4,%xmm3 +# SSE4.1 +phminposuw %xmm1,%xmm3 +# SSE4.2 +crc32 %ecx,%ebx +# VMX +vmxoff +# SMX +getsec +# 3DNow +pmulhrw %mm4,%mm3 +# 3DNow Extensions +pswapd %mm4,%mm3 +# SSE4a +insertq %xmm2,%xmm1 +# SVME +vmload +# ABM +lzcnt %ecx,%ebx +# SSE5 +frczss %xmm2, %xmm1 +# PadLock +xstorerng diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 12f64c1..9569f13 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -107,6 +107,11 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]] run_dump_test "arch-7" run_dump_test "arch-8" run_dump_test "arch-9" + run_dump_test "arch-10" + run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al" + run_list_test "arch-10-2" "-march=i686 -I${srcdir}/$subdir -al" + run_list_test "arch-10-3" "-march=i686+sse4.2 -I${srcdir}/$subdir -al" + run_list_test "arch-10-4" "-march=i686+sse4+vmx+smx -I${srcdir}/$subdir -al" # These tests require support for 8 and 16 bit relocs, # so we only run them for ELF and COFF targets. diff --git a/gas/testsuite/gas/i386/nops-2-i386.d b/gas/testsuite/gas/i386/nops-2-i386.d index 57f8dda..468a336 100644 --- a/gas/testsuite/gas/i386/nops-2-i386.d +++ b/gas/testsuite/gas/i386/nops-2-i386.d @@ -8,7 +8,7 @@ Disassembly of section .text: 0+ <nop>: -[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax +[ ]*0:[ ]+0f be f0[ ]+movsbl[ ]+%al,%esi [ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi [ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi diff --git a/gas/testsuite/gas/i386/nops-2-merom.d b/gas/testsuite/gas/i386/nops-2-merom.d index 7a54411..6cf50d0 100644 --- a/gas/testsuite/gas/i386/nops-2-merom.d +++ b/gas/testsuite/gas/i386/nops-2-merom.d @@ -8,7 +8,7 @@ Disassembly of section .text: 0+ <nop>: -[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax +[ ]*0:[ ]+0f be f0[ ]+movsbl[ ]+%al,%esi [ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi [ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi diff --git a/gas/testsuite/gas/i386/nops-2.d b/gas/testsuite/gas/i386/nops-2.d index 003a4eb..6cfbcfb 100644 --- a/gas/testsuite/gas/i386/nops-2.d +++ b/gas/testsuite/gas/i386/nops-2.d @@ -7,7 +7,7 @@ Disassembly of section .text: 0+ <nop>: -[ ]*0:[ ]+0f 44 c0[ ]+cmove[ ]+%eax,%eax +[ ]*0:[ ]+0f be f0[ ]+movsbl[ ]+%al,%esi [ ]*3:[ ]+8d b6 00 00 00 00[ ]+lea[ ]+0x0\(%esi\),%esi [ ]*9:[ ]+8d bc 27 00 00 00 00[ ]+lea[ ]+0x0\(%edi,%eiz,1\),%edi diff --git a/gas/testsuite/gas/i386/nops-2.s b/gas/testsuite/gas/i386/nops-2.s index afbb87e..6de16f2 100644 --- a/gas/testsuite/gas/i386/nops-2.s +++ b/gas/testsuite/gas/i386/nops-2.s @@ -1,6 +1,6 @@ .text nop: - cmove %eax,%eax + movsbl %al,%esi .p2align 4 nop15: diff --git a/gas/testsuite/gas/i386/x86-64-nops-2.d b/gas/testsuite/gas/i386/x86-64-nops-2.d index 2432b59..858c4c9 100644 --- a/gas/testsuite/gas/i386/x86-64-nops-2.d +++ b/gas/testsuite/gas/i386/x86-64-nops-2.d @@ -7,7 +7,7 @@ Disassembly of section .text: 0+ <nop>: -[ ]*[a-f0-9]+: 0f 44 c0 cmove %eax,%eax +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi [ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) 0+10 <nop15>: diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 20c0447..573c4dc 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2008-01-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and + CPU_SMX_FLAGS. + * i386-init.h: Regenerated. + 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Use Qword on movddup. diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 4f1b581..69c5a02 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -96,6 +96,10 @@ static initializer cpu_flag_init [] = "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1" }, { "CPU_SSE4_2_FLAGS", "CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2" }, + { "CPU_VMX_FLAGS", + "CpuVMX" }, + { "CPU_SMX_FLAGS", + "CpuSMX" }, { "CPU_3DNOW_FLAGS", "CpuMMX|Cpu3dnow" }, { "CPU_3DNOWA_FLAGS", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index b26db4f..624d006 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -130,6 +130,14 @@ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, \ 1, 0, 0, 1, 1, 0, 0, 0, 0, 0 } } +#define CPU_VMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + +#define CPU_SMX_FLAGS \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } + #define CPU_3DNOW_FLAGS \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } |