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-rw-r--r--gas/ChangeLog9
-rw-r--r--gas/config/tc-sh.c3
-rw-r--r--gas/testsuite/gas/sh/sh4a.d2
-rw-r--r--gas/testsuite/gas/sh/sh4a.s2
-rw-r--r--opcodes/ChangeLog8
-rw-r--r--opcodes/sh-dis.c6
-rw-r--r--opcodes/sh-opc.h35
7 files changed, 46 insertions, 19 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8cbe5ec..8df687b 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 22699
+ * config/tc-sh.c (build_Mytes): Change operand type IMM0_8 to
+ IMM0_8S and add support for IMM0_8U.
+ * testsuite/gas/sh/sh4a.s: Add test of a logical insn using an
+ unsigned 8-bit immediate.
+ * testsuite/gas/sh/sh4a.d: Extended expected disassembly.
+
2020-04-27 Tamar Christina <tamar.christina@arm.com>
* NEWS: Add news entry for big-obj.
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
index decbb29..d06cc5e 100644
--- a/gas/config/tc-sh.c
+++ b/gas/config/tc-sh.c
@@ -2091,7 +2091,8 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand)
case IMM0_8BY2:
insert (output + low_byte, BFD_RELOC_SH_IMM8BY2, 0, operand);
break;
- case IMM0_8:
+ case IMM0_8U:
+ case IMM0_8S:
insert (output + low_byte, BFD_RELOC_SH_IMM8, 0, operand);
break;
case IMM1_8BY4:
diff --git a/gas/testsuite/gas/sh/sh4a.d b/gas/testsuite/gas/sh/sh4a.d
index 0cdbf33..45fade6 100644
--- a/gas/testsuite/gas/sh/sh4a.d
+++ b/gas/testsuite/gas/sh/sh4a.d
@@ -25,3 +25,5 @@ Disassembly of section \.text:
0x0000001e 05 d3 prefi @r5
0x00000020 0a d3 prefi @r10
0x00000022 00 ab synco
+0x00000024 c8 80[ ]+tst[ ]+#128,r0
+#pass
diff --git a/gas/testsuite/gas/sh/sh4a.s b/gas/testsuite/gas/sh/sh4a.s
index 51c2382..6b68ec2 100644
--- a/gas/testsuite/gas/sh/sh4a.s
+++ b/gas/testsuite/gas/sh/sh4a.s
@@ -26,3 +26,5 @@
prefi @r10
synco
+
+ tst #128,r0
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e2cbe60..94b8a03 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 22699
+ * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
+ IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
+ * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
+ IMM0_8U case.
+
2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
PR 25848
diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
index 5d771a5..00bcffa 100644
--- a/opcodes/sh-dis.c
+++ b/opcodes/sh-dis.c
@@ -597,7 +597,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
case IMM1_4BY4:
imm = nibs[3] << 2;
goto ok;
- case IMM0_8:
+ case IMM0_8S:
case IMM1_8:
imm = (nibs[2] << 4) | nibs[3];
disp = imm;
@@ -605,6 +605,10 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
if (imm & 0x80)
imm -= 0x100;
goto ok;
+ case IMM0_8U:
+ disp = imm = (nibs[2] << 4) | nibs[3];
+ has_disp = 1;
+ goto ok;
case PCRELIMM_8BY2:
imm = ((nibs[2] << 4) | nibs[3]) << 1;
relmask = ~(bfd_vma) 1;
diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
index 93b5e98..cd9d2c2 100644
--- a/opcodes/sh-opc.h
+++ b/opcodes/sh-opc.h
@@ -61,7 +61,8 @@ typedef enum
IMM1_4BY4,
PCRELIMM_8BY2,
PCRELIMM_8BY4,
- IMM0_8,
+ IMM0_8S,
+ IMM0_8U,
IMM0_8BY2,
IMM0_8BY4,
IMM1_8,
@@ -381,7 +382,7 @@ typedef struct
const sh_opcode_info sh_table[] =
{
-/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up},
+/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8S}, arch_sh_up},
/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up},
@@ -389,11 +390,11 @@ const sh_opcode_info sh_table[] =
/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up},
-/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up},
+/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8U}, arch_sh_up},
/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up},
-/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up},
+/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8U}, arch_sh_up},
/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up},
@@ -419,7 +420,7 @@ const sh_opcode_info sh_table[] =
/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up},
-/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up},
+/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8S}, arch_sh_up},
/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up},
@@ -504,7 +505,7 @@ const sh_opcode_info sh_table[] =
/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},
/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
-/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
+/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8S}, arch_sh4al_dsp_up},
/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
@@ -558,7 +559,7 @@ const sh_opcode_info sh_table[] =
/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up},
-/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up},
+/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8S}, arch_sh_up},
/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up},
@@ -570,7 +571,7 @@ const sh_opcode_info sh_table[] =
/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up},
-/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up},
+/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8S}, arch_sh_up},
/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up},
@@ -677,11 +678,11 @@ const sh_opcode_info sh_table[] =
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
-/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up},
+/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8U}, arch_sh_up},
/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up},
-/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up},
+/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8U}, arch_sh_up},
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up},
@@ -707,11 +708,11 @@ const sh_opcode_info sh_table[] =
/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
-/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
+/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8S}, arch_sh_dsp_up},
/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
-/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
+/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8S,HEX_8}, arch_sh_dsp_up},
/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
@@ -843,19 +844,19 @@ const sh_opcode_info sh_table[] =
/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up},
-/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up},
+/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8U}, arch_sh_up},
-/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up},
+/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8U}, arch_sh_up},
/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up},
-/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up},
+/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8U}, arch_sh_up},
-/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up},
+/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8U}, arch_sh_up},
/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up},
-/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up},
+/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8U}, arch_sh_up},
/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up},
generated by cgit v1.1 at 2024-11-19 06:47:35 +0000