diff options
| -rw-r--r-- | gas/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/pseudos.d | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/pseudos.s | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-pseudos.d | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64-pseudos.s | 12 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 13 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 8 |
8 files changed, 67 insertions, 13 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 07d2b93..673e8d7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,12 @@ 2018-11-06 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/pseudos.s, + testsuite/gas/i386/x86-64-pseudos.s: Add pextrw / vpextrw cases. + * testsuite/gas/i386/pseudos.d, + testsuite/gas/i386/x86-64-pseudos.d: Adjust expectations. + +2018-11-06 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/avx-wig.s, testsuite/gas/i386/x86-64-avx-wig.s: Add vandp*, vandnp*, vorp*, vcmpeq*, and vcvtss2sd cases. diff --git a/gas/testsuite/gas/i386/pseudos.d b/gas/testsuite/gas/i386/pseudos.d index 65531bf..18804b2 100644 --- a/gas/testsuite/gas/i386/pseudos.d +++ b/gas/testsuite/gas/i386/pseudos.d @@ -1,5 +1,5 @@ #objdump: -drw -#name: pseudo prefxes +#name: pseudo prefixes .*: +file format .* @@ -264,6 +264,15 @@ Disassembly of section .text: +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7 +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7 +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7 + +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 66 0f 3a 15 c7 00 pextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: c4 e3 79 15 c7 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 62 f3 7d 08 15 c7 00 vpextrw \$0x0,%xmm0,%edi +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0 +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0 +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0 diff --git a/gas/testsuite/gas/i386/pseudos.s b/gas/testsuite/gas/i386/pseudos.s index 95da66c..419a4c5 100644 --- a/gas/testsuite/gas/i386/pseudos.s +++ b/gas/testsuite/gas/i386/pseudos.s @@ -265,6 +265,18 @@ _start: {load} {evex} vmovq %xmm0, %xmm7 {store} {evex} vmovq %xmm0, %xmm7 + pextrw $0, %xmm0, %edi + {load} pextrw $0, %xmm0, %edi + {store} pextrw $0, %xmm0, %edi + + vpextrw $0, %xmm0, %edi + {load} vpextrw $0, %xmm0, %edi + {store} vpextrw $0, %xmm0, %edi + + {evex} vpextrw $0, %xmm0, %edi + {load} {evex} vpextrw $0, %xmm0, %edi + {store} {evex} vpextrw $0, %xmm0, %edi + bndmov %bnd3, %bnd0 {load} bndmov %bnd3, %bnd0 {store} bndmov %bnd3, %bnd0 diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.d b/gas/testsuite/gas/i386/x86-64-pseudos.d index d38f837..55c42a0 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.d +++ b/gas/testsuite/gas/i386/x86-64-pseudos.d @@ -1,5 +1,5 @@ #objdump: -drw -#name: x86-64 pseudo prefxes +#name: x86-64 pseudo prefixes .*: +file format .* @@ -276,6 +276,15 @@ Disassembly of section .text: +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7 +[a-f0-9]+: 62 f1 fe 08 7e f8 vmovq %xmm0,%xmm7 +[a-f0-9]+: 62 f1 fd 08 d6 c7 vmovq %xmm0,%xmm7 + +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 66 0f c5 f8 00 pextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 66 0f 3a 15 c7 00 pextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: c5 f9 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: c4 e3 79 15 c7 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 62 f1 7d 08 c5 f8 00 vpextrw \$0x0,%xmm0,%edi + +[a-f0-9]+: 62 f3 7d 08 15 c7 00 vpextrw \$0x0,%xmm0,%edi +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0 +[a-f0-9]+: 66 0f 1a c3 bndmov %bnd3,%bnd0 +[a-f0-9]+: 66 0f 1b d8 bndmov %bnd3,%bnd0 diff --git a/gas/testsuite/gas/i386/x86-64-pseudos.s b/gas/testsuite/gas/i386/x86-64-pseudos.s index b5d9a8c..33712d3 100644 --- a/gas/testsuite/gas/i386/x86-64-pseudos.s +++ b/gas/testsuite/gas/i386/x86-64-pseudos.s @@ -277,6 +277,18 @@ _start: {load} {evex} vmovq %xmm0, %xmm7 {store} {evex} vmovq %xmm0, %xmm7 + pextrw $0, %xmm0, %edi + {load} pextrw $0, %xmm0, %edi + {store} pextrw $0, %xmm0, %edi + + vpextrw $0, %xmm0, %edi + {load} vpextrw $0, %xmm0, %edi + {store} vpextrw $0, %xmm0, %edi + + {evex} vpextrw $0, %xmm0, %edi + {load} {evex} vpextrw $0, %xmm0, %edi + {store} {evex} vpextrw $0, %xmm0, %edi + bndmov %bnd3, %bnd0 {load} bndmov %bnd3, %bnd0 {store} bndmov %bnd3, %bnd0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 639ed34..8137672 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms. + (vpmaxub): Re-order attributes on AVX512BW flavor. + * i386-tbl.h: Re-generate. + +2018-11-06 Jan Beulich <jbeulich@suse.com> + * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*, vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of Vex=1 on AVX / AVX2 flavors. diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5b883e6..9f009e0 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1251,10 +1251,10 @@ pavgb, 2, 0x660fe0, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_q pavgw, 2, 0xfe3, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX } pavgw, 2, 0x66e3, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } pavgw, 2, 0x660fe3, None, 2, CpuSSE2, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 } +pextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64 } pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Imm8, RegXMM, Reg32|Reg64|RegMem } pextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Imm8, RegXMM, Word|Unspecified|BaseIndex } -pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +pextrw, 3, 0x660fc5, None, 2, CpuSSE2, Load|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem } pextrw, 3, 0x660f3a15, None, 3, CpuSSE4_1, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex } pextrw, 3, 0xfc5, None, 2, CpuSSE|Cpu3dnowA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64|NoAVX, { Imm8, RegMMX, Reg32|Reg64 } @@ -2101,7 +2101,7 @@ vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_ vpextrb, 3, 0x6614, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Byte|Unspecified|BaseIndex } vpextrd, 3, 0x6616, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vpextrq, 3, 0x6616, None, 1, CpuAVX|Cpu64, Modrm|Vex|VexOpcode=2|VexW=2|Size64|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64|Qword|Unspecified|BaseIndex } -vpextrw, 3, 0x66c5, None, 1, CpuAVX, Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } +vpextrw, 3, 0x66c5, None, 1, CpuAVX, Load|Modrm|Vex|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64 } vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Imm8, RegXMM, Reg32|Reg64|RegMem } vpextrw, 3, 0x6615, None, 1, CpuAVX, Modrm|Vex|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex } vphaddd, 3, 0x6602, None, 1, CpuAVX, Modrm|Vex|VexOpcode=1|VexVVVV=1|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM } @@ -4289,7 +4289,9 @@ vpcmpnltuw, 3, 0x663E, 5, 1, CpuAVX512BW, Modrm|Masking=2|VexOpcode=2|VexVVVV=1| vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|VexOpcode=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW, Modrm|VexOpcode=0|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Load|Modrm|EVex=4|VexOpcode=0|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 } +vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem } +vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex } vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexWIG|VexVVVV=1|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexWIG|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Word|Unspecified|BaseIndex, RegXMM, RegXMM } @@ -4298,9 +4300,6 @@ vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Ignore vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } -vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|RegMem } -vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexWIG|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Word|Unspecified|BaseIndex } - vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW, Modrm|Masking=3|VexOpcode=0|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmovb2m, 2, 0xF329, None, 1, CpuAVX512BW, Modrm|EVex=5|VexOpcode=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index d37b0b9..790169f 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -14479,7 +14479,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, + { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -14536,7 +14536,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, + { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -37445,7 +37445,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, + { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -37502,7 +37502,7 @@ const insn_template i386_optab[] = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, + { 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, |