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-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/testsuite/gas/z8k/inout.d4
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/z8k-opc.h8
-rw-r--r--opcodes/z8kgen.c4
5 files changed, 20 insertions, 8 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index cf0cc0d..771e865 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2020-08-04 Christian Groessler <chris@groessler.org>
+
+ * gas/testsuite/gas/z8k/inout.d: Adapt to correct encoding of
+ "sout/soutb #imm,reg"
+
2020-08-04 H.J. Lu <hongjiu.lu@intel.com>
* NEWS: Mention {disp16} pseudo prefix.
diff --git a/gas/testsuite/gas/z8k/inout.d b/gas/testsuite/gas/z8k/inout.d
index 7b9696b..21b69eb 100644
--- a/gas/testsuite/gas/z8k/inout.d
+++ b/gas/testsuite/gas/z8k/inout.d
@@ -461,8 +461,8 @@ Disassembly of section \.text:
68c: 3a21 0cd0 sinirb @r13,@r2,r12
690: 3a11 0ae0 sinirb @r14,@r1,r10
694: 3a01 09f0 sinirb @r15,@r0,r9
- 698: 3b06 beee out #0xbeee,r0
- 69c: 3a46 babe outb #0xbabe,rh4
+ 698: 3b07 beee sout #0xbeee,r0
+ 69c: 3a47 babe soutb #0xbabe,rh4
6a0: 3bfb 0808 soutd @r0,@r15,r8
6a4: 3beb 0718 soutd @r1,@r14,r7
6a8: 3bdb 0628 soutd @r2,@r13,r6
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3fae7c7..44c0ac2 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2020-08-04 Christian Groessler <chris@groessler.org>
+ Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
+
+ * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
+ opcodes (special "out" to absolute address).
+ * z8k-opc.h: Regenerate.
+
2020-07-30 H.J. Lu <hongjiu.lu@intel.com>
PR gas/26305
diff --git a/opcodes/z8k-opc.h b/opcodes/z8k-opc.h
index 35ce4bc..c852e1c 100644
--- a/opcodes/z8k-opc.h
+++ b/opcodes/z8k-opc.h
@@ -3252,21 +3252,21 @@ const opcode_entry_type z8k_table[] = {
"sotirb",OPC_sotirb,0,{CLASS_IRO+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),},
{CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RD),CLASS_BIT+0,0,},3,4,170},
-/* 0011 1011 ssss 0110 imm16 *** sout imm16,rs */
+/* 0011 1011 ssss 0111 imm16 *** sout imm16,rs */
{
#ifdef NICENAMES
"sout imm16,rs",16,12,0x00,
#endif
"sout",OPC_sout,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),},
- {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,171},
+ {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,171},
-/* 0011 1010 ssss 0110 imm16 *** soutb imm16,rbs */
+/* 0011 1010 ssss 0111 imm16 *** soutb imm16,rbs */
{
#ifdef NICENAMES
"soutb imm16,rbs",8,12,0x00,
#endif
"soutb",OPC_soutb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),},
- {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,172},
+ {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,172},
/* 0011 1011 ssN0 1011 0000 aaaa dddd 1000 *** soutd @ro,@rs,ra */
{
diff --git a/opcodes/z8kgen.c b/opcodes/z8kgen.c
index b72fcff..e22e6d6 100644
--- a/opcodes/z8kgen.c
+++ b/opcodes/z8kgen.c
@@ -458,8 +458,8 @@ static struct op opt[] =
{"CZS---", 13, 8, "1011 0010 dddd 0001 iiii iiii 0000 imm4", "sllb rbd,imm4", 0},
{"CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0},
- {"------", 12, 16, "0011 1011 ssss 0110 imm16", "sout imm16,rs", 0},
- {"------", 12, 8, "0011 1010 ssss 0110 imm16", "soutb imm16,rbs", 0},
+ {"------", 12, 16, "0011 1011 ssss 0111 imm16", "sout imm16,rs", 0},
+ {"------", 12, 8, "0011 1010 ssss 0111 imm16", "soutb imm16,rbs", 0},
{"---V--", 21, 16, "0011 1011 ssN0 1011 0000 aaaa dddd 1000", "soutd @ro,@rs,ra", 0},
{"---V--", 21, 8, "0011 1010 ssN0 1011 0000 aaaa dddd 1000", "soutdb @ro,@rs,ra", 0},
{"---V--", 11, 16, "0011 1011 ssN0 1011 0000 aaaa dddd 0000", "sotdr @ro,@rs,ra", 0},