diff options
| -rw-r--r-- | bfd/ChangeLog | 4 | ||||
| -rw-r--r-- | bfd/elfxx-ia64.c | 2 | ||||
| -rw-r--r-- | gas/ChangeLog | 4 | ||||
| -rw-r--r-- | gas/config/tc-ia64.h | 1 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/ia64/dv-imply.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/ia64/dv-mutex.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/ia64/dv-safe.d | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/ia64/dv-srlz.d | 4 | ||||
| -rw-r--r-- | gas/testsuite/gas/ia64/opc-m.d | 1728 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 12 | ||||
| -rw-r--r-- | opcodes/ia64-asmtab.c | 1398 | ||||
| -rw-r--r-- | opcodes/ia64-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/ia64-gen.c | 22 | ||||
| -rw-r--r-- | opcodes/ia64-opc.c | 3 |
15 files changed, 1624 insertions, 1591 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index ed0fb41..d747462 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,7 @@ +2000-12-12 Jim Wilson <wilson@redhat.com> + + * elfxx-ia64.c (get_dyn_sym_info): Cast %p argument to void *. + 2000-12-08 Mark Salter <msalter@redhat.com> * binary.c (binary_set_section_contents): Ignore sections diff --git a/bfd/elfxx-ia64.c b/bfd/elfxx-ia64.c index 5f93287..56087a6 100644 --- a/bfd/elfxx-ia64.c +++ b/bfd/elfxx-ia64.c @@ -1504,7 +1504,7 @@ get_dyn_sym_info (ia64_info, h, abfd, rel, create) len += 10; /* %p slop */ addr_name = alloca (len); - sprintf (addr_name, "%p:%lx", abfd, ELFNN_R_SYM (rel->r_info)); + sprintf (addr_name, "%p:%lx", (void *) abfd, ELFNN_R_SYM (rel->r_info)); /* Collect the canonical entry data for this address. */ loc_h = elfNN_ia64_local_hash_lookup (&ia64_info->loc_hash_table, diff --git a/gas/ChangeLog b/gas/ChangeLog index 21901da..2ba9c0e 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,7 @@ +2000-12-12 Jim Wilson <wilson@redhat.com> + + * config/tc-ia64.h (ia64_init): Add prototype. + 2000-12-12 H.J. Lu <hjl@gnu.org> * dwarf2dbg.c: Enabled only if BFD_ASSEMBLER is defined. diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h index 264fe12..73add66 100644 --- a/gas/config/tc-ia64.h +++ b/gas/config/tc-ia64.h @@ -39,6 +39,7 @@ md_parse_args. */ #define HOST_SPECIAL_INIT ia64_init +extern void ia64_init PARAMS ((int, char **)); #define TARGET_FORMAT ia64_target_format() extern const char *ia64_target_format PARAMS ((void)); diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index e47bc4d..213b4d3 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2000-12-12 Jim Wilson <wilson@redhat.com> + + * gas/ia64/dv-imply.d, gas/ia64/dv-mutex.d, gas/ia64/dv-safe.d, + gas/ia64/dv-srlz.d, gas/ia64/opc-m.d: Update. + 2000-12-12 Nick Clifton <nickc@redhat.com> * gas/vtable/vtable.exp: Fix formatting. diff --git a/gas/testsuite/gas/ia64/dv-imply.d b/gas/testsuite/gas/ia64/dv-imply.d index c8d9bca..d009be07 100644 --- a/gas/testsuite/gas/ia64/dv-imply.d +++ b/gas/testsuite/gas/ia64/dv-imply.d @@ -22,18 +22,18 @@ Disassembly of section \.text: 40: 6a 08 06 04 02 78 \[MMI\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2;; 46: 40 10 00 00 42 00 \(p01\) mov r4=2 4c: 00 00 04 00 nop\.i 0x0 - 50: 76 00 1c 00 00 10 \[BBB\] \(p03\) br\.cond\.sptk\.few c0 <L> - 56: 00 00 00 00 10 00 nop\.b 0x0 - 5c: 00 00 00 20 nop\.b 0x0 + 50: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 56: 00 00 00 02 80 01 nop\.f 0x0 + 5c: 70 00 00 40 \(p03\) br\.cond\.sptk\.few c0 <L> 60: 1d 20 1c 00 00 21 \[MFB\] mov r4=7 66: 00 00 00 02 00 00 nop\.f 0x0 6c: 00 00 20 00 rfi;; 70: 62 08 06 04 02 38 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2 76: 30 28 18 88 e8 80 cmp\.eq\.or p3,p4=r5,r6;; 7c: 20 00 00 84 \(p01\) mov r4=2 - 80: 76 00 10 00 00 10 \[BBB\] \(p03\) br\.cond\.sptk\.few c0 <L> - 86: 00 00 00 00 10 00 nop\.b 0x0 - 8c: 00 00 00 20 nop\.b 0x0 + 80: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 86: 00 00 00 02 80 01 nop\.f 0x0 + 8c: 40 00 00 40 \(p03\) br\.cond\.sptk\.few c0 <L> 90: 1d 20 1c 00 00 21 \[MFB\] mov r4=7 96: 00 00 00 02 00 00 nop\.f 0x0 9c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-mutex.d b/gas/testsuite/gas/ia64/dv-mutex.d index e21a80f..f5663a6 100644 --- a/gas/testsuite/gas/ia64/dv-mutex.d +++ b/gas/testsuite/gas/ia64/dv-mutex.d @@ -10,18 +10,18 @@ Disassembly of section \.text: 0: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2 6: 40 28 00 00 c2 81 \(p02\) mov r4=5 c: 70 00 00 84 \(p03\) mov r4=7 - 10: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 16: 00 00 00 00 10 00 nop\.b 0x0 + 10: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 16: 00 00 00 02 00 00 nop\.f 0x0 1c: 00 00 20 00 rfi;; 20: 0a 08 04 04 02 78 \[MMI\] cmp\.eq p1,p2=r1,r2;; 26: 40 10 00 00 42 81 \(p01\) mov r4=2 2c: 40 00 00 84 \(p02\) mov r4=4 - 30: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 36: 00 00 00 00 10 00 nop\.b 0x0 + 30: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 36: 00 00 00 02 00 00 nop\.f 0x0 3c: 00 00 20 00 rfi;; 40: 60 08 06 04 02 78 \[MII\] \(p03\) cmp\.eq\.unc p1,p2=r1,r2 46: 40 10 00 00 42 81 \(p01\) mov r4=2 4c: 40 00 00 84 \(p02\) mov r4=4 - 50: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 56: 00 00 00 00 10 00 nop\.b 0x0 + 50: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 56: 00 00 00 02 00 00 nop\.f 0x0 5c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/dv-safe.d b/gas/testsuite/gas/ia64/dv-safe.d index de0e892..c45ef9b 100644 --- a/gas/testsuite/gas/ia64/dv-safe.d +++ b/gas/testsuite/gas/ia64/dv-safe.d @@ -10,9 +10,9 @@ Disassembly of section \.text: 0: 02 08 04 04 02 38 \[MII\] cmp\.eq p1,p2=r1,r2 6: 30 18 10 08 70 00 cmp\.eq p3,p4=r3,r4;; c: 00 00 04 00 nop\.i 0x0 - 10: 76 08 0c 00 00 14 \[BBB\] \(p03\) br\.call\.sptk\.few b1=40 <L> - 16: 00 00 00 00 10 00 nop\.b 0x0 - 1c: 00 00 00 20 nop\.b 0x0 + 10: 1c 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 16: 00 00 00 02 80 21 nop\.f 0x0 + 1c: 30 00 00 50 \(p03\) br\.call\.sptk\.few b1=40 <L> 20: 20 20 08 00 00 a1 \[MII\] \(p01\) mov r4=2 26: 40 28 00 00 c2 a1 \(p02\) mov r4=5 2c: 00 30 00 84 \(p03\) mov r5=r6 diff --git a/gas/testsuite/gas/ia64/dv-srlz.d b/gas/testsuite/gas/ia64/dv-srlz.d index 856cfde..31759a1 100644 --- a/gas/testsuite/gas/ia64/dv-srlz.d +++ b/gas/testsuite/gas/ia64/dv-srlz.d @@ -19,6 +19,6 @@ Disassembly of section \.text: 30: 17 00 00 00 10 00 \[BBB\] epc 36: 00 00 00 00 10 00 nop\.b 0x0 3c: 00 00 00 20 nop\.b 0x0;; - 40: 17 00 00 00 00 08 \[BBB\] nop\.b 0x0 - 46: 00 00 00 00 10 00 nop\.b 0x0 + 40: 1d 00 00 00 01 00 \[MFB\] nop\.m 0x0 + 46: 00 00 00 02 00 00 nop\.f 0x0 4c: 00 00 20 00 rfi;; diff --git a/gas/testsuite/gas/ia64/opc-m.d b/gas/testsuite/gas/ia64/opc-m.d index ad72767..3549b2e 100644 --- a/gas/testsuite/gas/ia64/opc-m.d +++ b/gas/testsuite/gas/ia64/opc-m.d @@ -6,1263 +6,1263 @@ Disassembly of section \.text: 0000000000000000 <_start>: - 0: 0e 20 00 0a 00 10 \[MMF\] ld1 r4=\[r5\] + 0: 18 20 00 0a 00 10 \[MMB\] ld1 r4=\[r5\] 6: 40 30 14 00 24 00 ld1 r4=\[r5\],r6 - c: 00 00 04 00 nop\.f 0x0 - 10: 0e 20 00 0a 00 16 \[MMF\] ld1 r4=\[r5\],-256 + c: 00 00 00 20 nop\.b 0x0 + 10: 18 20 00 0a 00 16 \[MMB\] ld1 r4=\[r5\],-256 16: 40 00 14 04 20 00 ld1\.nt1 r4=\[r5\] - 1c: 00 00 04 00 nop\.f 0x0 - 20: 0e 20 18 0a 02 12 \[MMF\] ld1\.nt1 r4=\[r5\],r6 + 1c: 00 00 00 20 nop\.b 0x0 + 20: 18 20 18 0a 02 12 \[MMB\] ld1\.nt1 r4=\[r5\],r6 26: 40 68 14 04 2c 00 ld1\.nt1 r4=\[r5\],-243 - 2c: 00 00 04 00 nop\.f 0x0 - 30: 0e 20 00 0a 06 10 \[MMF\] ld1\.nta r4=\[r5\] + 2c: 00 00 00 20 nop\.b 0x0 + 30: 18 20 00 0a 06 10 \[MMB\] ld1\.nta r4=\[r5\] 36: 40 30 14 0c 24 00 ld1\.nta r4=\[r5\],r6 - 3c: 00 00 04 00 nop\.f 0x0 - 40: 0e 20 68 0a 06 16 \[MMF\] ld1\.nta r4=\[r5\],-230 + 3c: 00 00 00 20 nop\.b 0x0 + 40: 18 20 68 0a 06 16 \[MMB\] ld1\.nta r4=\[r5\],-230 46: 40 00 14 40 20 00 ld1\.s r4=\[r5\] - 4c: 00 00 04 00 nop\.f 0x0 - 50: 0e 20 18 0a 20 12 \[MMF\] ld1\.s r4=\[r5\],r6 + 4c: 00 00 00 20 nop\.b 0x0 + 50: 18 20 18 0a 20 12 \[MMB\] ld1\.s r4=\[r5\],r6 56: 40 38 15 40 2c 00 ld1\.s r4=\[r5\],-217 - 5c: 00 00 04 00 nop\.f 0x0 - 60: 0e 20 00 0a 22 10 \[MMF\] ld1\.s\.nt1 r4=\[r5\] + 5c: 00 00 00 20 nop\.b 0x0 + 60: 18 20 00 0a 22 10 \[MMB\] ld1\.s\.nt1 r4=\[r5\] 66: 40 30 14 44 24 00 ld1\.s\.nt1 r4=\[r5\],r6 - 6c: 00 00 04 00 nop\.f 0x0 - 70: 0e 20 d0 0a 22 16 \[MMF\] ld1\.s\.nt1 r4=\[r5\],-204 + 6c: 00 00 00 20 nop\.b 0x0 + 70: 18 20 d0 0a 22 16 \[MMB\] ld1\.s\.nt1 r4=\[r5\],-204 76: 40 00 14 4c 20 00 ld1\.s\.nta r4=\[r5\] - 7c: 00 00 04 00 nop\.f 0x0 - 80: 0e 20 18 0a 26 12 \[MMF\] ld1\.s\.nta r4=\[r5\],r6 + 7c: 00 00 00 20 nop\.b 0x0 + 80: 18 20 18 0a 26 12 \[MMB\] ld1\.s\.nta r4=\[r5\],r6 86: 40 08 16 4c 2c 00 ld1\.s\.nta r4=\[r5\],-191 - 8c: 00 00 04 00 nop\.f 0x0 - 90: 0e 20 00 0a 40 10 \[MMF\] ld1\.a r4=\[r5\] + 8c: 00 00 00 20 nop\.b 0x0 + 90: 18 20 00 0a 40 10 \[MMB\] ld1\.a r4=\[r5\] 96: 40 30 14 80 24 00 ld1\.a r4=\[r5\],r6 - 9c: 00 00 04 00 nop\.f 0x0 - a0: 0e 20 38 0b 40 16 \[MMF\] ld1\.a r4=\[r5\],-178 + 9c: 00 00 00 20 nop\.b 0x0 + a0: 18 20 38 0b 40 16 \[MMB\] ld1\.a r4=\[r5\],-178 a6: 40 00 14 84 20 00 ld1\.a\.nt1 r4=\[r5\] - ac: 00 00 04 00 nop\.f 0x0 - b0: 0e 20 18 0a 42 12 \[MMF\] ld1\.a\.nt1 r4=\[r5\],r6 + ac: 00 00 00 20 nop\.b 0x0 + b0: 18 20 18 0a 42 12 \[MMB\] ld1\.a\.nt1 r4=\[r5\],r6 b6: 40 d8 16 84 2c 00 ld1\.a\.nt1 r4=\[r5\],-165 - bc: 00 00 04 00 nop\.f 0x0 - c0: 0e 20 00 0a 46 10 \[MMF\] ld1\.a\.nta r4=\[r5\] + bc: 00 00 00 20 nop\.b 0x0 + c0: 18 20 00 0a 46 10 \[MMB\] ld1\.a\.nta r4=\[r5\] c6: 40 30 14 8c 24 00 ld1\.a\.nta r4=\[r5\],r6 - cc: 00 00 04 00 nop\.f 0x0 - d0: 0e 20 a0 0b 46 16 \[MMF\] ld1\.a\.nta r4=\[r5\],-152 + cc: 00 00 00 20 nop\.b 0x0 + d0: 18 20 a0 0b 46 16 \[MMB\] ld1\.a\.nta r4=\[r5\],-152 d6: 40 00 14 c0 20 00 ld1\.sa r4=\[r5\] - dc: 00 00 04 00 nop\.f 0x0 - e0: 0e 20 18 0a 60 12 \[MMF\] ld1\.sa r4=\[r5\],r6 + dc: 00 00 00 20 nop\.b 0x0 + e0: 18 20 18 0a 60 12 \[MMB\] ld1\.sa r4=\[r5\],r6 e6: 40 a8 17 c0 2c 00 ld1\.sa r4=\[r5\],-139 - ec: 00 00 04 00 nop\.f 0x0 - f0: 0e 20 00 0a 62 10 \[MMF\] ld1\.sa\.nt1 r4=\[r5\] + ec: 00 00 00 20 nop\.b 0x0 + f0: 18 20 00 0a 62 10 \[MMB\] ld1\.sa\.nt1 r4=\[r5\] f6: 40 30 14 c4 24 00 ld1\.sa\.nt1 r4=\[r5\],r6 - fc: 00 00 04 00 nop\.f 0x0 - 100: 0e 20 08 0a 63 16 \[MMF\] ld1\.sa\.nt1 r4=\[r5\],-126 + fc: 00 00 00 20 nop\.b 0x0 + 100: 18 20 08 0a 63 16 \[MMB\] ld1\.sa\.nt1 r4=\[r5\],-126 106: 40 00 14 cc 20 00 ld1\.sa\.nta r4=\[r5\] - 10c: 00 00 04 00 nop\.f 0x0 - 110: 0e 20 18 0a 66 12 \[MMF\] ld1\.sa\.nta r4=\[r5\],r6 + 10c: 00 00 00 20 nop\.b 0x0 + 110: 18 20 18 0a 66 12 \[MMB\] ld1\.sa\.nta r4=\[r5\],r6 116: 40 78 14 ce 2c 00 ld1\.sa\.nta r4=\[r5\],-113 - 11c: 00 00 04 00 nop\.f 0x0 - 120: 0e 20 00 0a 00 11 \[MMF\] ld1\.c\.clr r4=\[r5\] + 11c: 00 00 00 20 nop\.b 0x0 + 120: 18 20 00 0a 00 11 \[MMB\] ld1\.c\.clr r4=\[r5\] 126: 40 30 14 00 26 00 ld1\.c\.clr r4=\[r5\],r6 - 12c: 00 00 04 00 nop\.f 0x0 - 130: 0e 20 70 0a 01 17 \[MMF\] ld1\.c\.clr r4=\[r5\],-100 + 12c: 00 00 00 20 nop\.b 0x0 + 130: 18 20 70 0a 01 17 \[MMB\] ld1\.c\.clr r4=\[r5\],-100 136: 40 00 14 04 22 00 ld1\.c\.clr\.nt1 r4=\[r5\] - 13c: 00 00 04 00 nop\.f 0x0 - 140: 0e 20 18 0a 02 13 \[MMF\] ld1\.c\.clr\.nt1 r4=\[r5\],r6 + 13c: 00 00 00 20 nop\.b 0x0 + 140: 18 20 18 0a 02 13 \[MMB\] ld1\.c\.clr\.nt1 r4=\[r5\],r6 146: 40 48 15 06 2e 00 ld1\.c\.clr\.nt1 r4=\[r5\],-87 - 14c: 00 00 04 00 nop\.f 0x0 - 150: 0e 20 00 0a 06 11 \[MMF\] ld1\.c\.clr\.nta r4=\[r5\] + 14c: 00 00 00 20 nop\.b 0x0 + 150: 18 20 00 0a 06 11 \[MMB\] ld1\.c\.clr\.nta r4=\[r5\] 156: 40 30 14 0c 26 00 ld1\.c\.clr\.nta r4=\[r5\],r6 - 15c: 00 00 04 00 nop\.f 0x0 - 160: 0e 20 d8 0a 07 17 \[MMF\] ld1\.c\.clr\.nta r4=\[r5\],-74 + 15c: 00 00 00 20 nop\.b 0x0 + 160: 18 20 d8 0a 07 17 \[MMB\] ld1\.c\.clr\.nta r4=\[r5\],-74 166: 40 00 14 40 22 00 ld1\.c\.nc r4=\[r5\] - 16c: 00 00 04 00 nop\.f 0x0 - 170: 0e 20 18 0a 20 13 \[MMF\] ld1\.c\.nc r4=\[r5\],r6 + 16c: 00 00 00 20 nop\.b 0x0 + 170: 18 20 18 0a 20 13 \[MMB\] ld1\.c\.nc r4=\[r5\],r6 176: 40 18 16 42 2e 00 ld1\.c\.nc r4=\[r5\],-61 - 17c: 00 00 04 00 nop\.f 0x0 - 180: 0e 20 00 0a 22 11 \[MMF\] ld1\.c\.nc\.nt1 r4=\[r5\] + 17c: 00 00 00 20 nop\.b 0x0 + 180: 18 20 00 0a 22 11 \[MMB\] ld1\.c\.nc\.nt1 r4=\[r5\] 186: 40 30 14 44 26 00 ld1\.c\.nc\.nt1 r4=\[r5\],r6 - 18c: 00 00 04 00 nop\.f 0x0 - 190: 0e 20 40 0b 23 17 \[MMF\] ld1\.c\.nc\.nt1 r4=\[r5\],-48 + 18c: 00 00 00 20 nop\.b 0x0 + 190: 18 20 40 0b 23 17 \[MMB\] ld1\.c\.nc\.nt1 r4=\[r5\],-48 196: 40 00 14 4c 22 00 ld1\.c\.nc\.nta r4=\[r5\] - 19c: 00 00 04 00 nop\.f 0x0 - 1a0: 0e 20 18 0a 26 13 \[MMF\] ld1\.c\.nc\.nta r4=\[r5\],r6 + 19c: 00 00 00 20 nop\.b 0x0 + 1a0: 18 20 18 0a 26 13 \[MMB\] ld1\.c\.nc\.nta r4=\[r5\],r6 1a6: 40 e8 16 4e 2e 00 ld1\.c\.nc\.nta r4=\[r5\],-35 - 1ac: 00 00 04 00 nop\.f 0x0 - 1b0: 0e 20 00 0a 80 10 \[MMF\] ld1\.bias r4=\[r5\] + 1ac: 00 00 00 20 nop\.b 0x0 + 1b0: 18 20 00 0a 80 10 \[MMB\] ld1\.bias r4=\[r5\] 1b6: 40 30 14 00 25 00 ld1\.bias r4=\[r5\],r6 - 1bc: 00 00 04 00 nop\.f 0x0 - 1c0: 0e 20 a8 0b 81 16 \[MMF\] ld1\.bias r4=\[r5\],-22 + 1bc: 00 00 00 20 nop\.b 0x0 + 1c0: 18 20 a8 0b 81 16 \[MMB\] ld1\.bias r4=\[r5\],-22 1c6: 40 00 14 04 21 00 ld1\.bias\.nt1 r4=\[r5\] - 1cc: 00 00 04 00 nop\.f 0x0 - 1d0: 0e 20 18 0a 82 12 \[MMF\] ld1\.bias\.nt1 r4=\[r5\],r6 + 1cc: 00 00 00 20 nop\.b 0x0 + 1d0: 18 20 18 0a 82 12 \[MMB\] ld1\.bias\.nt1 r4=\[r5\],r6 1d6: 40 b8 17 06 2d 00 ld1\.bias\.nt1 r4=\[r5\],-9 - 1dc: 00 00 04 00 nop\.f 0x0 - 1e0: 0e 20 00 0a 86 10 \[MMF\] ld1\.bias\.nta r4=\[r5\] + 1dc: 00 00 00 20 nop\.b 0x0 + 1e0: 18 20 00 0a 86 10 \[MMB\] ld1\.bias\.nta r4=\[r5\] 1e6: 40 30 14 0c 25 00 ld1\.bias\.nta r4=\[r5\],r6 - 1ec: 00 00 04 00 nop\.f 0x0 - 1f0: 0e 20 10 0a 86 14 \[MMF\] ld1\.bias\.nta r4=\[r5\],4 + 1ec: 00 00 00 20 nop\.b 0x0 + 1f0: 18 20 10 0a 86 14 \[MMB\] ld1\.bias\.nta r4=\[r5\],4 1f6: 40 00 14 40 21 00 ld1\.acq r4=\[r5\] - 1fc: 00 00 04 00 nop\.f 0x0 - 200: 0e 20 18 0a a0 12 \[MMF\] ld1\.acq r4=\[r5\],r6 + 1fc: 00 00 00 20 nop\.b 0x0 + 200: 18 20 18 0a a0 12 \[MMB\] ld1\.acq r4=\[r5\],r6 206: 40 88 14 40 29 00 ld1\.acq r4=\[r5\],17 - 20c: 00 00 04 00 nop\.f 0x0 - 210: 0e 20 00 0a a2 10 \[MMF\] ld1\.acq\.nt1 r4=\[r5\] + 20c: 00 00 00 20 nop\.b 0x0 + 210: 18 20 00 0a a2 10 \[MMB\] ld1\.acq\.nt1 r4=\[r5\] 216: 40 30 14 44 25 00 ld1\.acq\.nt1 r4=\[r5\],r6 - 21c: 00 00 04 00 nop\.f 0x0 - 220: 0e 20 78 0a a2 14 \[MMF\] ld1\.acq\.nt1 r4=\[r5\],30 + 21c: 00 00 00 20 nop\.b 0x0 + 220: 18 20 78 0a a2 14 \[MMB\] ld1\.acq\.nt1 r4=\[r5\],30 226: 40 00 14 4c 21 00 ld1\.acq\.nta r4=\[r5\] - 22c: 00 00 04 00 nop\.f 0x0 - 230: 0e 20 18 0a a6 12 \[MMF\] ld1\.acq\.nta r4=\[r5\],r6 + 22c: 00 00 00 20 nop\.b 0x0 + 230: 18 20 18 0a a6 12 \[MMB\] ld1\.acq\.nta r4=\[r5\],r6 236: 40 58 15 4c 29 00 ld1\.acq\.nta r4=\[r5\],43 - 23c: 00 00 04 00 nop\.f 0x0 - 240: 0e 20 00 0a 40 11 \[MMF\] ld1\.c\.clr\.acq r4=\[r5\] + 23c: 00 00 00 20 nop\.b 0x0 + 240: 18 20 00 0a 40 11 \[MMB\] ld1\.c\.clr\.acq r4=\[r5\] 246: 40 30 14 80 26 00 ld1\.c\.clr\.acq r4=\[r5\],r6 - 24c: 00 00 04 00 nop\.f 0x0 - 250: 0e 20 e0 0a 40 15 \[MMF\] ld1\.c\.clr\.acq r4=\[r5\],56 + 24c: 00 00 00 20 nop\.b 0x0 + 250: 18 20 e0 0a 40 15 \[MMB\] ld1\.c\.clr\.acq r4=\[r5\],56 256: 40 00 14 84 22 00 ld1\.c\.clr\.acq\.nt1 r4=\[r5\] - 25c: 00 00 04 00 nop\.f 0x0 - 260: 0e 20 18 0a 42 13 \[MMF\] ld1\.c\.clr\.acq\.nt1 r4=\[r5\],r6 + 25c: 00 00 00 20 nop\.b 0x0 + 260: 18 20 18 0a 42 13 \[MMB\] ld1\.c\.clr\.acq\.nt1 r4=\[r5\],r6 266: 40 28 16 84 2a 00 ld1\.c\.clr\.acq\.nt1 r4=\[r5\],69 - 26c: 00 00 04 00 nop\.f 0x0 - 270: 0e 20 00 0a 46 11 \[MMF\] ld1\.c\.clr\.acq\.nta r4=\[r5\] + 26c: 00 00 00 20 nop\.b 0x0 + 270: 18 20 00 0a 46 11 \[MMB\] ld1\.c\.clr\.acq\.nta r4=\[r5\] 276: 40 30 14 8c 26 00 ld1\.c\.clr\.acq\.nta r4=\[r5\],r6 - 27c: 00 00 04 00 nop\.f 0x0 - 280: 0e 20 48 0b 46 15 \[MMF\] ld1\.c\.clr\.acq\.nta r4=\[r5\],82 + 27c: 00 00 00 20 nop\.b 0x0 + 280: 18 20 48 0b 46 15 \[MMB\] ld1\.c\.clr\.acq\.nta r4=\[r5\],82 286: 40 00 14 10 20 00 ld2 r4=\[r5\] - 28c: 00 00 04 00 nop\.f 0x0 - 290: 0e 20 18 0a 08 12 \[MMF\] ld2 r4=\[r5\],r6 + 28c: 00 00 00 20 nop\.b 0x0 + 290: 18 20 18 0a 08 12 \[MMB\] ld2 r4=\[r5\],r6 296: 40 f8 16 10 28 00 ld2 r4=\[r5\],95 - 29c: 00 00 04 00 nop\.f 0x0 - 2a0: 0e 20 00 0a 0a 10 \[MMF\] ld2\.nt1 r4=\[r5\] + 29c: 00 00 00 20 nop\.b 0x0 + 2a0: 18 20 00 0a 0a 10 \[MMB\] ld2\.nt1 r4=\[r5\] 2a6: 40 30 14 14 24 00 ld2\.nt1 r4=\[r5\],r6 - 2ac: 00 00 04 00 nop\.f 0x0 - 2b0: 0e 20 b0 0b 0a 14 \[MMF\] ld2\.nt1 r4=\[r5\],108 + 2ac: 00 00 00 20 nop\.b 0x0 + 2b0: 18 20 b0 0b 0a 14 \[MMB\] ld2\.nt1 r4=\[r5\],108 2b6: 40 00 14 1c 20 00 ld2\.nta r4=\[r5\] - 2bc: 00 00 04 00 nop\.f 0x0 - 2c0: 0e 20 18 0a 0e 12 \[MMF\] ld2\.nta r4=\[r5\],r6 + 2bc: 00 00 00 20 nop\.b 0x0 + 2c0: 18 20 18 0a 0e 12 \[MMB\] ld2\.nta r4=\[r5\],r6 2c6: 40 c8 17 1c 28 00 ld2\.nta r4=\[r5\],121 - 2cc: 00 00 04 00 nop\.f 0x0 - 2d0: 0e 20 00 0a 28 10 \[MMF\] ld2\.s r4=\[r5\] + 2cc: 00 00 00 20 nop\.b 0x0 + 2d0: 18 20 00 0a 28 10 \[MMB\] ld2\.s r4=\[r5\] 2d6: 40 30 14 50 24 00 ld2\.s r4=\[r5\],r6 - 2dc: 00 00 04 00 nop\.f 0x0 - 2e0: 0e 20 18 0a 29 14 \[MMF\] ld2\.s r4=\[r5\],134 + 2dc: 00 00 00 20 nop\.b 0x0 + 2e0: 18 20 18 0a 29 14 \[MMB\] ld2\.s r4=\[r5\],134 2e6: 40 00 14 54 20 00 ld2\.s\.nt1 r4=\[r5\] - 2ec: 00 00 04 00 nop\.f 0x0 - 2f0: 0e 20 18 0a 2a 12 \[MMF\] ld2\.s\.nt1 r4=\[r5\],r6 + 2ec: 00 00 00 20 nop\.b 0x0 + 2f0: 18 20 18 0a 2a 12 \[MMB\] ld2\.s\.nt1 r4=\[r5\],r6 2f6: 40 98 14 56 28 00 ld2\.s\.nt1 r4=\[r5\],147 - 2fc: 00 00 04 00 nop\.f 0x0 - 300: 0e 20 00 0a 2e 10 \[MMF\] ld2\.s\.nta r4=\[r5\] + 2fc: 00 00 00 20 nop\.b 0x0 + 300: 18 20 00 0a 2e 10 \[MMB\] ld2\.s\.nta r4=\[r5\] 306: 40 30 14 5c 24 00 ld2\.s\.nta r4=\[r5\],r6 - 30c: 00 00 04 00 nop\.f 0x0 - 310: 0e 20 80 0a 2f 14 \[MMF\] ld2\.s\.nta r4=\[r5\],160 + 30c: 00 00 00 20 nop\.b 0x0 + 310: 18 20 80 0a 2f 14 \[MMB\] ld2\.s\.nta r4=\[r5\],160 316: 40 00 14 90 20 00 ld2\.a r4=\[r5\] - 31c: 00 00 04 00 nop\.f 0x0 - 320: 0e 20 18 0a 48 12 \[MMF\] ld2\.a r4=\[r5\],r6 + 31c: 00 00 00 20 nop\.b 0x0 + 320: 18 20 18 0a 48 12 \[MMB\] ld2\.a r4=\[r5\],r6 326: 40 68 15 92 28 00 ld2\.a r4=\[r5\],173 - 32c: 00 00 04 00 nop\.f 0x0 - 330: 0e 20 00 0a 4a 10 \[MMF\] ld2\.a\.nt1 r4=\[r5\] + 32c: 00 00 00 20 nop\.b 0x0 + 330: 18 20 00 0a 4a 10 \[MMB\] ld2\.a\.nt1 r4=\[r5\] 336: 40 30 14 94 24 00 ld2\.a\.nt1 r4=\[r5\],r6 - 33c: 00 00 04 00 nop\.f 0x0 - 340: 0e 20 e8 0a 4b 14 \[MMF\] ld2\.a\.nt1 r4=\[r5\],186 + 33c: 00 00 00 20 nop\.b 0x0 + 340: 18 20 e8 0a 4b 14 \[MMB\] ld2\.a\.nt1 r4=\[r5\],186 346: 40 00 14 9c 20 00 ld2\.a\.nta r4=\[r5\] - 34c: 00 00 04 00 nop\.f 0x0 - 350: 0e 20 18 0a 4e 12 \[MMF\] ld2\.a\.nta r4=\[r5\],r6 + 34c: 00 00 00 20 nop\.b 0x0 + 350: 18 20 18 0a 4e 12 \[MMB\] ld2\.a\.nta r4=\[r5\],r6 356: 40 38 16 9e 28 00 ld2\.a\.nta r4=\[r5\],199 - 35c: 00 00 04 00 nop\.f 0x0 - 360: 0e 20 00 0a 68 10 \[MMF\] ld2\.sa r4=\[r5\] + 35c: 00 00 00 20 nop\.b 0x0 + 360: 18 20 00 0a 68 10 \[MMB\] ld2\.sa r4=\[r5\] 366: 40 30 14 d0 24 00 ld2\.sa r4=\[r5\],r6 - 36c: 00 00 04 00 nop\.f 0x0 - 370: 0e 20 50 0b 69 14 \[MMF\] ld2\.sa r4=\[r5\],212 + 36c: 00 00 00 20 nop\.b 0x0 + 370: 18 20 50 0b 69 14 \[MMB\] ld2\.sa r4=\[r5\],212 376: 40 00 14 d4 20 00 ld2\.sa\.nt1 r4=\[r5\] - 37c: 00 00 04 00 nop\.f 0x0 - 380: 0e 20 18 0a 6a 12 \[MMF\] ld2\.sa\.nt1 r4=\[r5\],r6 + 37c: 00 00 00 20 nop\.b 0x0 + 380: 18 20 18 0a 6a 12 \[MMB\] ld2\.sa\.nt1 r4=\[r5\],r6 386: 40 08 17 d6 28 00 ld2\.sa\.nt1 r4=\[r5\],225 - 38c: 00 00 04 00 nop\.f 0x0 - 390: 0e 20 00 0a 6e 10 \[MMF\] ld2\.sa\.nta r4=\[r5\] + 38c: 00 00 00 20 nop\.b 0x0 + 390: 18 20 00 0a 6e 10 \[MMB\] ld2\.sa\.nta r4=\[r5\] 396: 40 30 14 dc 24 00 ld2\.sa\.nta r4=\[r5\],r6 - 39c: 00 00 04 00 nop\.f 0x0 - 3a0: 0e 20 b8 0b 6f 14 \[MMF\] ld2\.sa\.nta r4=\[r5\],238 + 39c: 00 00 00 20 nop\.b 0x0 + 3a0: 18 20 b8 0b 6f 14 \[MMB\] ld2\.sa\.nta r4=\[r5\],238 3a6: 40 00 14 10 22 00 ld2\.c\.clr r4=\[r5\] - 3ac: 00 00 04 00 nop\.f 0x0 - 3b0: 0e 20 18 0a 08 13 \[MMF\] ld2\.c\.clr r4=\[r5\],r6 + 3ac: 00 00 00 20 nop\.b 0x0 + 3b0: 18 20 18 0a 08 13 \[MMB\] ld2\.c\.clr r4=\[r5\],r6 3b6: 40 d8 17 12 2a 00 ld2\.c\.clr r4=\[r5\],251 - 3bc: 00 00 04 00 nop\.f 0x0 - 3c0: 0e 20 00 0a 0a 11 \[MMF\] ld2\.c\.clr\.nt1 r4=\[r5\] + 3bc: 00 00 00 20 nop\.b 0x0 + 3c0: 18 20 00 0a 0a 11 \[MMB\] ld2\.c\.clr\.nt1 r4=\[r5\] 3c6: 40 30 14 14 26 00 ld2\.c\.clr\.nt1 r4=\[r5\],r6 - 3cc: 00 00 04 00 nop\.f 0x0 - 3d0: 0e 20 20 0a 0a 17 \[MMF\] ld2\.c\.clr\.nt1 r4=\[r5\],-248 + 3cc: 00 00 00 20 nop\.b 0x0 + 3d0: 18 20 20 0a 0a 17 \[MMB\] ld2\.c\.clr\.nt1 r4=\[r5\],-248 3d6: 40 00 14 1c 22 00 ld2\.c\.clr\.nta r4=\[r5\] - 3dc: 00 00 04 00 nop\.f 0x0 - 3e0: 0e 20 18 0a 0e 13 \[MMF\] ld2\.c\.clr\.nta r4=\[r5\],r6 + 3dc: 00 00 00 20 nop\.b 0x0 + 3e0: 18 20 18 0a 0e 13 \[MMB\] ld2\.c\.clr\.nta r4=\[r5\],r6 3e6: 40 a8 14 1c 2e 00 ld2\.c\.clr\.nta r4=\[r5\],-235 - 3ec: 00 00 04 00 nop\.f 0x0 - 3f0: 0e 20 00 0a 28 11 \[MMF\] ld2\.c\.nc r4=\[r5\] + 3ec: 00 00 00 20 nop\.b 0x0 + 3f0: 18 20 00 0a 28 11 \[MMB\] ld2\.c\.nc r4=\[r5\] 3f6: 40 30 14 50 26 00 ld2\.c\.nc r4=\[r5\],r6 - 3fc: 00 00 04 00 nop\.f 0x0 - 400: 0e 20 88 0a 28 17 \[MMF\] ld2\.c\.nc r4=\[r5\],-222 + 3fc: 00 00 00 20 nop\.b 0x0 + 400: 18 20 88 0a 28 17 \[MMB\] ld2\.c\.nc r4=\[r5\],-222 406: 40 00 14 54 22 00 ld2\.c\.nc\.nt1 r4=\[r5\] - 40c: 00 00 04 00 nop\.f 0x0 - 410: 0e 20 18 0a 2a 13 \[MMF\] ld2\.c\.nc\.nt1 r4=\[r5\],r6 + 40c: 00 00 00 20 nop\.b 0x0 + 410: 18 20 18 0a 2a 13 \[MMB\] ld2\.c\.nc\.nt1 r4=\[r5\],r6 416: 40 78 15 54 2e 00 ld2\.c\.nc\.nt1 r4=\[r5\],-209 - 41c: 00 00 04 00 nop\.f 0x0 - 420: 0e 20 00 0a 2e 11 \[MMF\] ld2\.c\.nc\.nta r4=\[r5\] + 41c: 00 00 00 20 nop\.b 0x0 + 420: 18 20 00 0a 2e 11 \[MMB\] ld2\.c\.nc\.nta r4=\[r5\] 426: 40 30 14 5c 26 00 ld2\.c\.nc\.nta r4=\[r5\],r6 - 42c: 00 00 04 00 nop\.f 0x0 - 430: 0e 20 f0 0a 2e 17 \[MMF\] ld2\.c\.nc\.nta r4=\[r5\],-196 + 42c: 00 00 00 20 nop\.b 0x0 + 430: 18 20 f0 0a 2e 17 \[MMB\] ld2\.c\.nc\.nta r4=\[r5\],-196 436: 40 00 14 10 21 00 ld2\.bias r4=\[r5\] - 43c: 00 00 04 00 nop\.f 0x0 - 440: 0e 20 18 0a 88 12 \[MMF\] ld2\.bias r4=\[r5\],r6 + 43c: 00 00 00 20 nop\.b 0x0 + 440: 18 20 18 0a 88 12 \[MMB\] ld2\.bias r4=\[r5\],r6 446: 40 48 16 10 2d 00 ld2\.bias r4=\[r5\],-183 - 44c: 00 00 04 00 nop\.f 0x0 - 450: 0e 20 00 0a 8a 10 \[MMF\] ld2\.bias\.nt1 r4=\[r5\] + 44c: 00 00 00 20 nop\.b 0x0 + 450: 18 20 00 0a 8a 10 \[MMB\] ld2\.bias\.nt1 r4=\[r5\] 456: 40 30 14 14 25 00 ld2\.bias\.nt1 r4=\[r5\],r6 - 45c: 00 00 04 00 nop\.f 0x0 - 460: 0e 20 58 0b 8a 16 \[MMF\] ld2\.bias\.nt1 r4=\[r5\],-170 + 45c: 00 00 00 20 nop\.b 0x0 + 460: 18 20 58 0b 8a 16 \[MMB\] ld2\.bias\.nt1 r4=\[r5\],-170 466: 40 00 14 1c 21 00 ld2\.bias\.nta r4=\[r5\] - 46c: 00 00 04 00 nop\.f 0x0 - 470: 0e 20 18 0a 8e 12 \[MMF\] ld2\.bias\.nta r4=\[r5\],r6 + 46c: 00 00 00 20 nop\.b 0x0 + 470: 18 20 18 0a 8e 12 \[MMB\] ld2\.bias\.nta r4=\[r5\],r6 476: 40 18 17 1c 2d 00 ld2\.bias\.nta r4=\[r5\],-157 - 47c: 00 00 04 00 nop\.f 0x0 - 480: 0e 20 00 0a a8 10 \[MMF\] ld2\.acq r4=\[r5\] + 47c: 00 00 00 20 nop\.b 0x0 + 480: 18 20 00 0a a8 10 \[MMB\] ld2\.acq r4=\[r5\] 486: 40 30 14 50 25 00 ld2\.acq r4=\[r5\],r6 - 48c: 00 00 04 00 nop\.f 0x0 - 490: 0e 20 c0 0b a8 16 \[MMF\] ld2\.acq r4=\[r5\],-144 + 48c: 00 00 00 20 nop\.b 0x0 + 490: 18 20 c0 0b a8 16 \[MMB\] ld2\.acq r4=\[r5\],-144 496: 40 00 14 54 21 00 ld2\.acq\.nt1 r4=\[r5\] - 49c: 00 00 04 00 nop\.f 0x0 - 4a0: 0e 20 18 0a aa 12 \[MMF\] ld2\.acq\.nt1 r4=\[r5\],r6 + 49c: 00 00 00 20 nop\.b 0x0 + 4a0: 18 20 18 0a aa 12 \[MMB\] ld2\.acq\.nt1 r4=\[r5\],r6 4a6: 40 e8 17 54 2d 00 ld2\.acq\.nt1 r4=\[r5\],-131 - 4ac: 00 00 04 00 nop\.f 0x0 - 4b0: 0e 20 00 0a ae 10 \[MMF\] ld2\.acq\.nta r4=\[r5\] + 4ac: 00 00 00 20 nop\.b 0x0 + 4b0: 18 20 00 0a ae 10 \[MMB\] ld2\.acq\.nta r4=\[r5\] 4b6: 40 30 14 5c 25 00 ld2\.acq\.nta r4=\[r5\],r6 - 4bc: 00 00 04 00 nop\.f 0x0 - 4c0: 0e 20 28 0a af 16 \[MMF\] ld2\.acq\.nta r4=\[r5\],-118 + 4bc: 00 00 00 20 nop\.b 0x0 + 4c0: 18 20 28 0a af 16 \[MMB\] ld2\.acq\.nta r4=\[r5\],-118 4c6: 40 00 14 90 22 00 ld2\.c\.clr\.acq r4=\[r5\] - 4cc: 00 00 04 00 nop\.f 0x0 - 4d0: 0e 20 18 0a 48 13 \[MMF\] ld2\.c\.clr\.acq r4=\[r5\],r6 + 4cc: 00 00 00 20 nop\.b 0x0 + 4d0: 18 20 18 0a 48 13 \[MMB\] ld2\.c\.clr\.acq r4=\[r5\],r6 4d6: 40 b8 14 92 2e 00 ld2\.c\.clr\.acq r4=\[r5\],-105 - 4dc: 00 00 04 00 nop\.f 0x0 - 4e0: 0e 20 00 0a 4a 11 \[MMF\] ld2\.c\.clr\.acq\.nt1 r4=\[r5\] + 4dc: 00 00 00 20 nop\.b 0x0 + 4e0: 18 20 00 0a 4a 11 \[MMB\] ld2\.c\.clr\.acq\.nt1 r4=\[r5\] 4e6: 40 30 14 94 26 00 ld2\.c\.clr\.acq\.nt1 r4=\[r5\],r6 - 4ec: 00 00 04 00 nop\.f 0x0 - 4f0: 0e 20 90 0a 4b 17 \[MMF\] ld2\.c\.clr\.acq\.nt1 r4=\[r5\],-92 + 4ec: 00 00 00 20 nop\.b 0x0 + 4f0: 18 20 90 0a 4b 17 \[MMB\] ld2\.c\.clr\.acq\.nt1 r4=\[r5\],-92 4f6: 40 00 14 9c 22 00 ld2\.c\.clr\.acq\.nta r4=\[r5\] - 4fc: 00 00 04 00 nop\.f 0x0 - 500: 0e 20 18 0a 4e 13 \[MMF\] ld2\.c\.clr\.acq\.nta r4=\[r5\],r6 + 4fc: 00 00 00 20 nop\.b 0x0 + 500: 18 20 18 0a 4e 13 \[MMB\] ld2\.c\.clr\.acq\.nta r4=\[r5\],r6 506: 40 88 15 9e 2e 00 ld2\.c\.clr\.acq\.nta r4=\[r5\],-79 - 50c: 00 00 04 00 nop\.f 0x0 - 510: 0e 20 00 0a 10 10 \[MMF\] ld4 r4=\[r5\] + 50c: 00 00 00 20 nop\.b 0x0 + 510: 18 20 00 0a 10 10 \[MMB\] ld4 r4=\[r5\] 516: 40 30 14 20 24 00 ld4 r4=\[r5\],r6 - 51c: 00 00 04 00 nop\.f 0x0 - 520: 0e 20 f8 0a 11 16 \[MMF\] ld4 r4=\[r5\],-66 + 51c: 00 00 00 20 nop\.b 0x0 + 520: 18 20 f8 0a 11 16 \[MMB\] ld4 r4=\[r5\],-66 526: 40 00 14 24 20 00 ld4\.nt1 r4=\[r5\] - 52c: 00 00 04 00 nop\.f 0x0 - 530: 0e 20 18 0a 12 12 \[MMF\] ld4\.nt1 r4=\[r5\],r6 + 52c: 00 00 00 20 nop\.b 0x0 + 530: 18 20 18 0a 12 12 \[MMB\] ld4\.nt1 r4=\[r5\],r6 536: 40 58 16 26 2c 00 ld4\.nt1 r4=\[r5\],-53 - 53c: 00 00 04 00 nop\.f 0x0 - 540: 0e 20 00 0a 16 10 \[MMF\] ld4\.nta r4=\[r5\] + 53c: 00 00 00 20 nop\.b 0x0 + 540: 18 20 00 0a 16 10 \[MMB\] ld4\.nta r4=\[r5\] 546: 40 30 14 2c 24 00 ld4\.nta r4=\[r5\],r6 - 54c: 00 00 04 00 nop\.f 0x0 - 550: 0e 20 60 0b 17 16 \[MMF\] ld4\.nta r4=\[r5\],-40 + 54c: 00 00 00 20 nop\.b 0x0 + 550: 18 20 60 0b 17 16 \[MMB\] ld4\.nta r4=\[r5\],-40 556: 40 00 14 60 20 00 ld4\.s r4=\[r5\] - 55c: 00 00 04 00 nop\.f 0x0 - 560: 0e 20 18 0a 30 12 \[MMF\] ld4\.s r4=\[r5\],r6 + 55c: 00 00 00 20 nop\.b 0x0 + 560: 18 20 18 0a 30 12 \[MMB\] ld4\.s r4=\[r5\],r6 566: 40 28 17 62 2c 00 ld4\.s r4=\[r5\],-27 - 56c: 00 00 04 00 nop\.f 0x0 - 570: 0e 20 00 0a 32 10 \[MMF\] ld4\.s\.nt1 r4=\[r5\] + 56c: 00 00 00 20 nop\.b 0x0 + 570: 18 20 00 0a 32 10 \[MMB\] ld4\.s\.nt1 r4=\[r5\] 576: 40 30 14 64 24 00 ld4\.s\.nt1 r4=\[r5\],r6 - 57c: 00 00 04 00 nop\.f 0x0 - 580: 0e 20 c8 0b 33 16 \[MMF\] ld4\.s\.nt1 r4=\[r5\],-14 + 57c: 00 00 00 20 nop\.b 0x0 + 580: 18 20 c8 0b 33 16 \[MMB\] ld4\.s\.nt1 r4=\[r5\],-14 586: 40 00 14 6c 20 00 ld4\.s\.nta r4=\[r5\] - 58c: 00 00 04 00 nop\.f 0x0 - 590: 0e 20 18 0a 36 12 \[MMF\] ld4\.s\.nta r4=\[r5\],r6 + 58c: 00 00 00 20 nop\.b 0x0 + 590: 18 20 18 0a 36 12 \[MMB\] ld4\.s\.nta r4=\[r5\],r6 596: 40 f8 17 6e 2c 00 ld4\.s\.nta r4=\[r5\],-1 - 59c: 00 00 04 00 nop\.f 0x0 - 5a0: 0e 20 00 0a 50 10 \[MMF\] ld4\.a r4=\[r5\] + 59c: 00 00 00 20 nop\.b 0x0 + 5a0: 18 20 00 0a 50 10 \[MMB\] ld4\.a r4=\[r5\] 5a6: 40 30 14 a0 24 00 ld4\.a r4=\[r5\],r6 - 5ac: 00 00 04 00 nop\.f 0x0 - 5b0: 0e 20 30 0a 50 14 \[MMF\] ld4\.a r4=\[r5\],12 + 5ac: 00 00 00 20 nop\.b 0x0 + 5b0: 18 20 30 0a 50 14 \[MMB\] ld4\.a r4=\[r5\],12 5b6: 40 00 14 a4 20 00 ld4\.a\.nt1 r4=\[r5\] - 5bc: 00 00 04 00 nop\.f 0x0 - 5c0: 0e 20 18 0a 52 12 \[MMF\] ld4\.a\.nt1 r4=\[r5\],r6 + 5bc: 00 00 00 20 nop\.b 0x0 + 5c0: 18 20 18 0a 52 12 \[MMB\] ld4\.a\.nt1 r4=\[r5\],r6 5c6: 40 c8 14 a4 28 00 ld4\.a\.nt1 r4=\[r5\],25 - 5cc: 00 00 04 00 nop\.f 0x0 - 5d0: 0e 20 00 0a 56 10 \[MMF\] ld4\.a\.nta r4=\[r5\] + 5cc: 00 00 00 20 nop\.b 0x0 + 5d0: 18 20 00 0a 56 10 \[MMB\] ld4\.a\.nta r4=\[r5\] 5d6: 40 30 14 ac 24 00 ld4\.a\.nta r4=\[r5\],r6 - 5dc: 00 00 04 00 nop\.f 0x0 - 5e0: 0e 20 98 0a 56 14 \[MMF\] ld4\.a\.nta r4=\[r5\],38 + 5dc: 00 00 00 20 nop\.b 0x0 + 5e0: 18 20 98 0a 56 14 \[MMB\] ld4\.a\.nta r4=\[r5\],38 5e6: 40 00 14 e0 20 00 ld4\.sa r4=\[r5\] - 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dbc: 00 00 04 00 nop\.f 0x0 - dc0: 0e 20 e0 0a 3f 1c \[MMF\] ldfd\.s\.nta f4=\[r5\],184 + dbc: 00 00 00 20 nop\.b 0x0 + dc0: 18 20 e0 0a 3f 1c \[MMB\] ldfd\.s\.nta f4=\[r5\],184 dc6: 40 00 14 b0 30 00 ldfd\.a f4=\[r5\] - dcc: 00 00 04 00 nop\.f 0x0 - dd0: 0e 20 18 0a 58 1a \[MMF\] ldfd\.a f4=\[r5\],r6 + dcc: 00 00 00 20 nop\.b 0x0 + dd0: 18 20 18 0a 58 1a \[MMB\] ldfd\.a f4=\[r5\],r6 dd6: 40 28 16 b2 38 00 ldfd\.a f4=\[r5\],197 - ddc: 00 00 04 00 nop\.f 0x0 - de0: 0e 20 00 0a 5a 18 \[MMF\] ldfd\.a\.nt1 f4=\[r5\] + ddc: 00 00 00 20 nop\.b 0x0 + de0: 18 20 00 0a 5a 18 \[MMB\] ldfd\.a\.nt1 f4=\[r5\] de6: 40 30 14 b4 34 00 ldfd\.a\.nt1 f4=\[r5\],r6 - dec: 00 00 04 00 nop\.f 0x0 - df0: 0e 20 48 0b 5b 1c \[MMF\] ldfd\.a\.nt1 f4=\[r5\],210 + dec: 00 00 00 20 nop\.b 0x0 + df0: 18 20 48 0b 5b 1c \[MMB\] ldfd\.a\.nt1 f4=\[r5\],210 df6: 40 00 14 bc 30 00 ldfd\.a\.nta f4=\[r5\] - dfc: 00 00 04 00 nop\.f 0x0 - e00: 0e 20 18 0a 5e 1a \[MMF\] ldfd\.a\.nta f4=\[r5\],r6 + dfc: 00 00 00 20 nop\.b 0x0 + e00: 18 20 18 0a 5e 1a \[MMB\] ldfd\.a\.nta f4=\[r5\],r6 e06: 40 f8 16 be 38 00 ldfd\.a\.nta f4=\[r5\],223 - e0c: 00 00 04 00 nop\.f 0x0 - e10: 0e 20 00 0a 78 18 \[MMF\] ldfd\.sa f4=\[r5\] + e0c: 00 00 00 20 nop\.b 0x0 + e10: 18 20 00 0a 78 18 \[MMB\] ldfd\.sa f4=\[r5\] e16: 40 30 14 f0 34 00 ldfd\.sa f4=\[r5\],r6 - e1c: 00 00 04 00 nop\.f 0x0 - e20: 0e 20 b0 0b 79 1c \[MMF\] ldfd\.sa f4=\[r5\],236 + e1c: 00 00 00 20 nop\.b 0x0 + e20: 18 20 b0 0b 79 1c \[MMB\] ldfd\.sa f4=\[r5\],236 e26: 40 00 14 f4 30 00 ldfd\.sa\.nt1 f4=\[r5\] - e2c: 00 00 04 00 nop\.f 0x0 - e30: 0e 20 18 0a 7a 1a \[MMF\] ldfd\.sa\.nt1 f4=\[r5\],r6 + e2c: 00 00 00 20 nop\.b 0x0 + e30: 18 20 18 0a 7a 1a \[MMB\] ldfd\.sa\.nt1 f4=\[r5\],r6 e36: 40 c8 17 f6 38 00 ldfd\.sa\.nt1 f4=\[r5\],249 - e3c: 00 00 04 00 nop\.f 0x0 - e40: 0e 20 00 0a 7e 18 \[MMF\] ldfd\.sa\.nta f4=\[r5\] + e3c: 00 00 00 20 nop\.b 0x0 + e40: 18 20 00 0a 7e 18 \[MMB\] ldfd\.sa\.nta f4=\[r5\] e46: 40 30 14 fc 34 00 ldfd\.sa\.nta f4=\[r5\],r6 - e4c: 00 00 04 00 nop\.f 0x0 - e50: 0e 20 18 0a 7e 1e \[MMF\] ldfd\.sa\.nta f4=\[r5\],-250 + e4c: 00 00 00 20 nop\.b 0x0 + e50: 18 20 18 0a 7e 1e \[MMB\] ldfd\.sa\.nta f4=\[r5\],-250 e56: 40 00 14 30 32 00 ldfd\.c\.clr f4=\[r5\] - e5c: 00 00 04 00 nop\.f 0x0 - e60: 0e 20 18 0a 18 1b \[MMF\] ldfd\.c\.clr f4=\[r5\],r6 + e5c: 00 00 00 20 nop\.b 0x0 + e60: 18 20 18 0a 18 1b \[MMB\] ldfd\.c\.clr f4=\[r5\],r6 e66: 40 98 14 30 3e 00 ldfd\.c\.clr f4=\[r5\],-237 - e6c: 00 00 04 00 nop\.f 0x0 - e70: 0e 20 00 0a 1a 19 \[MMF\] ldfd\.c\.clr\.nt1 f4=\[r5\] + e6c: 00 00 00 20 nop\.b 0x0 + e70: 18 20 00 0a 1a 19 \[MMB\] ldfd\.c\.clr\.nt1 f4=\[r5\] e76: 40 30 14 34 36 00 ldfd\.c\.clr\.nt1 f4=\[r5\],r6 - e7c: 00 00 04 00 nop\.f 0x0 - e80: 0e 20 80 0a 1a 1f \[MMF\] ldfd\.c\.clr\.nt1 f4=\[r5\],-224 + e7c: 00 00 00 20 nop\.b 0x0 + e80: 18 20 80 0a 1a 1f \[MMB\] ldfd\.c\.clr\.nt1 f4=\[r5\],-224 e86: 40 00 14 3c 32 00 ldfd\.c\.clr\.nta f4=\[r5\] - e8c: 00 00 04 00 nop\.f 0x0 - e90: 0e 20 18 0a 1e 1b \[MMF\] ldfd\.c\.clr\.nta f4=\[r5\],r6 + e8c: 00 00 00 20 nop\.b 0x0 + e90: 18 20 18 0a 1e 1b \[MMB\] ldfd\.c\.clr\.nta f4=\[r5\],r6 e96: 40 68 15 3c 3e 00 ldfd\.c\.clr\.nta f4=\[r5\],-211 - e9c: 00 00 04 00 nop\.f 0x0 - ea0: 0e 20 00 0a 38 19 \[MMF\] ldfd\.c\.nc f4=\[r5\] + e9c: 00 00 00 20 nop\.b 0x0 + ea0: 18 20 00 0a 38 19 \[MMB\] ldfd\.c\.nc f4=\[r5\] ea6: 40 30 14 70 36 00 ldfd\.c\.nc f4=\[r5\],r6 - eac: 00 00 04 00 nop\.f 0x0 - eb0: 0e 20 e8 0a 38 1f \[MMF\] ldfd\.c\.nc f4=\[r5\],-198 + eac: 00 00 00 20 nop\.b 0x0 + eb0: 18 20 e8 0a 38 1f \[MMB\] ldfd\.c\.nc f4=\[r5\],-198 eb6: 40 00 14 74 32 00 ldfd\.c\.nc\.nt1 f4=\[r5\] - ebc: 00 00 04 00 nop\.f 0x0 - ec0: 0e 20 18 0a 3a 1b \[MMF\] ldfd\.c\.nc\.nt1 f4=\[r5\],r6 + ebc: 00 00 00 20 nop\.b 0x0 + ec0: 18 20 18 0a 3a 1b \[MMB\] ldfd\.c\.nc\.nt1 f4=\[r5\],r6 ec6: 40 38 16 74 3e 00 ldfd\.c\.nc\.nt1 f4=\[r5\],-185 - ecc: 00 00 04 00 nop\.f 0x0 - ed0: 0e 20 00 0a 3e 19 \[MMF\] ldfd\.c\.nc\.nta f4=\[r5\] + ecc: 00 00 00 20 nop\.b 0x0 + ed0: 18 20 00 0a 3e 19 \[MMB\] ldfd\.c\.nc\.nta f4=\[r5\] ed6: 40 30 14 7c 36 00 ldfd\.c\.nc\.nta f4=\[r5\],r6 - edc: 00 00 04 00 nop\.f 0x0 - ee0: 0e 20 50 0b 3e 1f \[MMF\] ldfd\.c\.nc\.nta f4=\[r5\],-172 + edc: 00 00 00 20 nop\.b 0x0 + ee0: 18 20 50 0b 3e 1f \[MMB\] ldfd\.c\.nc\.nta f4=\[r5\],-172 ee6: 40 00 14 10 30 00 ldf8 f4=\[r5\] - eec: 00 00 04 00 nop\.f 0x0 - ef0: 0e 20 18 0a 08 1a \[MMF\] ldf8 f4=\[r5\],r6 + eec: 00 00 00 20 nop\.b 0x0 + ef0: 18 20 18 0a 08 1a \[MMB\] ldf8 f4=\[r5\],r6 ef6: 40 08 17 10 3c 00 ldf8 f4=\[r5\],-159 - efc: 00 00 04 00 nop\.f 0x0 - f00: 0e 20 00 0a 0a 18 \[MMF\] ldf8\.nt1 f4=\[r5\] + efc: 00 00 00 20 nop\.b 0x0 + f00: 18 20 00 0a 0a 18 \[MMB\] ldf8\.nt1 f4=\[r5\] f06: 40 30 14 14 34 00 ldf8\.nt1 f4=\[r5\],r6 - f0c: 00 00 04 00 nop\.f 0x0 - f10: 0e 20 b8 0b 0a 1e \[MMF\] ldf8\.nt1 f4=\[r5\],-146 + f0c: 00 00 00 20 nop\.b 0x0 + f10: 18 20 b8 0b 0a 1e \[MMB\] ldf8\.nt1 f4=\[r5\],-146 f16: 40 00 14 1c 30 00 ldf8\.nta f4=\[r5\] - f1c: 00 00 04 00 nop\.f 0x0 - f20: 0e 20 18 0a 0e 1a \[MMF\] ldf8\.nta f4=\[r5\],r6 + f1c: 00 00 00 20 nop\.b 0x0 + f20: 18 20 18 0a 0e 1a \[MMB\] ldf8\.nta f4=\[r5\],r6 f26: 40 d8 17 1c 3c 00 ldf8\.nta f4=\[r5\],-133 - f2c: 00 00 04 00 nop\.f 0x0 - f30: 0e 20 00 0a 28 18 \[MMF\] ldf8\.s f4=\[r5\] + f2c: 00 00 00 20 nop\.b 0x0 + f30: 18 20 00 0a 28 18 \[MMB\] ldf8\.s f4=\[r5\] f36: 40 30 14 50 34 00 ldf8\.s f4=\[r5\],r6 - f3c: 00 00 04 00 nop\.f 0x0 - f40: 0e 20 20 0a 29 1e \[MMF\] ldf8\.s f4=\[r5\],-120 + f3c: 00 00 00 20 nop\.b 0x0 + f40: 18 20 20 0a 29 1e \[MMB\] ldf8\.s f4=\[r5\],-120 f46: 40 00 14 54 30 00 ldf8\.s\.nt1 f4=\[r5\] - f4c: 00 00 04 00 nop\.f 0x0 - f50: 0e 20 18 0a 2a 1a \[MMF\] ldf8\.s\.nt1 f4=\[r5\],r6 + f4c: 00 00 00 20 nop\.b 0x0 + f50: 18 20 18 0a 2a 1a \[MMB\] ldf8\.s\.nt1 f4=\[r5\],r6 f56: 40 a8 14 56 3c 00 ldf8\.s\.nt1 f4=\[r5\],-107 - f5c: 00 00 04 00 nop\.f 0x0 - f60: 0e 20 00 0a 2e 18 \[MMF\] ldf8\.s\.nta f4=\[r5\] + f5c: 00 00 00 20 nop\.b 0x0 + f60: 18 20 00 0a 2e 18 \[MMB\] ldf8\.s\.nta f4=\[r5\] f66: 40 30 14 5c 34 00 ldf8\.s\.nta f4=\[r5\],r6 - f6c: 00 00 04 00 nop\.f 0x0 - f70: 0e 20 88 0a 2f 1e \[MMF\] ldf8\.s\.nta f4=\[r5\],-94 + f6c: 00 00 00 20 nop\.b 0x0 + f70: 18 20 88 0a 2f 1e \[MMB\] ldf8\.s\.nta f4=\[r5\],-94 f76: 40 00 14 90 30 00 ldf8\.a f4=\[r5\] - f7c: 00 00 04 00 nop\.f 0x0 - f80: 0e 20 18 0a 48 1a \[MMF\] ldf8\.a f4=\[r5\],r6 + f7c: 00 00 00 20 nop\.b 0x0 + f80: 18 20 18 0a 48 1a \[MMB\] ldf8\.a f4=\[r5\],r6 f86: 40 78 15 92 3c 00 ldf8\.a f4=\[r5\],-81 - f8c: 00 00 04 00 nop\.f 0x0 - f90: 0e 20 00 0a 4a 18 \[MMF\] ldf8\.a\.nt1 f4=\[r5\] + f8c: 00 00 00 20 nop\.b 0x0 + f90: 18 20 00 0a 4a 18 \[MMB\] ldf8\.a\.nt1 f4=\[r5\] f96: 40 30 14 94 34 00 ldf8\.a\.nt1 f4=\[r5\],r6 - f9c: 00 00 04 00 nop\.f 0x0 - fa0: 0e 20 f0 0a 4b 1e \[MMF\] ldf8\.a\.nt1 f4=\[r5\],-68 + f9c: 00 00 00 20 nop\.b 0x0 + fa0: 18 20 f0 0a 4b 1e \[MMB\] ldf8\.a\.nt1 f4=\[r5\],-68 fa6: 40 00 14 9c 30 00 ldf8\.a\.nta f4=\[r5\] - fac: 00 00 04 00 nop\.f 0x0 - fb0: 0e 20 18 0a 4e 1a \[MMF\] ldf8\.a\.nta f4=\[r5\],r6 + fac: 00 00 00 20 nop\.b 0x0 + fb0: 18 20 18 0a 4e 1a \[MMB\] ldf8\.a\.nta f4=\[r5\],r6 fb6: 40 48 16 9e 3c 00 ldf8\.a\.nta f4=\[r5\],-55 - fbc: 00 00 04 00 nop\.f 0x0 - fc0: 0e 20 00 0a 68 18 \[MMF\] ldf8\.sa f4=\[r5\] + fbc: 00 00 00 20 nop\.b 0x0 + fc0: 18 20 00 0a 68 18 \[MMB\] ldf8\.sa f4=\[r5\] fc6: 40 30 14 d0 34 00 ldf8\.sa f4=\[r5\],r6 - fcc: 00 00 04 00 nop\.f 0x0 - fd0: 0e 20 58 0b 69 1e \[MMF\] ldf8\.sa f4=\[r5\],-42 + fcc: 00 00 00 20 nop\.b 0x0 + fd0: 18 20 58 0b 69 1e \[MMB\] ldf8\.sa f4=\[r5\],-42 fd6: 40 00 14 d4 30 00 ldf8\.sa\.nt1 f4=\[r5\] - fdc: 00 00 04 00 nop\.f 0x0 - fe0: 0e 20 18 0a 6a 1a \[MMF\] ldf8\.sa\.nt1 f4=\[r5\],r6 + fdc: 00 00 00 20 nop\.b 0x0 + fe0: 18 20 18 0a 6a 1a \[MMB\] ldf8\.sa\.nt1 f4=\[r5\],r6 fe6: 40 18 17 d6 3c 00 ldf8\.sa\.nt1 f4=\[r5\],-29 - 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16ec: 00 00 04 00 nop\.f 0x0 - 16f0: 0e 00 00 08 70 19 \[MMF\] lfetch\.fault \[r4\] + 16ec: 00 00 00 20 nop\.b 0x0 + 16f0: 18 00 00 08 70 19 \[MMB\] lfetch\.fault \[r4\] 16f6: 00 28 10 e0 36 00 lfetch\.fault \[r4\],r5 - 16fc: 00 00 04 00 nop\.f 0x0 - 1700: 0e 00 48 08 70 1d \[MMF\] lfetch\.fault \[r4\],18 + 16fc: 00 00 00 20 nop\.b 0x0 + 1700: 18 00 48 08 70 1d \[MMB\] lfetch\.fault \[r4\],18 1706: 00 00 10 e4 32 00 lfetch\.fault\.nt1 \[r4\] - 170c: 00 00 04 00 nop\.f 0x0 - 1710: 0e 00 14 08 72 1b \[MMF\] lfetch\.fault\.nt1 \[r4\],r5 + 170c: 00 00 00 20 nop\.b 0x0 + 1710: 18 00 14 08 72 1b \[MMB\] lfetch\.fault\.nt1 \[r4\],r5 1716: 00 f8 10 e4 3a 00 lfetch\.fault\.nt1 \[r4\],31 - 171c: 00 00 04 00 nop\.f 0x0 - 1720: 0e 00 00 08 74 19 \[MMF\] lfetch\.fault\.nt2 \[r4\] + 171c: 00 00 00 20 nop\.b 0x0 + 1720: 18 00 00 08 74 19 \[MMB\] lfetch\.fault\.nt2 \[r4\] 1726: 00 28 10 e8 36 00 lfetch\.fault\.nt2 \[r4\],r5 - 172c: 00 00 04 00 nop\.f 0x0 - 1730: 0e 00 b0 08 74 1d \[MMF\] lfetch\.fault\.nt2 \[r4\],44 + 172c: 00 00 00 20 nop\.b 0x0 + 1730: 18 00 b0 08 74 1d \[MMB\] lfetch\.fault\.nt2 \[r4\],44 1736: 00 00 10 ec 32 00 lfetch\.fault\.nta \[r4\] - 173c: 00 00 04 00 nop\.f 0x0 - 1740: 0e 00 14 08 76 1b \[MMF\] lfetch\.fault\.nta \[r4\],r5 + 173c: 00 00 00 20 nop\.b 0x0 + 1740: 18 00 14 08 76 1b \[MMB\] lfetch\.fault\.nta \[r4\],r5 1746: 00 c8 11 ec 3a 00 lfetch\.fault\.nta \[r4\],57 - 174c: 00 00 04 00 nop\.f 0x0 - 1750: 0e 00 00 08 68 19 \[MMF\] lfetch\.excl \[r4\] + 174c: 00 00 00 20 nop\.b 0x0 + 1750: 18 00 00 08 68 19 \[MMB\] lfetch\.excl \[r4\] 1756: 00 28 10 d0 36 00 lfetch\.excl \[r4\],r5 - 175c: 00 00 04 00 nop\.f 0x0 - 1760: 0e 00 18 09 68 1d \[MMF\] lfetch\.excl \[r4\],70 + 175c: 00 00 00 20 nop\.b 0x0 + 1760: 18 00 18 09 68 1d \[MMB\] lfetch\.excl \[r4\],70 1766: 00 00 10 d4 32 00 lfetch\.excl\.nt1 \[r4\] - 176c: 00 00 04 00 nop\.f 0x0 - 1770: 0e 00 14 08 6a 1b \[MMF\] lfetch\.excl\.nt1 \[r4\],r5 + 176c: 00 00 00 20 nop\.b 0x0 + 1770: 18 00 14 08 6a 1b \[MMB\] lfetch\.excl\.nt1 \[r4\],r5 1776: 00 98 12 d4 3a 00 lfetch\.excl\.nt1 \[r4\],83 - 177c: 00 00 04 00 nop\.f 0x0 - 1780: 0e 00 00 08 6c 19 \[MMF\] lfetch\.excl\.nt2 \[r4\] + 177c: 00 00 00 20 nop\.b 0x0 + 1780: 18 00 00 08 6c 19 \[MMB\] lfetch\.excl\.nt2 \[r4\] 1786: 00 28 10 d8 36 00 lfetch\.excl\.nt2 \[r4\],r5 - 178c: 00 00 04 00 nop\.f 0x0 - 1790: 0e 00 80 09 6c 1d \[MMF\] lfetch\.excl\.nt2 \[r4\],96 + 178c: 00 00 00 20 nop\.b 0x0 + 1790: 18 00 80 09 6c 1d \[MMB\] lfetch\.excl\.nt2 \[r4\],96 1796: 00 00 10 dc 32 00 lfetch\.excl\.nta \[r4\] - 179c: 00 00 04 00 nop\.f 0x0 - 17a0: 0e 00 14 08 6e 1b \[MMF\] lfetch\.excl\.nta \[r4\],r5 + 179c: 00 00 00 20 nop\.b 0x0 + 17a0: 18 00 14 08 6e 1b \[MMB\] lfetch\.excl\.nta \[r4\],r5 17a6: 00 68 13 dc 3a 00 lfetch\.excl\.nta \[r4\],109 - 17ac: 00 00 04 00 nop\.f 0x0 - 17b0: 0e 00 00 08 78 19 \[MMF\] lfetch\.fault\.excl \[r4\] + 17ac: 00 00 00 20 nop\.b 0x0 + 17b0: 18 00 00 08 78 19 \[MMB\] lfetch\.fault\.excl \[r4\] 17b6: 00 28 10 f0 36 00 lfetch\.fault\.excl \[r4\],r5 - 17bc: 00 00 04 00 nop\.f 0x0 - 17c0: 0e 00 e8 09 78 1d \[MMF\] lfetch\.fault\.excl \[r4\],122 + 17bc: 00 00 00 20 nop\.b 0x0 + 17c0: 18 00 e8 09 78 1d \[MMB\] lfetch\.fault\.excl \[r4\],122 17c6: 00 00 10 f4 32 00 lfetch\.fault\.excl\.nt1 \[r4\] - 17cc: 00 00 04 00 nop\.f 0x0 - 17d0: 0e 00 14 08 7a 1b \[MMF\] lfetch\.fault\.excl\.nt1 \[r4\],r5 + 17cc: 00 00 00 20 nop\.b 0x0 + 17d0: 18 00 14 08 7a 1b \[MMB\] lfetch\.fault\.excl\.nt1 \[r4\],r5 17d6: 00 38 10 f6 3a 00 lfetch\.fault\.excl\.nt1 \[r4\],135 - 17dc: 00 00 04 00 nop\.f 0x0 - 17e0: 0e 00 00 08 7c 19 \[MMF\] lfetch\.fault\.excl\.nt2 \[r4\] + 17dc: 00 00 00 20 nop\.b 0x0 + 17e0: 18 00 00 08 7c 19 \[MMB\] lfetch\.fault\.excl\.nt2 \[r4\] 17e6: 00 28 10 f8 36 00 lfetch\.fault\.excl\.nt2 \[r4\],r5 - 17ec: 00 00 04 00 nop\.f 0x0 - 17f0: 0e 00 50 08 7d 1d \[MMF\] lfetch\.fault\.excl\.nt2 \[r4\],148 + 17ec: 00 00 00 20 nop\.b 0x0 + 17f0: 18 00 50 08 7d 1d \[MMB\] lfetch\.fault\.excl\.nt2 \[r4\],148 17f6: 00 00 10 fc 32 00 lfetch\.fault\.excl\.nta \[r4\] - 17fc: 00 00 04 00 nop\.f 0x0 - 1800: 0e 00 14 08 7e 1b \[MMF\] lfetch\.fault\.excl\.nta \[r4\],r5 + 17fc: 00 00 00 20 nop\.b 0x0 + 1800: 18 00 14 08 7e 1b \[MMB\] lfetch\.fault\.excl\.nta \[r4\],r5 1806: 00 08 11 fe 3a 00 lfetch\.fault\.excl\.nta \[r4\],161 - 180c: 00 00 04 00 nop\.f 0x0 - 1810: 0e 20 18 0a 01 10 \[MMF\] cmpxchg1\.acq r4=\[r5\],r6,ar\.ccv + 180c: 00 00 00 20 nop\.b 0x0 + 1810: 18 20 18 0a 01 10 \[MMB\] cmpxchg1\.acq r4=\[r5\],r6,ar\.ccv 1816: 40 30 14 06 20 00 cmpxchg1\.acq\.nt1 r4=\[r5\],r6,ar\.ccv - 181c: 00 00 04 00 nop\.f 0x0 - 1820: 0e 20 18 0a 07 10 \[MMF\] cmpxchg1\.acq\.nta r4=\[r5\],r6,ar\.ccv + 181c: 00 00 00 20 nop\.b 0x0 + 1820: 18 20 18 0a 07 10 \[MMB\] cmpxchg1\.acq\.nta r4=\[r5\],r6,ar\.ccv 1826: 40 30 14 42 20 00 cmpxchg1\.rel r4=\[r5\],r6,ar\.ccv - 182c: 00 00 04 00 nop\.f 0x0 - 1830: 0e 20 18 0a 23 10 \[MMF\] cmpxchg1\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 182c: 00 00 00 20 nop\.b 0x0 + 1830: 18 20 18 0a 23 10 \[MMB\] cmpxchg1\.rel\.nt1 r4=\[r5\],r6,ar\.ccv 1836: 40 30 14 4e 20 00 cmpxchg1\.rel\.nta r4=\[r5\],r6,ar\.ccv - 183c: 00 00 04 00 nop\.f 0x0 - 1840: 0e 20 18 0a 09 10 \[MMF\] cmpxchg2\.acq r4=\[r5\],r6,ar\.ccv + 183c: 00 00 00 20 nop\.b 0x0 + 1840: 18 20 18 0a 09 10 \[MMB\] cmpxchg2\.acq r4=\[r5\],r6,ar\.ccv 1846: 40 30 14 16 20 00 cmpxchg2\.acq\.nt1 r4=\[r5\],r6,ar\.ccv - 184c: 00 00 04 00 nop\.f 0x0 - 1850: 0e 20 18 0a 0f 10 \[MMF\] cmpxchg2\.acq\.nta r4=\[r5\],r6,ar\.ccv + 184c: 00 00 00 20 nop\.b 0x0 + 1850: 18 20 18 0a 0f 10 \[MMB\] cmpxchg2\.acq\.nta r4=\[r5\],r6,ar\.ccv 1856: 40 30 14 52 20 00 cmpxchg2\.rel r4=\[r5\],r6,ar\.ccv - 185c: 00 00 04 00 nop\.f 0x0 - 1860: 0e 20 18 0a 2b 10 \[MMF\] cmpxchg2\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 185c: 00 00 00 20 nop\.b 0x0 + 1860: 18 20 18 0a 2b 10 \[MMB\] cmpxchg2\.rel\.nt1 r4=\[r5\],r6,ar\.ccv 1866: 40 30 14 5e 20 00 cmpxchg2\.rel\.nta r4=\[r5\],r6,ar\.ccv - 186c: 00 00 04 00 nop\.f 0x0 - 1870: 0e 20 18 0a 11 10 \[MMF\] cmpxchg4\.acq r4=\[r5\],r6,ar\.ccv + 186c: 00 00 00 20 nop\.b 0x0 + 1870: 18 20 18 0a 11 10 \[MMB\] cmpxchg4\.acq r4=\[r5\],r6,ar\.ccv 1876: 40 30 14 26 20 00 cmpxchg4\.acq\.nt1 r4=\[r5\],r6,ar\.ccv - 187c: 00 00 04 00 nop\.f 0x0 - 1880: 0e 20 18 0a 17 10 \[MMF\] cmpxchg4\.acq\.nta r4=\[r5\],r6,ar\.ccv + 187c: 00 00 00 20 nop\.b 0x0 + 1880: 18 20 18 0a 17 10 \[MMB\] cmpxchg4\.acq\.nta r4=\[r5\],r6,ar\.ccv 1886: 40 30 14 62 20 00 cmpxchg4\.rel r4=\[r5\],r6,ar\.ccv - 188c: 00 00 04 00 nop\.f 0x0 - 1890: 0e 20 18 0a 33 10 \[MMF\] cmpxchg4\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 188c: 00 00 00 20 nop\.b 0x0 + 1890: 18 20 18 0a 33 10 \[MMB\] cmpxchg4\.rel\.nt1 r4=\[r5\],r6,ar\.ccv 1896: 40 30 14 6e 20 00 cmpxchg4\.rel\.nta r4=\[r5\],r6,ar\.ccv - 189c: 00 00 04 00 nop\.f 0x0 - 18a0: 0e 20 18 0a 19 10 \[MMF\] cmpxchg8\.acq r4=\[r5\],r6,ar\.ccv + 189c: 00 00 00 20 nop\.b 0x0 + 18a0: 18 20 18 0a 19 10 \[MMB\] cmpxchg8\.acq r4=\[r5\],r6,ar\.ccv 18a6: 40 30 14 36 20 00 cmpxchg8\.acq\.nt1 r4=\[r5\],r6,ar\.ccv - 18ac: 00 00 04 00 nop\.f 0x0 - 18b0: 0e 20 18 0a 1f 10 \[MMF\] cmpxchg8\.acq\.nta r4=\[r5\],r6,ar\.ccv + 18ac: 00 00 00 20 nop\.b 0x0 + 18b0: 18 20 18 0a 1f 10 \[MMB\] cmpxchg8\.acq\.nta r4=\[r5\],r6,ar\.ccv 18b6: 40 30 14 72 20 00 cmpxchg8\.rel r4=\[r5\],r6,ar\.ccv - 18bc: 00 00 04 00 nop\.f 0x0 - 18c0: 0e 20 18 0a 3b 10 \[MMF\] cmpxchg8\.rel\.nt1 r4=\[r5\],r6,ar\.ccv + 18bc: 00 00 00 20 nop\.b 0x0 + 18c0: 18 20 18 0a 3b 10 \[MMB\] cmpxchg8\.rel\.nt1 r4=\[r5\],r6,ar\.ccv 18c6: 40 30 14 7e 20 00 cmpxchg8\.rel\.nta r4=\[r5\],r6,ar\.ccv - 18cc: 00 00 04 00 nop\.f 0x0 - 18d0: 0e 20 18 0a 41 10 \[MMF\] xchg1 r4=\[r5\],r6 + 18cc: 00 00 00 20 nop\.b 0x0 + 18d0: 18 20 18 0a 41 10 \[MMB\] xchg1 r4=\[r5\],r6 18d6: 40 30 14 86 20 00 xchg1\.nt1 r4=\[r5\],r6 - 18dc: 00 00 04 00 nop\.f 0x0 - 18e0: 0e 20 18 0a 47 10 \[MMF\] xchg1\.nta r4=\[r5\],r6 + 18dc: 00 00 00 20 nop\.b 0x0 + 18e0: 18 20 18 0a 47 10 \[MMB\] xchg1\.nta r4=\[r5\],r6 18e6: 40 30 14 92 20 00 xchg2 r4=\[r5\],r6 - 18ec: 00 00 04 00 nop\.f 0x0 - 18f0: 0e 20 18 0a 4b 10 \[MMF\] xchg2\.nt1 r4=\[r5\],r6 + 18ec: 00 00 00 20 nop\.b 0x0 + 18f0: 18 20 18 0a 4b 10 \[MMB\] xchg2\.nt1 r4=\[r5\],r6 18f6: 40 30 14 9e 20 00 xchg2\.nta r4=\[r5\],r6 - 18fc: 00 00 04 00 nop\.f 0x0 - 1900: 0e 20 18 0a 51 10 \[MMF\] xchg4 r4=\[r5\],r6 + 18fc: 00 00 00 20 nop\.b 0x0 + 1900: 18 20 18 0a 51 10 \[MMB\] xchg4 r4=\[r5\],r6 1906: 40 30 14 a6 20 00 xchg4\.nt1 r4=\[r5\],r6 - 190c: 00 00 04 00 nop\.f 0x0 - 1910: 0e 20 18 0a 57 10 \[MMF\] xchg4\.nta r4=\[r5\],r6 + 190c: 00 00 00 20 nop\.b 0x0 + 1910: 18 20 18 0a 57 10 \[MMB\] xchg4\.nta r4=\[r5\],r6 1916: 40 30 14 b2 20 00 xchg8 r4=\[r5\],r6 - 191c: 00 00 04 00 nop\.f 0x0 - 1920: 0e 20 18 0a 5b 10 \[MMF\] xchg8\.nt1 r4=\[r5\],r6 + 191c: 00 00 00 20 nop\.b 0x0 + 1920: 18 20 18 0a 5b 10 \[MMB\] xchg8\.nt1 r4=\[r5\],r6 1926: 40 30 14 be 20 00 xchg8\.nta r4=\[r5\],r6 - 192c: 00 00 04 00 nop\.f 0x0 - 1930: 0e 20 10 0a 91 10 \[MMF\] fetchadd4\.acq r4=\[r5\],-16 + 192c: 00 00 00 20 nop\.b 0x0 + 1930: 18 20 10 0a 91 10 \[MMB\] fetchadd4\.acq r4=\[r5\],-16 1936: 40 28 14 26 21 00 fetchadd4\.acq\.nt1 r4=\[r5\],-8 - 193c: 00 00 04 00 nop\.f 0x0 - 1940: 0e 20 18 0a 97 10 \[MMF\] fetchadd4\.acq\.nta r4=\[r5\],-4 + 193c: 00 00 00 20 nop\.b 0x0 + 1940: 18 20 18 0a 97 10 \[MMB\] fetchadd4\.acq\.nta r4=\[r5\],-4 1946: 40 38 14 32 21 00 fetchadd8\.acq r4=\[r5\],-1 - 194c: 00 00 04 00 nop\.f 0x0 - 1950: 0e 20 0c 0a 9b 10 \[MMF\] fetchadd8\.acq\.nt1 r4=\[r5\],1 + 194c: 00 00 00 20 nop\.b 0x0 + 1950: 18 20 0c 0a 9b 10 \[MMB\] fetchadd8\.acq\.nt1 r4=\[r5\],1 1956: 40 10 14 3e 21 00 fetchadd8\.acq\.nta r4=\[r5\],4 - 195c: 00 00 04 00 nop\.f 0x0 - 1960: 0e 20 04 0a b1 10 \[MMF\] fetchadd4\.rel r4=\[r5\],8 + 195c: 00 00 00 20 nop\.b 0x0 + 1960: 18 20 04 0a b1 10 \[MMB\] fetchadd4\.rel r4=\[r5\],8 1966: 40 00 14 66 21 00 fetchadd4\.rel\.nt1 r4=\[r5\],16 - 196c: 00 00 04 00 nop\.f 0x0 - 1970: 0e 20 10 0a b7 10 \[MMF\] fetchadd4\.rel\.nta r4=\[r5\],-16 + 196c: 00 00 00 20 nop\.b 0x0 + 1970: 18 20 10 0a b7 10 \[MMB\] fetchadd4\.rel\.nta r4=\[r5\],-16 1976: 40 28 14 72 21 00 fetchadd8\.rel r4=\[r5\],-8 - 197c: 00 00 04 00 nop\.f 0x0 - 1980: 0e 20 18 0a bb 10 \[MMF\] fetchadd8\.rel\.nt1 r4=\[r5\],-4 + 197c: 00 00 00 20 nop\.b 0x0 + 1980: 18 20 18 0a bb 10 \[MMB\] fetchadd8\.rel\.nt1 r4=\[r5\],-4 1986: 40 38 14 7e 21 00 fetchadd8\.rel\.nta r4=\[r5\],-1 - 198c: 00 00 04 00 nop\.f 0x0 - 1990: 0e 20 14 00 e1 18 \[MMF\] setf\.sig f4=r5 + 198c: 00 00 00 20 nop\.b 0x0 + 1990: 18 20 14 00 e1 18 \[MMB\] setf\.sig f4=r5 1996: 40 28 00 d2 31 00 setf\.exp f4=r5 - 199c: 00 00 04 00 nop\.f 0x0 - 19a0: 0e 20 14 00 f1 18 \[MMF\] setf\.s f4=r5 + 199c: 00 00 00 20 nop\.b 0x0 + 19a0: 18 20 14 00 f1 18 \[MMB\] setf\.s f4=r5 19a6: 40 28 00 f2 31 00 setf\.d f4=r5 - 19ac: 00 00 04 00 nop\.f 0x0 - 19b0: 0e 20 14 00 e1 10 \[MMF\] getf\.sig r4=f5 + 19ac: 00 00 00 20 nop\.b 0x0 + 19b0: 18 20 14 00 e1 10 \[MMB\] getf\.sig r4=f5 19b6: 40 28 00 d2 21 00 getf\.exp r4=f5 - 19bc: 00 00 04 00 nop\.f 0x0 - 19c0: 0e 20 14 00 f1 10 \[MMF\] getf\.s r4=f5 + 19bc: 00 00 00 20 nop\.b 0x0 + 19c0: 18 20 14 00 f1 10 \[MMB\] getf\.s r4=f5 19c6: 40 28 00 f2 21 00 getf\.d r4=f5 - 19cc: 00 00 04 00 nop\.f 0x0 - 19d0: 0e 18 13 f8 7f 06 \[MMF\] chk\.s\.m r4,0 <_start> + 19cc: 00 00 00 20 nop\.b 0x0 + 19d0: 18 18 13 f8 7f 06 \[MMB\] chk\.s\.m r4,0 <_start> 19d6: 30 26 f0 ff 0d 00 chk\.s f4,0 <_start> - 19dc: 00 00 04 00 nop\.f 0x0 - 19e0: 0e 20 88 f9 3f 03 \[MMF\] chk\.a\.nc r4,0 <_start> + 19dc: 00 00 00 20 nop\.b 0x0 + 19e0: 18 20 88 f9 3f 03 \[MMB\] chk\.a\.nc r4,0 <_start> 19e6: 40 10 f3 ff 06 00 chk\.a\.clr r4,0 <_start> - 19ec: 00 00 04 00 nop\.f 0x0 - 19f0: 0e 20 84 f9 bf 03 \[MMF\] chk\.a\.nc f4,0 <_start> + 19ec: 00 00 00 20 nop\.b 0x0 + 19f0: 18 20 84 f9 bf 03 \[MMB\] chk\.a\.nc f4,0 <_start> 19f6: 40 08 f3 ff 07 00 chk\.a\.clr f4,0 <_start> - 19fc: 00 00 04 00 nop\.f 0x0 - 1a00: 0e 00 00 00 10 00 \[MMF\] invala + 19fc: 00 00 00 20 nop\.b 0x0 + 1a00: 18 00 00 00 10 00 \[MMB\] invala 1a06: 00 00 00 40 00 00 fwb - 1a0c: 00 00 04 00 nop\.f 0x0 - 1a10: 0e 00 00 00 22 00 \[MMF\] mf + 1a0c: 00 00 00 20 nop\.b 0x0 + 1a10: 18 00 00 00 22 00 \[MMB\] mf 1a16: 00 00 00 46 00 00 mf\.a - 1a1c: 00 00 04 00 nop\.f 0x0 - 1a20: 0e 00 00 00 30 00 \[MMF\] srlz\.d + 1a1c: 00 00 00 20 nop\.b 0x0 + 1a20: 18 00 00 00 30 00 \[MMB\] srlz\.d 1a26: 00 00 00 62 00 00 srlz\.i - 1a2c: 00 00 04 00 nop\.f 0x0 + 1a2c: 00 00 00 20 nop\.b 0x0 1a30: 09 00 00 00 33 00 \[MMI\] sync\.i 1a36: 00 00 00 02 00 00 nop\.m 0x0 1a3c: 00 00 04 00 nop\.i 0x0;; @@ -1275,54 +1275,54 @@ Disassembly of section \.text: 1a60: 00 00 00 00 0a 00 \[MII\] loadrs 1a66: 00 00 00 02 00 00 nop\.i 0x0 1a6c: 00 00 04 00 nop\.i 0x0 - 1a70: 0e 20 00 00 12 00 \[MMF\] invala\.e r4 + 1a70: 18 20 00 00 12 00 \[MMB\] invala\.e r4 1a76: 40 00 00 26 00 00 invala\.e f4 - 1a7c: 00 00 04 00 nop\.f 0x0 - 1a80: 0e 00 00 08 30 04 \[MMF\] fc r4 + 1a7c: 00 00 00 20 nop\.b 0x0 + 1a80: 18 00 00 08 30 04 \[MMB\] fc r4 1a86: 00 00 10 68 08 00 ptc\.e r4 - 1a8c: 00 00 04 00 nop\.f 0x0 - 1a90: 0e 00 00 00 00 00 \[MMF\] break\.m 0x0 + 1a8c: 00 00 00 20 nop\.b 0x0 + 1a90: 18 00 00 00 00 00 \[MMB\] break\.m 0x0 1a96: f0 ff 1f 00 00 00 break\.m 0x1ffff - 1a9c: 00 00 04 00 nop\.f 0x0 - 1aa0: 0e 00 00 00 01 00 \[MMF\] nop\.m 0x0 + 1a9c: 00 00 00 20 nop\.b 0x0 + 1aa0: 18 00 00 00 01 00 \[MMB\] nop\.m 0x0 1aa6: f0 ff 1f 00 00 00 break\.m 0x1ffff - 1aac: 00 00 04 00 nop\.f 0x0 - 1ab0: 0e 20 18 0a 38 04 \[MMF\] probe\.r r4=r5,r6 + 1aac: 00 00 00 20 nop\.b 0x0 + 1ab0: 18 20 18 0a 38 04 \[MMB\] probe\.r r4=r5,r6 1ab6: 40 30 14 72 08 00 probe\.w r4=r5,r6 - 1abc: 00 00 04 00 nop\.f 0x0 - 1ac0: 0e 20 00 0a 18 04 \[MMF\] probe\.r r4=r5,0 + 1abc: 00 00 00 20 nop\.b 0x0 + 1ac0: 18 20 00 0a 18 04 \[MMB\] probe\.r r4=r5,0 1ac6: 40 08 14 32 08 00 probe\.w r4=r5,1 - 1acc: 00 00 04 00 nop\.f 0x0 - 1ad0: 0e 00 08 06 32 04 \[MMF\] probe\.r\.fault r3,2 + 1acc: 00 00 00 20 nop\.b 0x0 + 1ad0: 18 00 08 06 32 04 \[MMB\] probe\.r\.fault r3,2 1ad6: 00 18 0c 66 08 00 probe\.w\.fault r3,3 - 1adc: 00 00 04 00 nop\.f 0x0 - 1ae0: 0e 00 00 06 31 04 \[MMF\] probe\.rw\.fault r3,0 + 1adc: 00 00 00 20 nop\.b 0x0 + 1ae0: 18 00 00 06 31 04 \[MMB\] probe\.rw\.fault r3,0 1ae6: 00 00 00 02 00 00 nop\.m 0x0 - 1aec: 00 00 04 00 nop\.f 0x0 + 1aec: 00 00 00 20 nop\.b 0x0 1af0: 0b 00 20 00 2e 04 \[MMI\] itc\.d r8;; 1af6: 00 00 00 02 00 00 nop\.m 0x0 1afc: 00 00 04 00 nop\.i 0x0;; 1b00: 0a 00 24 00 2f 04 \[MMI\] itc\.i r9;; 1b06: 40 23 01 08 00 00 sum 0x1234 1b0c: 00 00 04 00 nop\.i 0x0 - 1b10: 0e 50 55 d5 25 00 \[MMF\] rum 0x5aaaaa + 1b10: 18 50 55 d5 25 00 \[MMB\] rum 0x5aaaaa 1b16: f0 ff ff 6d 04 00 ssm 0xffffff - 1b1c: 00 00 04 00 nop\.f 0x0 - 1b20: 0e 00 00 00 27 00 \[MMF\] rsm 0x400000 + 1b1c: 00 00 00 20 nop\.b 0x0 + 1b20: 18 00 00 00 27 00 \[MMB\] rsm 0x400000 1b26: 00 28 10 12 08 00 ptc\.l r4,r5 - 1b2c: 00 00 04 00 nop\.f 0x0 + 1b2c: 00 00 00 20 nop\.b 0x0 1b30: 0a 00 14 08 0a 04 \[MMI\] ptc\.g r4,r5;; 1b36: 00 00 00 02 00 00 nop\.m 0x0 1b3c: 00 00 04 00 nop\.i 0x0 1b40: 0a 00 14 08 0b 04 \[MMI\] ptc\.ga r4,r5;; 1b46: 00 00 00 02 00 00 nop\.m 0x0 1b4c: 00 00 04 00 nop\.i 0x0 - 1b50: 0e 00 14 08 0c 04 \[MMF\] ptr\.d r4,r5 + 1b50: 18 00 14 08 0c 04 \[MMB\] ptr\.d r4,r5 1b56: 00 28 10 1a 08 00 ptr\.i r4,r5 - 1b5c: 00 00 04 00 nop\.f 0x0 - 1b60: 0e 20 00 0a 1a 04 \[MMF\] thash r4=r5 + 1b5c: 00 00 00 20 nop\.b 0x0 + 1b60: 18 20 00 0a 1a 04 \[MMB\] thash r4=r5 1b66: 40 00 14 36 08 00 ttag r4=r5 - 1b6c: 00 00 04 00 nop\.f 0x0 - 1b70: 0f 20 00 0a 1e 04 \[MMF\] tpa r4=r5 + 1b6c: 00 00 00 20 nop\.b 0x0 + 1b70: 19 20 00 0a 1e 04 \[MMB\] tpa r4=r5 1b76: 40 00 14 3e 08 00 tak r4=r5 - 1b7c: 00 00 04 00 nop\.f 0x0;; + 1b7c: 00 00 00 20 nop\.b 0x0;; diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a2af556..b84bcfd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,15 @@ +2000-12-12 Jim Wilson <wilson@redhat.com> + + * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode + argument. + * ia64_gen.c (insert_deplist): Cast sizeof result to int. + (print_dependency_table): Print NULL if semantics field not set. + (insert_opcode_dependencies): Mark cmp parameter as unused. + (print_main_table): Use fprintf_vma to print long long fields. + (main): Mark argv paramter as unused. Convert to old style definition. + * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int. + * ia64-asmtab.c: Regnerate. + 2000-12-09 Nick Clifton <nickc@redhat.com> * m32r-dis.c (print_insn): Prevent re-read of instruction from diff --git a/opcodes/ia64-asmtab.c b/opcodes/ia64-asmtab.c index d08119d..e37e791 100644 --- a/opcodes/ia64-asmtab.c +++ b/opcodes/ia64-asmtab.c @@ -36,323 +36,323 @@ static const char *ia64_strings[] = { static const struct ia64_dependency dependencies[] = { - { "ALAT", 0, 0, 0, -1, }, - { "AR[BSP]", 26, 0, 2, 17, }, - { "AR[BSPSTORE]", 26, 0, 2, 18, }, - { "AR[CCV]", 26, 0, 2, 32, }, - { "AR[EC]", 26, 0, 2, 66, }, - { "AR[FPSR].sf0.controls", 30, 0, 2, -1, }, - { "AR[FPSR].sf1.controls", 30, 0, 2, -1, }, - { "AR[FPSR].sf2.controls", 30, 0, 2, -1, }, - { "AR[FPSR].sf3.controls", 30, 0, 2, -1, }, - { "AR[FPSR].sf0.flags", 30, 0, 2, -1, }, - { "AR[FPSR].sf1.flags", 30, 0, 2, -1, }, - { "AR[FPSR].sf2.flags", 30, 0, 2, -1, }, - { "AR[FPSR].sf3.flags", 30, 0, 2, -1, }, - { "AR[FPSR].traps", 30, 0, 2, -1, }, - { "AR[FPSR].rv", 30, 0, 2, -1, }, - { "AR[ITC]", 26, 0, 2, 44, }, - { "AR[K%], % in 0 - 7", 1, 0, 2, -1, }, - { "AR[LC]", 26, 0, 2, 65, }, - { "AR[PFS]", 26, 0, 2, 64, }, - { "AR[PFS]", 26, 0, 2, 64, }, - { "AR[PFS]", 26, 0, 0, 64, }, - { "AR[RNAT]", 26, 0, 2, 19, }, - { "AR[RSC]", 26, 0, 2, 16, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, }, - { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, }, - { "BR%, % in 0 - 7", 5, 0, 0, -1, }, - { "BR%, % in 0 - 7", 5, 0, 2, -1, }, - { "CFM", 6, 0, 2, -1, }, - { "CFM", 6, 0, 2, -1, }, - { "CFM", 6, 0, 2, -1, }, - { "CFM", 6, 0, 2, -1, }, - { "CFM", 6, 0, 0, -1, }, - { "CPUID#", 7, 0, 5, -1, }, - { "CR[CMCV]", 27, 0, 3, 74, }, - { "CR[DCR]", 27, 0, 3, 0, }, + { "ALAT", 0, 0, 0, -1, NULL, }, + { "AR[BSP]", 26, 0, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, + { "AR[CCV]", 26, 0, 2, 32, NULL, }, + { "AR[EC]", 26, 0, 2, 66, NULL, }, + { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, + { "AR[ITC]", 26, 0, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, + { "AR[LC]", 26, 0, 2, 65, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 2, 64, NULL, }, + { "AR[PFS]", 26, 0, 0, 64, NULL, }, + { "AR[RNAT]", 26, 0, 2, 19, NULL, }, + { "AR[RSC]", 26, 0, 2, 16, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, + { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 0, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 2, -1, NULL, }, + { "CFM", 6, 0, 0, -1, NULL, }, + { "CPUID#", 7, 0, 5, -1, NULL, }, + { "CR[CMCV]", 27, 0, 3, 74, NULL, }, + { "CR[DCR]", 27, 0, 3, 0, NULL, }, { "CR[EOI]", 27, 0, 7, 67, "SC Section 10.8.3.4", }, - { "CR[GPTA]", 27, 0, 3, 9, }, - { "CR[IFA]", 27, 0, 1, 20, }, - { "CR[IFA]", 27, 0, 3, 20, }, - { "CR[IFS]", 27, 0, 3, 23, }, - { "CR[IFS]", 27, 0, 1, 23, }, - { "CR[IFS]", 27, 0, 1, 23, }, - { "CR[IHA]", 27, 0, 3, 25, }, - { "CR[IIM]", 27, 0, 3, 24, }, - { "CR[IIP]", 27, 0, 3, 19, }, - { "CR[IIP]", 27, 0, 1, 19, }, - { "CR[IIPA]", 27, 0, 3, 22, }, - { "CR[IPSR]", 27, 0, 3, 16, }, - { "CR[IPSR]", 27, 0, 1, 16, }, - { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, }, - { "CR[ISR]", 27, 0, 3, 17, }, - { "CR[ITIR]", 27, 0, 3, 21, }, - { "CR[ITIR]", 27, 0, 1, 21, }, - { "CR[ITM]", 27, 0, 3, 1, }, - { "CR[ITV]", 27, 0, 3, 72, }, - { "CR[IVA]", 27, 0, 4, 2, }, + { "CR[GPTA]", 27, 0, 3, 9, NULL, }, + { "CR[IFA]", 27, 0, 1, 20, NULL, }, + { "CR[IFA]", 27, 0, 3, 20, NULL, }, + { "CR[IFS]", 27, 0, 3, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IFS]", 27, 0, 1, 23, NULL, }, + { "CR[IHA]", 27, 0, 3, 25, NULL, }, + { "CR[IIM]", 27, 0, 3, 24, NULL, }, + { "CR[IIP]", 27, 0, 3, 19, NULL, }, + { "CR[IIP]", 27, 0, 1, 19, NULL, }, + { "CR[IIPA]", 27, 0, 3, 22, NULL, }, + { "CR[IPSR]", 27, 0, 3, 16, NULL, }, + { "CR[IPSR]", 27, 0, 1, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 0, 3, -1, NULL, }, + { "CR[ISR]", 27, 0, 3, 17, NULL, }, + { "CR[ITIR]", 27, 0, 3, 21, NULL, }, + { "CR[ITIR]", 27, 0, 1, 21, NULL, }, + { "CR[ITM]", 27, 0, 3, 1, NULL, }, + { "CR[ITV]", 27, 0, 3, 72, NULL, }, + { "CR[IVA]", 27, 0, 4, 2, NULL, }, { "CR[IVR]", 27, 0, 7, 65, "SC Section 10.8.3.2", }, { "CR[LID]", 27, 0, 7, 64, "SC Section 10.8.3.1", }, - { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, }, - { "CR[PMV]", 27, 0, 3, 73, }, - { "CR[PTA]", 27, 0, 3, 8, }, - { "CR[TPR]", 27, 0, 3, 66, }, + { "CR[LRR%], % in 0 - 1", 9, 0, 3, -1, NULL, }, + { "CR[PMV]", 27, 0, 3, 73, NULL, }, + { "CR[PTA]", 27, 0, 3, 8, NULL, }, + { "CR[TPR]", 27, 0, 3, 66, NULL, }, { "CR[TPR]", 27, 0, 7, 66, "SC Section 10.8.3.3", }, - { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, }, - { "DBR#", 11, 0, 2, -1, }, - { "DBR#", 11, 0, 3, -1, }, - { "DTC", 0, 0, 3, -1, }, - { "DTC", 0, 0, 2, -1, }, - { "DTC", 0, 0, 0, -1, }, - { "DTC", 0, 0, 2, -1, }, - { "DTC_LIMIT*", 0, 0, 2, -1, }, - { "DTR", 0, 0, 3, -1, }, - { "DTR", 0, 0, 2, -1, }, - { "DTR", 0, 0, 3, -1, }, - { "DTR", 0, 0, 0, -1, }, - { "DTR", 0, 0, 2, -1, }, - { "FR%, % in 0 - 1", 12, 0, 0, -1, }, - { "FR%, % in 2 - 127", 13, 0, 2, -1, }, - { "FR%, % in 2 - 127", 13, 0, 0, -1, }, - { "GR0", 14, 0, 0, -1, }, - { "GR%, % in 1 - 127", 15, 0, 0, -1, }, - { "GR%, % in 1 - 127", 15, 0, 2, -1, }, - { "IBR#", 16, 0, 2, -1, }, - { "InService*", 17, 0, 3, -1, }, - { "InService*", 17, 0, 2, -1, }, - { "InService*", 17, 0, 2, -1, }, - { "IP", 0, 0, 0, -1, }, - { "ITC", 0, 0, 4, -1, }, - { "ITC", 0, 0, 2, -1, }, - { "ITC", 0, 0, 0, -1, }, - { "ITC", 0, 0, 4, -1, }, - { "ITC", 0, 0, 2, -1, }, - { "ITC_LIMIT*", 0, 0, 2, -1, }, - { "ITR", 0, 0, 2, -1, }, - { "ITR", 0, 0, 4, -1, }, - { "ITR", 0, 0, 2, -1, }, - { "ITR", 0, 0, 0, -1, }, - { "ITR", 0, 0, 4, -1, }, - { "memory", 0, 0, 0, -1, }, - { "MSR#", 18, 0, 5, -1, }, - { "PKR#", 19, 0, 3, -1, }, - { "PKR#", 19, 0, 0, -1, }, - { "PKR#", 19, 0, 2, -1, }, - { "PKR#", 19, 0, 2, -1, }, - { "PMC#", 20, 0, 2, -1, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 0, 0, -1, NULL, }, + { "DBR#", 11, 0, 2, -1, NULL, }, + { "DBR#", 11, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 3, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC", 0, 0, 0, -1, NULL, }, + { "DTC", 0, 0, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "DTR", 0, 0, 3, -1, NULL, }, + { "DTR", 0, 0, 0, -1, NULL, }, + { "DTR", 0, 0, 2, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 0, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 2, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 0, 0, -1, NULL, }, + { "GR0", 14, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 0, 2, -1, NULL, }, + { "IBR#", 16, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 3, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "InService*", 17, 0, 2, -1, NULL, }, + { "IP", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC", 0, 0, 0, -1, NULL, }, + { "ITC", 0, 0, 4, -1, NULL, }, + { "ITC", 0, 0, 2, -1, NULL, }, + { "ITC_LIMIT*", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "ITR", 0, 0, 2, -1, NULL, }, + { "ITR", 0, 0, 0, -1, NULL, }, + { "ITR", 0, 0, 4, -1, NULL, }, + { "memory", 0, 0, 0, -1, NULL, }, + { "MSR#", 18, 0, 5, -1, NULL, }, + { "PKR#", 19, 0, 3, -1, NULL, }, + { "PKR#", 19, 0, 0, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PKR#", 19, 0, 2, -1, NULL, }, + { "PMC#", 20, 0, 2, -1, NULL, }, { "PMC#", 20, 0, 7, -1, "SC+3 Section 12.1.1", }, - { "PMD#", 21, 0, 2, -1, }, - { "PR0", 0, 0, 0, -1, }, - { "PR%, % in 1 - 15", 22, 0, 2, -1, }, - { "PR%, % in 1 - 15", 22, 0, 2, -1, }, - { "PR%, % in 1 - 15", 22, 0, 0, -1, }, - { "PR%, % in 16 - 62", 23, 0, 2, -1, }, - { "PR%, % in 16 - 62", 23, 0, 2, -1, }, - { "PR%, % in 16 - 62", 23, 0, 0, -1, }, - { "PR63", 24, 0, 2, -1, }, - { "PR63", 24, 0, 2, -1, }, - { "PR63", 24, 0, 0, -1, }, - { "PSR.ac", 28, 0, 1, 3, }, - { "PSR.ac", 28, 0, 3, 3, }, - { "PSR.ac", 28, 0, 2, 3, }, - { "PSR.be", 28, 0, 1, 1, }, - { "PSR.be", 28, 0, 3, 1, }, - { "PSR.be", 28, 0, 2, 1, }, - { "PSR.bn", 28, 0, 2, 44, }, - { "PSR.cpl", 28, 0, 1, 32, }, - { "PSR.da", 28, 0, 3, 38, }, - { "PSR.db", 28, 0, 3, 24, }, - { "PSR.db", 28, 0, 2, 24, }, - { "PSR.db", 28, 0, 3, 24, }, - { "PSR.dd", 28, 0, 3, 39, }, - { "PSR.dfh", 28, 0, 3, 19, }, - { "PSR.dfh", 28, 0, 2, 19, }, - { "PSR.dfl", 28, 0, 3, 18, }, - { "PSR.dfl", 28, 0, 2, 18, }, - { "PSR.di", 28, 0, 3, 22, }, - { "PSR.di", 28, 0, 2, 22, }, - { "PSR.dt", 28, 0, 3, 17, }, - { "PSR.dt", 28, 0, 2, 17, }, - { "PSR.ed", 28, 0, 3, 43, }, - { "PSR.i", 28, 0, 2, 14, }, - { "PSR.i", 28, 0, 3, 14, }, - { "PSR.ia", 28, 0, 0, 14, }, - { "PSR.ic", 28, 0, 2, 13, }, - { "PSR.ic", 28, 0, 3, 13, }, - { "PSR.id", 28, 0, 0, 14, }, - { "PSR.is", 28, 0, 0, 14, }, - { "PSR.it", 28, 0, 3, 14, }, - { "PSR.lp", 28, 0, 2, 25, }, - { "PSR.lp", 28, 0, 3, 25, }, - { "PSR.lp", 28, 0, 3, 25, }, - { "PSR.mc", 28, 0, 0, 35, }, - { "PSR.mfh", 28, 0, 2, 5, }, - { "PSR.mfl", 28, 0, 2, 4, }, - { "PSR.pk", 28, 0, 3, 15, }, - { "PSR.pk", 28, 0, 2, 15, }, - { "PSR.pp", 28, 0, 2, 21, }, - { "PSR.ri", 28, 0, 0, 41, }, - { "PSR.rt", 28, 0, 2, 27, }, - { "PSR.rt", 28, 0, 3, 27, }, - { "PSR.rt", 28, 0, 3, 27, }, - { "PSR.si", 28, 0, 2, 23, }, - { "PSR.si", 28, 0, 3, 23, }, - { "PSR.sp", 28, 0, 2, 20, }, - { "PSR.sp", 28, 0, 3, 20, }, - { "PSR.ss", 28, 0, 3, 40, }, - { "PSR.tb", 28, 0, 3, 26, }, - { "PSR.tb", 28, 0, 2, 26, }, - { "PSR.up", 28, 0, 2, 2, }, - { "RR#", 25, 0, 3, -1, }, - { "RR#", 25, 0, 2, -1, }, - { "RSE", 29, 0, 2, -1, }, - { "ALAT", 0, 1, 0, -1, }, - { "AR[BSP]", 26, 1, 2, 17, }, - { "AR[BSPSTORE]", 26, 1, 2, 18, }, - { "AR[CCV]", 26, 1, 2, 32, }, - { "AR[EC]", 26, 1, 2, 66, }, - { "AR[FPSR].sf0.controls", 30, 1, 2, -1, }, - { "AR[FPSR].sf1.controls", 30, 1, 2, -1, }, - { "AR[FPSR].sf2.controls", 30, 1, 2, -1, }, - { "AR[FPSR].sf3.controls", 30, 1, 2, -1, }, - { "AR[FPSR].sf0.flags", 30, 1, 0, -1, }, - { "AR[FPSR].sf0.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf0.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf1.flags", 30, 1, 0, -1, }, - { "AR[FPSR].sf1.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf1.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf2.flags", 30, 1, 0, -1, }, - { "AR[FPSR].sf2.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf2.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf3.flags", 30, 1, 0, -1, }, - { "AR[FPSR].sf3.flags", 30, 1, 2, -1, }, - { "AR[FPSR].sf3.flags", 30, 1, 2, -1, }, - { "AR[FPSR].rv", 30, 1, 2, -1, }, - { "AR[FPSR].traps", 30, 1, 2, -1, }, - { "AR[ITC]", 26, 1, 2, 44, }, - { "AR[K%], % in 0 - 7", 1, 1, 2, -1, }, - { "AR[LC]", 26, 1, 2, 65, }, - { "AR[PFS]", 26, 1, 0, 64, }, - { "AR[PFS]", 26, 1, 2, 64, }, - { "AR[PFS]", 26, 1, 2, 64, }, - { "AR[RNAT]", 26, 1, 2, 19, }, - { "AR[RSC]", 26, 1, 2, 16, }, - { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, }, - { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, }, - { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, }, - { "BR%, % in 0 - 7", 5, 1, 2, -1, }, - { "BR%, % in 0 - 7", 5, 1, 0, -1, }, - { "CFM", 6, 1, 2, -1, }, - { "CPUID#", 7, 1, 0, -1, }, - { "CR[CMCV]", 27, 1, 2, 74, }, - { "CR[DCR]", 27, 1, 2, 0, }, + { "PMD#", 21, 0, 2, -1, NULL, }, + { "PR0", 0, 0, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 0, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 0, 0, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 2, -1, NULL, }, + { "PR63", 24, 0, 0, -1, NULL, }, + { "PSR.ac", 28, 0, 1, 3, NULL, }, + { "PSR.ac", 28, 0, 3, 3, NULL, }, + { "PSR.ac", 28, 0, 2, 3, NULL, }, + { "PSR.be", 28, 0, 1, 1, NULL, }, + { "PSR.be", 28, 0, 3, 1, NULL, }, + { "PSR.be", 28, 0, 2, 1, NULL, }, + { "PSR.bn", 28, 0, 2, 44, NULL, }, + { "PSR.cpl", 28, 0, 1, 32, NULL, }, + { "PSR.da", 28, 0, 3, 38, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.db", 28, 0, 2, 24, NULL, }, + { "PSR.db", 28, 0, 3, 24, NULL, }, + { "PSR.dd", 28, 0, 3, 39, NULL, }, + { "PSR.dfh", 28, 0, 3, 19, NULL, }, + { "PSR.dfh", 28, 0, 2, 19, NULL, }, + { "PSR.dfl", 28, 0, 3, 18, NULL, }, + { "PSR.dfl", 28, 0, 2, 18, NULL, }, + { "PSR.di", 28, 0, 3, 22, NULL, }, + { "PSR.di", 28, 0, 2, 22, NULL, }, + { "PSR.dt", 28, 0, 3, 17, NULL, }, + { "PSR.dt", 28, 0, 2, 17, NULL, }, + { "PSR.ed", 28, 0, 3, 43, NULL, }, + { "PSR.i", 28, 0, 2, 14, NULL, }, + { "PSR.i", 28, 0, 3, 14, NULL, }, + { "PSR.ia", 28, 0, 0, 14, NULL, }, + { "PSR.ic", 28, 0, 2, 13, NULL, }, + { "PSR.ic", 28, 0, 3, 13, NULL, }, + { "PSR.id", 28, 0, 0, 14, NULL, }, + { "PSR.is", 28, 0, 0, 14, NULL, }, + { "PSR.it", 28, 0, 3, 14, NULL, }, + { "PSR.lp", 28, 0, 2, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.lp", 28, 0, 3, 25, NULL, }, + { "PSR.mc", 28, 0, 0, 35, NULL, }, + { "PSR.mfh", 28, 0, 2, 5, NULL, }, + { "PSR.mfl", 28, 0, 2, 4, NULL, }, + { "PSR.pk", 28, 0, 3, 15, NULL, }, + { "PSR.pk", 28, 0, 2, 15, NULL, }, + { "PSR.pp", 28, 0, 2, 21, NULL, }, + { "PSR.ri", 28, 0, 0, 41, NULL, }, + { "PSR.rt", 28, 0, 2, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.rt", 28, 0, 3, 27, NULL, }, + { "PSR.si", 28, 0, 2, 23, NULL, }, + { "PSR.si", 28, 0, 3, 23, NULL, }, + { "PSR.sp", 28, 0, 2, 20, NULL, }, + { "PSR.sp", 28, 0, 3, 20, NULL, }, + { "PSR.ss", 28, 0, 3, 40, NULL, }, + { "PSR.tb", 28, 0, 3, 26, NULL, }, + { "PSR.tb", 28, 0, 2, 26, NULL, }, + { "PSR.up", 28, 0, 2, 2, NULL, }, + { "RR#", 25, 0, 3, -1, NULL, }, + { "RR#", 25, 0, 2, -1, NULL, }, + { "RSE", 29, 0, 2, -1, NULL, }, + { "ALAT", 0, 1, 0, -1, NULL, }, + { "AR[BSP]", 26, 1, 2, 17, NULL, }, + { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, + { "AR[CCV]", 26, 1, 2, 32, NULL, }, + { "AR[EC]", 26, 1, 2, 66, NULL, }, + { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.controls", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf0.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf1.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf2.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 0, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, + { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, + { "AR[ITC]", 26, 1, 2, 44, NULL, }, + { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, + { "AR[LC]", 26, 1, 2, 65, NULL, }, + { "AR[PFS]", 26, 1, 0, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[PFS]", 26, 1, 2, 64, NULL, }, + { "AR[RNAT]", 26, 1, 2, 19, NULL, }, + { "AR[RSC]", 26, 1, 2, 16, NULL, }, + { "AR[UNAT]{%}, % in 0 - 63", 2, 1, 2, -1, NULL, }, + { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 1, 0, -1, NULL, }, + { "AR%, % in 48 - 63, 112-127", 4, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 2, -1, NULL, }, + { "BR%, % in 0 - 7", 5, 1, 0, -1, NULL, }, + { "CFM", 6, 1, 2, -1, NULL, }, + { "CPUID#", 7, 1, 0, -1, NULL, }, + { "CR[CMCV]", 27, 1, 2, 74, NULL, }, + { "CR[DCR]", 27, 1, 2, 0, NULL, }, { "CR[EOI]", 27, 1, 7, 67, "SC Section 10.8.3.4", }, - { "CR[GPTA]", 27, 1, 2, 9, }, - { "CR[IFA]", 27, 1, 2, 20, }, - { "CR[IFS]", 27, 1, 2, 23, }, - { "CR[IHA]", 27, 1, 2, 25, }, - { "CR[IIM]", 27, 1, 2, 24, }, - { "CR[IIP]", 27, 1, 2, 19, }, - { "CR[IIPA]", 27, 1, 2, 22, }, - { "CR[IPSR]", 27, 1, 2, 16, }, - { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, }, - { "CR[ISR]", 27, 1, 2, 17, }, - { "CR[ITIR]", 27, 1, 2, 21, }, - { "CR[ITM]", 27, 1, 2, 1, }, - { "CR[ITV]", 27, 1, 2, 72, }, - { "CR[IVA]", 27, 1, 2, 2, }, + { "CR[GPTA]", 27, 1, 2, 9, NULL, }, + { "CR[IFA]", 27, 1, 2, 20, NULL, }, + { "CR[IFS]", 27, 1, 2, 23, NULL, }, + { "CR[IHA]", 27, 1, 2, 25, NULL, }, + { "CR[IIM]", 27, 1, 2, 24, NULL, }, + { "CR[IIP]", 27, 1, 2, 19, NULL, }, + { "CR[IIPA]", 27, 1, 2, 22, NULL, }, + { "CR[IPSR]", 27, 1, 2, 16, NULL, }, + { "CR[IRR%], % in 0 - 3", 8, 1, 2, -1, NULL, }, + { "CR[ISR]", 27, 1, 2, 17, NULL, }, + { "CR[ITIR]", 27, 1, 2, 21, NULL, }, + { "CR[ITM]", 27, 1, 2, 1, NULL, }, + { "CR[ITV]", 27, 1, 2, 72, NULL, }, + { "CR[IVA]", 27, 1, 2, 2, NULL, }, { "CR[IVR]", 27, 1, 7, 65, "SC", }, { "CR[LID]", 27, 1, 7, 64, "SC", }, - { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, }, - { "CR[PMV]", 27, 1, 2, 73, }, - { "CR[PTA]", 27, 1, 2, 8, }, - { "CR[TPR]", 27, 1, 2, 66, }, - { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, }, - { "DBR#", 11, 1, 2, -1, }, - { "DTC", 0, 1, 0, -1, }, - { "DTC", 0, 1, 2, -1, }, - { "DTC", 0, 1, 2, -1, }, - { "DTC_LIMIT*", 0, 1, 2, -1, }, - { "DTR", 0, 1, 2, -1, }, - { "DTR", 0, 1, 2, -1, }, - { "DTR", 0, 1, 2, -1, }, - { "DTR", 0, 1, 0, -1, }, - { "FR%, % in 0 - 1", 12, 1, 0, -1, }, - { "FR%, % in 2 - 127", 13, 1, 2, -1, }, - { "GR0", 14, 1, 0, -1, }, - { "GR%, % in 1 - 127", 15, 1, 2, -1, }, - { "IBR#", 16, 1, 2, -1, }, + { "CR[LRR%], % in 0 - 1", 9, 1, 2, -1, NULL, }, + { "CR[PMV]", 27, 1, 2, 73, NULL, }, + { "CR[PTA]", 27, 1, 2, 8, NULL, }, + { "CR[TPR]", 27, 1, 2, 66, NULL, }, + { "CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127", 10, 1, 0, -1, NULL, }, + { "DBR#", 11, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 0, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC", 0, 1, 2, -1, NULL, }, + { "DTC_LIMIT*", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 2, -1, NULL, }, + { "DTR", 0, 1, 0, -1, NULL, }, + { "FR%, % in 0 - 1", 12, 1, 0, -1, NULL, }, + { "FR%, % in 2 - 127", 13, 1, 2, -1, NULL, }, + { "GR0", 14, 1, 0, -1, NULL, }, + { "GR%, % in 1 - 127", 15, 1, 2, -1, NULL, }, + { "IBR#", 16, 1, 2, -1, NULL, }, { "InService*", 17, 1, 7, -1, "SC", }, - { "IP", 0, 1, 0, -1, }, - { "ITC", 0, 1, 0, -1, }, - { "ITC", 0, 1, 2, -1, }, - { "ITC", 0, 1, 2, -1, }, - { "ITR", 0, 1, 2, -1, }, - { "ITR", 0, 1, 2, -1, }, - { "ITR", 0, 1, 0, -1, }, - { "memory", 0, 1, 0, -1, }, + { "IP", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 0, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITC", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 2, -1, NULL, }, + { "ITR", 0, 1, 0, -1, NULL, }, + { "memory", 0, 1, 0, -1, NULL, }, { "MSR#", 18, 1, 7, -1, "SC", }, - { "PKR#", 19, 1, 0, -1, }, - { "PKR#", 19, 1, 0, -1, }, - { "PKR#", 19, 1, 2, -1, }, - { "PMC#", 20, 1, 2, -1, }, - { "PMD#", 21, 1, 2, -1, }, - { "PR0", 0, 1, 0, -1, }, - { "PR%, % in 1 - 15", 22, 1, 0, -1, }, - { "PR%, % in 1 - 15", 22, 1, 0, -1, }, - { "PR%, % in 1 - 15", 22, 1, 2, -1, }, - { "PR%, % in 1 - 15", 22, 1, 2, -1, }, - { "PR%, % in 16 - 62", 23, 1, 0, -1, }, - { "PR%, % in 16 - 62", 23, 1, 0, -1, }, - { "PR%, % in 16 - 62", 23, 1, 2, -1, }, - { "PR%, % in 16 - 62", 23, 1, 2, -1, }, - { "PR63", 24, 1, 0, -1, }, - { "PR63", 24, 1, 0, -1, }, - { "PR63", 24, 1, 2, -1, }, - { "PR63", 24, 1, 2, -1, }, - { "PSR.ac", 28, 1, 2, 3, }, - { "PSR.be", 28, 1, 2, 1, }, - { "PSR.bn", 28, 1, 2, 44, }, - { "PSR.cpl", 28, 1, 2, 32, }, - { "PSR.da", 28, 1, 2, 38, }, - { "PSR.db", 28, 1, 2, 24, }, - { "PSR.dd", 28, 1, 2, 39, }, - { "PSR.dfh", 28, 1, 2, 19, }, - { "PSR.dfl", 28, 1, 2, 18, }, - { "PSR.di", 28, 1, 2, 22, }, - { "PSR.dt", 28, 1, 2, 17, }, - { "PSR.ed", 28, 1, 2, 43, }, - { "PSR.i", 28, 1, 2, 14, }, - { "PSR.ia", 28, 1, 2, 14, }, - { "PSR.ic", 28, 1, 2, 13, }, - { "PSR.id", 28, 1, 2, 14, }, - { "PSR.is", 28, 1, 2, 14, }, - { "PSR.it", 28, 1, 2, 14, }, - { "PSR.lp", 28, 1, 2, 25, }, - { "PSR.mc", 28, 1, 2, 35, }, - { "PSR.mfh", 28, 1, 0, 5, }, - { "PSR.mfh", 28, 1, 2, 5, }, - { "PSR.mfh", 28, 1, 2, 5, }, - { "PSR.mfl", 28, 1, 0, 4, }, - { "PSR.mfl", 28, 1, 2, 4, }, - { "PSR.mfl", 28, 1, 2, 4, }, - { "PSR.pk", 28, 1, 2, 15, }, - { "PSR.pp", 28, 1, 2, 21, }, - { "PSR.ri", 28, 1, 2, 41, }, - { "PSR.rt", 28, 1, 2, 27, }, - { "PSR.si", 28, 1, 2, 23, }, - { "PSR.sp", 28, 1, 2, 20, }, - { "PSR.ss", 28, 1, 2, 40, }, - { "PSR.tb", 28, 1, 2, 26, }, - { "PSR.up", 28, 1, 2, 2, }, - { "RR#", 25, 1, 2, -1, }, - { "RSE", 29, 1, 2, -1, }, - { "PR63", 24, 2, 6, -1, }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 0, -1, NULL, }, + { "PKR#", 19, 1, 2, -1, NULL, }, + { "PMC#", 20, 1, 2, -1, NULL, }, + { "PMD#", 21, 1, 2, -1, NULL, }, + { "PR0", 0, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 0, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 1 - 15", 22, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 0, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR%, % in 16 - 62", 23, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 0, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PR63", 24, 1, 2, -1, NULL, }, + { "PSR.ac", 28, 1, 2, 3, NULL, }, + { "PSR.be", 28, 1, 2, 1, NULL, }, + { "PSR.bn", 28, 1, 2, 44, NULL, }, + { "PSR.cpl", 28, 1, 2, 32, NULL, }, + { "PSR.da", 28, 1, 2, 38, NULL, }, + { "PSR.db", 28, 1, 2, 24, NULL, }, + { "PSR.dd", 28, 1, 2, 39, NULL, }, + { "PSR.dfh", 28, 1, 2, 19, NULL, }, + { "PSR.dfl", 28, 1, 2, 18, NULL, }, + { "PSR.di", 28, 1, 2, 22, NULL, }, + { "PSR.dt", 28, 1, 2, 17, NULL, }, + { "PSR.ed", 28, 1, 2, 43, NULL, }, + { "PSR.i", 28, 1, 2, 14, NULL, }, + { "PSR.ia", 28, 1, 2, 14, NULL, }, + { "PSR.ic", 28, 1, 2, 13, NULL, }, + { "PSR.id", 28, 1, 2, 14, NULL, }, + { "PSR.is", 28, 1, 2, 14, NULL, }, + { "PSR.it", 28, 1, 2, 14, NULL, }, + { "PSR.lp", 28, 1, 2, 25, NULL, }, + { "PSR.mc", 28, 1, 2, 35, NULL, }, + { "PSR.mfh", 28, 1, 0, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfh", 28, 1, 2, 5, NULL, }, + { "PSR.mfl", 28, 1, 0, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.mfl", 28, 1, 2, 4, NULL, }, + { "PSR.pk", 28, 1, 2, 15, NULL, }, + { "PSR.pp", 28, 1, 2, 21, NULL, }, + { "PSR.ri", 28, 1, 2, 41, NULL, }, + { "PSR.rt", 28, 1, 2, 27, NULL, }, + { "PSR.si", 28, 1, 2, 23, NULL, }, + { "PSR.sp", 28, 1, 2, 20, NULL, }, + { "PSR.ss", 28, 1, 2, 40, NULL, }, + { "PSR.tb", 28, 1, 2, 26, NULL, }, + { "PSR.up", 28, 1, 2, 2, NULL, }, + { "RR#", 25, 1, 2, -1, NULL, }, + { "RSE", 29, 1, 2, -1, NULL, }, + { "PR63", 24, 2, 6, -1, NULL, }, }; static const short dep0[] = { @@ -4094,398 +4094,398 @@ completer_table[] = { static const struct ia64_main_table main_table[] = { - { 5, 1, 1, 0x10000000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, - { 5, 1, 1, 0x10008000000ull, 0x1eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 1, }, - { 5, 7, 1, 0x0ull, 0x0ull, { 23, 65, 25, 0, 0 }, 0x0, 2, }, - { 6, 1, 1, 0x12000000000ull, 0x1e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 3, }, - { 7, 1, 1, 0x10040000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 4, }, - { 7, 1, 1, 0x10c00000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 5, }, - { 8, 1, 1, 0x10800000000ull, 0x1ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 6, }, - { 9, 3, 1, 0x2c00000000ull, 0x1ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 7, }, - { 10, 1, 1, 0x10060000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 8, }, - { 10, 1, 1, 0x10160000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 9, }, - { 11, 1, 1, 0x10068000000ull, 0x1eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 10, }, - { 11, 1, 1, 0x10168000000ull, 0x1eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 11, }, - { 14, 4, 0, 0x100000000ull, 0x1eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 781, }, - { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 647, }, - { 14, 4, 0, 0x100000000ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 648, }, - { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1770, }, - { 14, 4, 0, 0x108000100ull, 0x1eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1771, }, - { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 404, }, - { 14, 4, 1, 0x2000000000ull, 0x1ee00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 405, }, - { 14, 4, 0, 0x8000000000ull, 0x1ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 802, }, - { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 649, }, - { 14, 4, 0, 0x8000000000ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 650, }, - { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 2406, }, - { 14, 4, 0, 0x8000000080ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 2407, }, - { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 412, }, - { 14, 4, 0, 0x8000000140ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 413, }, - { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 410, }, - { 14, 4, 0, 0x8000000180ull, 0x1ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 411, }, - { 14, 4, 1, 0xa000000000ull, 0x1ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 406, }, - { 14, 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0x0000010680000000ull, 0x000001ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 159, }, + { 200, 2, 1, 0x000000e220000000ull, 0x000001fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 160, }, + { 200, 2, 1, 0x000000e630000000ull, 0x000001fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 161, }, + { 201, 2, 1, 0x000000f020000000ull, 0x000001fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 162, }, + { 201, 2, 1, 0x000000f430000000ull, 0x000001fff0000000ull, { 23, 25, 42, 0, 0 }, 0x0, 163, }, + { 202, 1, 1, 0x00000106c0000000ull, 0x000001ffe0000000ull, { 23, 24, 40, 25, 0 }, 0x0, 164, }, + { 203, 1, 1, 0x0000010420000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 165, }, + { 204, 1, 1, 0x0000010620000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 166, }, + { 205, 1, 1, 0x0000011420000000ull, 0x000001fff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 167, }, + { 206, 3, 0, 0x0000002048000000ull, 0x000001eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 943, }, + { 206, 3, 0, 0x0000002050000000ull, 0x000001eff8000000ull, { 25, 24, 0, 0, 0 }, 0xc, 862, }, + { 206, 3, 0, 0x00000021a0000000ull, 0x000001eff8000000ull, { 25, 0, 0, 0, 0 }, 0x8, 744, }, + { 207, 3, 0, 0x0000002060000000ull, 0x000001eff8000000ull, { 25, 24, 0, 0, 0 }, 0x8, 670, }, + { 212, 4, 0, 0x0000000040000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 168, }, + { 213, 3, 0, 0x0000000038000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 169, }, + { 214, 3, 0, 0x0000000028000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 170, }, + { 223, 3, 1, 0x000000c708000000ull, 0x000001ffc8000000ull, { 17, 24, 0, 0, 0 }, 0x0, 2222, }, + { 224, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 23, 24, 44, 0, 0 }, 0x140, 171, }, + { 224, 2, 1, 0x000000f240000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 172, }, + { 225, 1, 1, 0x0000010080000000ull, 0x000001efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 173, }, + { 226, 1, 1, 0x00000100c0000000ull, 0x000001efe0000000ull, { 23, 24, 39, 25, 0 }, 0x0, 174, }, + { 227, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 23, 25, 75, 0, 0 }, 0x140, 2318, }, + { 227, 2, 1, 0x000000f220000000ull, 0x000001fff0000000ull, { 23, 25, 24, 0, 0 }, 0x0, 176, }, + { 228, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 23, 24, 25, 43, 0 }, 0x0, 177, }, + { 233, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 672, }, + { 234, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x8, 178, }, + { 236, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 179, }, + { 236, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 180, }, + { 237, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 181, }, + { 237, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 182, }, + { 238, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 183, }, + { 238, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 184, }, + { 239, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 32, 24, 0, 0, 0 }, 0x0, 185, }, + { 239, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 32, 24, 60, 0, 0 }, 0x400, 186, }, + { 240, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 2225, }, + { 240, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 2226, }, + { 241, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 187, }, + { 241, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 188, }, + { 242, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 189, }, + { 242, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 190, }, + { 243, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 191, }, + { 243, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 192, }, + { 244, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 32, 18, 0, 0, 0 }, 0x0, 193, }, + { 244, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 32, 18, 60, 0, 0 }, 0x400, 194, }, + { 245, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 195, }, + { 245, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 196, }, + { 245, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 197, }, + { 246, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 66, 0, 0, 0, 0 }, 0x0, 198, }, + { 247, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 199, }, + { 248, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 200, }, + { 249, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 201, }, + { 250, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 918, }, + { 251, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 202, }, + { 252, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 21, 22, 25, 75, 0 }, 0x0, 2416, }, + { 252, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 21, 25, 75, 0 }, 0x40, 1675, }, + { 253, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 203, }, + { 254, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 21, 22, 25, 0, 0 }, 0x0, 2418, }, + { 254, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 21, 25, 0, 0 }, 0x40, 1677, }, + { 255, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x8, 204, }, + { 257, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 205, }, + { 261, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 901, }, + { 262, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 902, }, + { 263, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 23, 24, 25, 0, 0 }, 0x0, 903, }, + { 271, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 206, }, + { 272, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 207, }, + { 273, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 208, }, + { 274, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 23, 32, 24, 0, 0 }, 0x0, 209, }, + { 276, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x0, 947, }, + { 276, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 17, 19, 20, 18, 0 }, 0x40, 987, }, + { 277, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 17, 19, 20, 0, 0 }, 0x40, 948, }, + { 278, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 210, }, + { 278, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 211, }, + { 281, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 212, }, + { 282, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 213, }, + { 283, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 23, 25, 0, 0, 0 }, 0x0, 214, }, }; static const char dis_table[] = { diff --git a/opcodes/ia64-dis.c b/opcodes/ia64-dis.c index c776abd..5e46796 100644 --- a/opcodes/ia64-dis.c +++ b/opcodes/ia64-dis.c @@ -261,7 +261,7 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) (*info->fprintf_func) (info->stream, ";;"); done: - ia64_free_opcode (idesc); + ia64_free_opcode ((struct ia64_opcode *)idesc); failed: if (slotnum == 2) retval += 16 - 3*slot_multiplier; diff --git a/opcodes/ia64-gen.c b/opcodes/ia64-gen.c index f0451ce..e5e4e93 100644 --- a/opcodes/ia64-gen.c +++ b/opcodes/ia64-gen.c @@ -281,14 +281,14 @@ insert_deplist(int count, unsigned short *deps) for (i=0;i < count;i++) set[deps[i]] = 1; count = 0; - for (i=0;i < sizeof(set);i++) + for (i=0;i < (int)sizeof(set);i++) if (set[i]) ++count; list = tmalloc(struct deplist); list->len = count; list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count); - for (i=0, count=0;i < sizeof(set);i++) + for (i=0, count=0;i < (int)sizeof(set);i++) { if (set[i]) { @@ -1459,6 +1459,8 @@ print_dependency_table () (int)rdeps[i]->mode, (int)rdeps[i]->semantics, regindex); if (rdeps[i]->semantics == IA64_DVS_OTHER) printf ("\"%s\", ", rdeps[i]->extra); + else + printf ("NULL, "); printf("},\n"); } printf ("};\n\n"); @@ -2395,7 +2397,7 @@ collapse_redundant_completers () int insert_opcode_dependencies (opc, cmp) struct ia64_opcode *opc; - struct completer_entry *cmp; + struct completer_entry *cmp ATTRIBUTE_UNUSED; { /* note all resources which point to this opcode. rfi has the most chks (79) and cmpxchng has the most regs (54) so 100 here should be enough */ @@ -2701,12 +2703,14 @@ print_main_table () printf ("static const struct ia64_main_table\nmain_table[] = {\n"); while (ptr != NULL) { - printf (" { %d, %d, %d, 0x%llxull, 0x%llxull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", + printf (" { %d, %d, %d, 0x", ptr->name->num, ptr->opcode->type, - ptr->opcode->num_outputs, - ptr->opcode->opcode, - ptr->opcode->mask, + ptr->opcode->num_outputs); + fprintf_vma (stdout, ptr->opcode->opcode); + printf ("ull, 0x"); + fprintf_vma (stdout, ptr->opcode->mask); + printf ("ull, { %d, %d, %d, %d, %d }, 0x%x, %d, },\n", ptr->opcode->operands[0], ptr->opcode->operands[1], ptr->opcode->operands[2], @@ -2735,7 +2739,9 @@ shrink (table) } int -main (int argc, char **argv) +main (argc, argv) + int argc; + char **argv ATTRIBUTE_UNUSED; { if (argc > 1) { diff --git a/opcodes/ia64-opc.c b/opcodes/ia64-opc.c index c054b3d..c2ddc87 100644 --- a/opcodes/ia64-opc.c +++ b/opcodes/ia64-opc.c @@ -740,7 +740,8 @@ ia64_find_dependency (index) { index = DEP(index); - if (index < 0 || index >= sizeof(dependencies) / sizeof(dependencies[0])) + if (index < 0 + || index >= (int)(sizeof(dependencies) / sizeof(dependencies[0]))) return NULL; return &dependencies[index]; |