diff options
| -rw-r--r-- | gas/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/sse2.d | 10 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 10 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 51 |
4 files changed, 65 insertions, 11 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index fad1588..e12b47f 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + * sse2.d : Fixed the correct result for cvtpi2pd,cvtpd2pi + and cvttpd2pi. + 2006-08-12 Thiemo Seufer <ths@networkno.de> * gas/mips/mips16-save.d: Fix testcase. diff --git a/gas/testsuite/gas/i386/sse2.d b/gas/testsuite/gas/i386/sse2.d index 545def3..2d8af13 100644 --- a/gas/testsuite/gas/i386/sse2.d +++ b/gas/testsuite/gas/i386/sse2.d @@ -61,16 +61,16 @@ Disassembly of section .text: [ ]+f5: f2 0f c2 f8 07[ ]+cmpordsd %xmm0,%xmm7 [ ]+fa: 66 0f 2f c1[ ]+comisd %xmm1,%xmm0 [ ]+fe: 66 0f 2f 0a[ ]+comisd \(%edx\),%xmm1 - 102: 66 0f 2a d3[ ]+cvtpi2pd %xmm3,%xmm2 + 102: 66 0f 2a d3[ ]+cvtpi2pd %mm3,%xmm2 106: 66 0f 2a 1c 24[ ]+cvtpi2pd \(%esp\),%xmm3 10b: f2 0f 2a e5[ ]+cvtsi2sd %ebp,%xmm4 10f: f2 0f 2a 2e[ ]+cvtsi2sd \(%esi\),%xmm5 - 113: 66 0f 2d f7[ ]+cvtpd2pi %xmm7,%xmm6 - 117: 66 0f 2d 38[ ]+cvtpd2pi \(%eax\),%xmm7 + 113: 66 0f 2d f7[ ]+cvtpd2pi %xmm7,%mm6 + 117: 66 0f 2d 38[ ]+cvtpd2pi \(%eax\),%mm7 11b: f2 0f 2d 01[ ]+cvtsd2si \(%ecx\),%eax 11f: f2 0f 2d ca[ ]+cvtsd2si %xmm2,%ecx - 123: 66 0f 2c 13[ ]+cvttpd2pi \(%ebx\),%xmm2 - 127: 66 0f 2c dc[ ]+cvttpd2pi %xmm4,%xmm3 + 123: 66 0f 2c 13[ ]+cvttpd2pi \(%ebx\),%mm2 + 127: 66 0f 2c dc[ ]+cvttpd2pi %xmm4,%mm3 12b: f2 0f 2c 65 00[ ]+cvttsd2si 0x0\(%ebp\),%esp 130: f2 0f 2c ee[ ]+cvttsd2si %xmm6,%ebp 134: 66 0f 5e c1[ ]+divpd[ ]+%xmm1,%xmm0 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index c916655..177f5d8 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,13 @@ +2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + * i386-dis.c (MXC,EMC): Define. + (OP_MXC): New function to handle cvt* (convert instructions) between + %xmm and %mm register correctly. + (OP_EMC): ditto. + (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi + instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately + with EMC/MXC. + 2006-07-29 Richard Sandiford <richard@codesourcery.com> * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 80898c9..8ba7ac4 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -85,6 +85,8 @@ static void OP_MMX (int, int); static void OP_XMM (int, int); static void OP_EM (int, int); static void OP_EX (int, int); +static void OP_EMC (int,int); +static void OP_MXC (int,int); static void OP_MS (int, int); static void OP_XS (int, int); static void OP_M (int, int); @@ -312,6 +314,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EX OP_EX, v_mode #define MS OP_MS, v_mode #define XS OP_XS, v_mode +#define EMC OP_EMC, v_mode +#define MXC OP_MXC, 0 #define VM OP_VMX, q_mode #define OPSUF OP_3DNowSuffix, 0 #define OPSIMD OP_SIMD_Suffix, 0 @@ -1569,23 +1573,23 @@ static const struct dis386 prefix_user_table[][4] = { }, /* PREGRP2 */ { - { "cvtpi2ps", XM, EM, XX, XX }, + { "cvtpi2ps", XM, EMC, XX, XX }, { "cvtsi2ssY", XM, Ev, XX, XX }, - { "cvtpi2pd", XM, EM, XX, XX }, + { "cvtpi2pd", XM, EMC, XX, XX }, { "cvtsi2sdY", XM, Ev, XX, XX }, }, /* PREGRP3 */ { - { "cvtps2pi", MX, EX, XX, XX }, + { "cvtps2pi", MXC, EX, XX, XX }, { "cvtss2siY", Gv, EX, XX, XX }, - { "cvtpd2pi", MX, EX, XX, XX }, + { "cvtpd2pi", MXC, EX, XX, XX }, { "cvtsd2siY", Gv, EX, XX, XX }, }, /* PREGRP4 */ { - { "cvttps2pi", MX, EX, XX, XX }, + { "cvttps2pi", MXC, EX, XX, XX }, { "cvttss2siY", Gv, EX, XX, XX }, - { "cvttpd2pi", MX, EX, XX, XX }, + { "cvttpd2pi", MXC, EX, XX, XX }, { "cvttsd2siY", Gv, EX, XX, XX }, }, /* PREGRP5 */ @@ -4362,6 +4366,41 @@ OP_EM (int bytemode, int sizeflag) oappend (scratchbuf + intel_syntax); } +/* cvt* are the only instructions in sse2 which have + both SSE and MMX operands and also have 0x66 prefix + in their opcode. 0x66 was originally used to differentiate + between SSE and MMX instruction(operands). So we have to handle the + cvt* separately using OP_EMC and OP_MXC */ +static void +OP_EMC (int bytemode, int sizeflag) +{ + if (mod != 3) + { + if (intel_syntax && bytemode == v_mode) + { + bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; + used_prefixes |= (prefixes & PREFIX_DATA); + } + OP_E (bytemode, sizeflag); + return; + } + + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; + used_prefixes |= (prefixes & PREFIX_DATA); + sprintf (scratchbuf, "%%mm%d", rm); + oappend (scratchbuf + intel_syntax); +} + +static void +OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + used_prefixes |= (prefixes & PREFIX_DATA); + sprintf (scratchbuf, "%%mm%d", reg); + oappend (scratchbuf + intel_syntax); +} + static void OP_EX (int bytemode, int sizeflag) { |