diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 | ||||
| -rw-r--r-- | gas/doc/c-riscv.texi | 6 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector-zvamo.d | 81 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-vector-zvamo.s | 74 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 37 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 18 |
7 files changed, 221 insertions, 1 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e2c3ffe..97219b6 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1374,6 +1374,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] = {"xtheadmempair", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadsync", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xtheadvector", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xtheadzvamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -2590,6 +2591,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "xtheadsync"); case INSN_CLASS_XTHEADVECTOR: return riscv_subset_supports (rps, "xtheadvector"); + case INSN_CLASS_XTHEADZVAMO: + return riscv_subset_supports (rps, "xtheadzvamo"); case INSN_CLASS_XVENTANACONDOPS: return riscv_subset_supports (rps, "xventanacondops"); default: @@ -2836,6 +2839,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "xtheadsync"; case INSN_CLASS_XTHEADVECTOR: return "xtheadvector"; + case INSN_CLASS_XTHEADZVAMO: + return "xtheadzvamo"; default: rps->error_handler (_("internal: unreachable INSN_CLASS_*")); diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index a7c9420..763e89c 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -819,6 +819,12 @@ The XTheadVector extension provides instructions for thead vector. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. +@item XTheadZvamo +The XTheadZvamo extension is a subextension of the XTheadVector extension, +and it provides AMO instructions for the T-Head VECTOR vendor extension. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf}. + @item XVentanaCondOps XVentanaCondOps extension provides instructions for branchless sequences that perform conditional arithmetic, conditional diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d new file mode 100644 index 0000000..6b507ad --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.d @@ -0,0 +1,81 @@ +#as: -march=rv32if_xtheadvector_xtheadzvamo +#objdump: -dr + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 <.text>: +[ ]+[0-9a-f]+:[ ]+0685e22f[ ]+th.vamoaddw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0285e22f[ ]+th.vamoaddw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0685f22f[ ]+th.vamoaddd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0285f22f[ ]+th.vamoaddd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0485e22f[ ]+th.vamoaddw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0085e22f[ ]+th.vamoaddw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0485f22f[ ]+th.vamoaddd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0085f22f[ ]+th.vamoaddd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0e85e22f[ ]+th.vamoswapw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0a85e22f[ ]+th.vamoswapw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0e85f22f[ ]+th.vamoswapd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0a85f22f[ ]+th.vamoswapd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+0c85e22f[ ]+th.vamoswapw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0885e22f[ ]+th.vamoswapw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0c85f22f[ ]+th.vamoswapd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+0885f22f[ ]+th.vamoswapd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2685e22f[ ]+th.vamoxorw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2285e22f[ ]+th.vamoxorw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2685f22f[ ]+th.vamoxord.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2285f22f[ ]+th.vamoxord.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+2485e22f[ ]+th.vamoxorw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2085e22f[ ]+th.vamoxorw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2485f22f[ ]+th.vamoxord.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+2085f22f[ ]+th.vamoxord.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6685e22f[ ]+th.vamoandw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6285e22f[ ]+th.vamoandw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6685f22f[ ]+th.vamoandd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6285f22f[ ]+th.vamoandd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+6485e22f[ ]+th.vamoandw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6085e22f[ ]+th.vamoandw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6485f22f[ ]+th.vamoandd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+6085f22f[ ]+th.vamoandd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4685e22f[ ]+th.vamoorw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4285e22f[ ]+th.vamoorw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4685f22f[ ]+th.vamoord.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4285f22f[ ]+th.vamoord.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+4485e22f[ ]+th.vamoorw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4085e22f[ ]+th.vamoorw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4485f22f[ ]+th.vamoord.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+4085f22f[ ]+th.vamoord.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8685e22f[ ]+th.vamominw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8285e22f[ ]+th.vamominw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8685f22f[ ]+th.vamomind.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8285f22f[ ]+th.vamomind.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+8485e22f[ ]+th.vamominw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8085e22f[ ]+th.vamominw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8485f22f[ ]+th.vamomind.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+8085f22f[ ]+th.vamomind.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a685e22f[ ]+th.vamomaxw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a285e22f[ ]+th.vamomaxw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a685f22f[ ]+th.vamomaxd.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a285f22f[ ]+th.vamomaxd.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+a485e22f[ ]+th.vamomaxw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a085e22f[ ]+th.vamomaxw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a485f22f[ ]+th.vamomaxd.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+a085f22f[ ]+th.vamomaxd.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c685e22f[ ]+th.vamominuw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c285e22f[ ]+th.vamominuw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c685f22f[ ]+th.vamominud.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c285f22f[ ]+th.vamominud.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+c485e22f[ ]+th.vamominuw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c085e22f[ ]+th.vamominuw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c485f22f[ ]+th.vamominud.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+c085f22f[ ]+th.vamominud.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e685e22f[ ]+th.vamomaxuw.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e285e22f[ ]+th.vamomaxuw.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e685f22f[ ]+th.vamomaxud.v[ ]+v4,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e285f22f[ ]+th.vamomaxud.v[ ]+zero,v8,\(a1\),v4 +[ ]+[0-9a-f]+:[ ]+e485e22f[ ]+th.vamomaxuw.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e085e22f[ ]+th.vamomaxuw.v[ ]+zero,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e485f22f[ ]+th.vamomaxud.v[ ]+v4,v8,\(a1\),v4,v0.t +[ ]+[0-9a-f]+:[ ]+e085f22f[ ]+th.vamomaxud.v[ ]+zero,v8,\(a1\),v4,v0.t diff --git a/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s new file mode 100644 index 0000000..9d55a1f0 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-vector-zvamo.s @@ -0,0 +1,74 @@ + th.vamoaddw.v v4, v8, (a1), v4 + th.vamoaddw.v x0, v8, (a1), v4 + th.vamoaddd.v v4, v8, (a1), v4 + th.vamoaddd.v x0, v8, (a1), v4 + th.vamoaddw.v v4, v8, (a1), v4, v0.t + th.vamoaddw.v x0, v8, (a1), v4, v0.t + th.vamoaddd.v v4, v8, (a1), v4, v0.t + th.vamoaddd.v x0, v8, (a1), v4, v0.t + th.vamoswapw.v v4, v8, (a1), v4 + th.vamoswapw.v x0, v8, (a1), v4 + th.vamoswapd.v v4, v8, (a1), v4 + th.vamoswapd.v x0, v8, (a1), v4 + th.vamoswapw.v v4, v8, (a1), v4, v0.t + th.vamoswapw.v x0, v8, (a1), v4, v0.t + th.vamoswapd.v v4, v8, (a1), v4, v0.t + th.vamoswapd.v x0, v8, (a1), v4, v0.t + + th.vamoxorw.v v4, v8, (a1), v4 + th.vamoxorw.v x0, v8, (a1), v4 + th.vamoxord.v v4, v8, (a1), v4 + th.vamoxord.v x0, v8, (a1), v4 + th.vamoxorw.v v4, v8, (a1), v4, v0.t + th.vamoxorw.v x0, v8, (a1), v4, v0.t + th.vamoxord.v v4, v8, (a1), v4, v0.t + th.vamoxord.v x0, v8, (a1), v4, v0.t + th.vamoandw.v v4, v8, (a1), v4 + th.vamoandw.v x0, v8, (a1), v4 + th.vamoandd.v v4, v8, (a1), v4 + th.vamoandd.v x0, v8, (a1), v4 + th.vamoandw.v v4, v8, (a1), v4, v0.t + th.vamoandw.v x0, v8, (a1), v4, v0.t + th.vamoandd.v v4, v8, (a1), v4, v0.t + th.vamoandd.v x0, v8, (a1), v4, v0.t + th.vamoorw.v v4, v8, (a1), v4 + th.vamoorw.v x0, v8, (a1), v4 + th.vamoord.v v4, v8, (a1), v4 + th.vamoord.v x0, v8, (a1), v4 + th.vamoorw.v v4, v8, (a1), v4, v0.t + th.vamoorw.v x0, v8, (a1), v4, v0.t + th.vamoord.v v4, v8, (a1), v4, v0.t + th.vamoord.v x0, v8, (a1), v4, v0.t + + th.vamominw.v v4, v8, (a1), v4 + th.vamominw.v x0, v8, (a1), v4 + th.vamomind.v v4, v8, (a1), v4 + th.vamomind.v x0, v8, (a1), v4 + th.vamominw.v v4, v8, (a1), v4, v0.t + th.vamominw.v x0, v8, (a1), v4, v0.t + th.vamomind.v v4, v8, (a1), v4, v0.t + th.vamomind.v x0, v8, (a1), v4, v0.t + th.vamomaxw.v v4, v8, (a1), v4 + th.vamomaxw.v x0, v8, (a1), v4 + th.vamomaxd.v v4, v8, (a1), v4 + th.vamomaxd.v x0, v8, (a1), v4 + th.vamomaxw.v v4, v8, (a1), v4, v0.t + th.vamomaxw.v x0, v8, (a1), v4, v0.t + th.vamomaxd.v v4, v8, (a1), v4, v0.t + th.vamomaxd.v x0, v8, (a1), v4, v0.t + th.vamominuw.v v4, v8, (a1), v4 + th.vamominuw.v x0, v8, (a1), v4 + th.vamominud.v v4, v8, (a1), v4 + th.vamominud.v x0, v8, (a1), v4 + th.vamominuw.v v4, v8, (a1), v4, v0.t + th.vamominuw.v x0, v8, (a1), v4, v0.t + th.vamominud.v v4, v8, (a1), v4, v0.t + th.vamominud.v x0, v8, (a1), v4, v0.t + th.vamomaxuw.v v4, v8, (a1), v4 + th.vamomaxuw.v x0, v8, (a1), v4 + th.vamomaxud.v v4, v8, (a1), v4 + th.vamomaxud.v x0, v8, (a1), v4 + th.vamomaxuw.v v4, v8, (a1), v4, v0.t + th.vamomaxuw.v x0, v8, (a1), v4, v0.t + th.vamomaxud.v v4, v8, (a1), v4, v0.t + th.vamomaxud.v x0, v8, (a1), v4, v0.t diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 6556de2..58618a4 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2849,7 +2849,42 @@ #define MASK_TH_VLSEG8HFFV 0xfdf0707f #define MATCH_TH_VLSEG8WFFV 0xf1006007 #define MASK_TH_VLSEG8WFFV 0xfdf0707f - +#define MATCH_TH_VAMOADDWV 0x0000602f +#define MASK_TH_VAMOADDWV 0xf800707f +#define MATCH_TH_VAMOADDDV 0x0000702f +#define MASK_TH_VAMOADDDV 0xf800707f +#define MATCH_TH_VAMOSWAPWV 0x0800602f +#define MASK_TH_VAMOSWAPWV 0xf800707f +#define MATCH_TH_VAMOSWAPDV 0x0800702f +#define MASK_TH_VAMOSWAPDV 0xf800707f +#define MATCH_TH_VAMOXORWV 0x2000602f +#define MASK_TH_VAMOXORWV 0xf800707f +#define MATCH_TH_VAMOXORDV 0x2000702f +#define MASK_TH_VAMOXORDV 0xf800707f +#define MATCH_TH_VAMOANDWV 0x6000602f +#define MASK_TH_VAMOANDWV 0xf800707f +#define MATCH_TH_VAMOANDDV 0x6000702f +#define MASK_TH_VAMOANDDV 0xf800707f +#define MATCH_TH_VAMOORWV 0x4000602f +#define MASK_TH_VAMOORWV 0xf800707f +#define MATCH_TH_VAMOORDV 0x4000702f +#define MASK_TH_VAMOORDV 0xf800707f +#define MATCH_TH_VAMOMINWV 0x8000602f +#define MASK_TH_VAMOMINWV 0xf800707f +#define MATCH_TH_VAMOMINDV 0x8000702f +#define MASK_TH_VAMOMINDV 0xf800707f +#define MATCH_TH_VAMOMAXWV 0xa000602f +#define MASK_TH_VAMOMAXWV 0xf800707f +#define MATCH_TH_VAMOMAXDV 0xa000702f +#define MASK_TH_VAMOMAXDV 0xf800707f +#define MATCH_TH_VAMOMINUWV 0xc000602f +#define MASK_TH_VAMOMINUWV 0xf800707f +#define MATCH_TH_VAMOMINUDV 0xc000702f +#define MASK_TH_VAMOMINUDV 0xf800707f +#define MATCH_TH_VAMOMAXUWV 0xe000602f +#define MASK_TH_VAMOMAXUWV 0xf800707f +#define MATCH_TH_VAMOMAXUDV 0xe000702f +#define MASK_TH_VAMOMAXUDV 0xf800707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index a26ef8a..3099c9e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -468,6 +468,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADMEMPAIR, INSN_CLASS_XTHEADSYNC, INSN_CLASS_XTHEADVECTOR, + INSN_CLASS_XTHEADZVAMO, INSN_CLASS_XVENTANACONDOPS, }; diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 71e4453..51b9956 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -2561,6 +2561,24 @@ const struct riscv_opcode riscv_opcodes[] = {"th.vlseg8huff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E16FFV, MASK_VLSEG8E16FFV, match_opcode, INSN_DREF }, {"th.vlseg8wuff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E32FFV, MASK_VLSEG8E32FFV, match_opcode, INSN_DREF }, {"th.vlseg8eff.v", 0, INSN_CLASS_XTHEADVECTOR, "Vd,0(s)Vm", MATCH_VLSEG8E64FFV, MASK_VLSEG8E64FFV, match_opcode, INSN_DREF }, +{"th.vamoaddw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDWV, MASK_TH_VAMOADDWV, match_opcode, INSN_DREF}, +{"th.vamoaddd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOADDDV, MASK_TH_VAMOADDDV, match_opcode, INSN_DREF}, +{"th.vamoswapw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPWV, MASK_TH_VAMOSWAPWV, match_opcode, INSN_DREF}, +{"th.vamoswapd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOSWAPDV, MASK_TH_VAMOSWAPDV, match_opcode, INSN_DREF}, +{"th.vamoxorw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORWV, MASK_TH_VAMOXORWV, match_opcode, INSN_DREF}, +{"th.vamoxord.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOXORDV, MASK_TH_VAMOXORDV, match_opcode, INSN_DREF}, +{"th.vamoandw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDWV, MASK_TH_VAMOANDWV, match_opcode, INSN_DREF}, +{"th.vamoandd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOANDDV, MASK_TH_VAMOANDDV, match_opcode, INSN_DREF}, +{"th.vamoorw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORWV, MASK_TH_VAMOORWV, match_opcode, INSN_DREF}, +{"th.vamoord.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOORDV, MASK_TH_VAMOORDV, match_opcode, INSN_DREF}, +{"th.vamominw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINWV, MASK_TH_VAMOMINWV, match_opcode, INSN_DREF}, +{"th.vamomind.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINDV, MASK_TH_VAMOMINDV, match_opcode, INSN_DREF}, +{"th.vamomaxw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXWV, MASK_TH_VAMOMAXWV, match_opcode, INSN_DREF}, +{"th.vamomaxd.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXDV, MASK_TH_VAMOMAXDV, match_opcode, INSN_DREF}, +{"th.vamominuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUWV, MASK_TH_VAMOMINUWV, match_opcode, INSN_DREF}, +{"th.vamominud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMINUDV, MASK_TH_VAMOMINUDV, match_opcode, INSN_DREF}, +{"th.vamomaxuw.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUWV, MASK_TH_VAMOMAXUWV, match_opcode, INSN_DREF}, +{"th.vamomaxud.v", 0, INSN_CLASS_XTHEADZVAMO, "Ve,Vt,(s),VfVm", MATCH_TH_VAMOMAXUDV, MASK_TH_VAMOMAXUDV, match_opcode, INSN_DREF}, /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ {"vt.maskc", 64, INSN_CLASS_XVENTANACONDOPS, "d,s,t", MATCH_VT_MASKC, MASK_VT_MASKC, match_opcode, 0 }, |