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-rw-r--r--bfd/ChangeLog7
-rw-r--r--bfd/elf32-arm.c37
-rw-r--r--ld/testsuite/ChangeLog6
-rw-r--r--ld/testsuite/ld-arm/arm-elf.exp4
-rw-r--r--ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d1107
-rw-r--r--ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s81
6 files changed, 1238 insertions, 4 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 3dc8434..dc696e7 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2010-08-25 Julian Brown <julian@codesourcery.com>
+
+ * elf32-arm.c (arm_stub_required_alignment): New.
+ (arm_build_one_stub): Use above to partition stubs.
+ (make_branch_to_a8_stub): Use arm_stub_a8_veneer_lwm not
+ arm_stub_a8_veneer_b_cond.
+
2010-08-25 Alan Modra <amodra@gmail.com>
* aout-arm.c (MY(bfd_reloc_type_lookup)): Use bfd_arch_bits_per_address.
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 0cd1e64..390c0af 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -3475,6 +3475,36 @@ static bfd_reloc_status_type elf32_arm_final_link_relocate
Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
const char *, int, struct elf_link_hash_entry *, bfd_boolean *, char **);
+static unsigned int
+arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
+{
+ switch (stub_type)
+ {
+ case arm_stub_a8_veneer_b_cond:
+ case arm_stub_a8_veneer_b:
+ case arm_stub_a8_veneer_bl:
+ return 2;
+
+ case arm_stub_long_branch_any_any:
+ case arm_stub_long_branch_v4t_arm_thumb:
+ case arm_stub_long_branch_thumb_only:
+ case arm_stub_long_branch_v4t_thumb_thumb:
+ case arm_stub_long_branch_v4t_thumb_arm:
+ case arm_stub_short_branch_v4t_thumb_arm:
+ case arm_stub_long_branch_any_arm_pic:
+ case arm_stub_long_branch_any_thumb_pic:
+ case arm_stub_long_branch_v4t_thumb_thumb_pic:
+ case arm_stub_long_branch_v4t_arm_thumb_pic:
+ case arm_stub_long_branch_v4t_thumb_arm_pic:
+ case arm_stub_long_branch_thumb_only_pic:
+ case arm_stub_a8_veneer_blx:
+ return 4;
+
+ default:
+ abort (); /* Should be unreachable. */
+ }
+}
+
static bfd_boolean
arm_build_one_stub (struct bfd_hash_entry *gen_entry,
void * in_arg)
@@ -3506,9 +3536,8 @@ arm_build_one_stub (struct bfd_hash_entry *gen_entry,
stub_sec = stub_entry->stub_sec;
if ((globals->fix_cortex_a8 < 0)
- != (stub_entry->stub_type >= arm_stub_a8_veneer_lwm))
- /* We have to do the a8 fixes last, as they are less aligned than
- the other veneers. */
+ != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
+ /* We have to do less-strictly-aligned fixes last. */
return TRUE;
/* Make a note of the offset within the stubs for this entry. */
@@ -13356,7 +13385,7 @@ make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
data = (struct a8_branch_to_stub_data *) in_arg;
if (stub_entry->target_section != data->writing_section
- || stub_entry->stub_type < arm_stub_a8_veneer_b_cond)
+ || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
return TRUE;
contents = data->contents;
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index eeed7da..85063c3 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2010-08-25 Julian Brown <julian@codesourcery.com>
+
+ * ld-arm/arm-elf.exp (armelftests): Add cortex-a8-fix-blx-bcond.s.
+ * ld-arm/cortex-a8-fix-blx-bcond.s: New.
+ * ld-arm/cortex-a8-fix-blx-bcond.d: New.
+
2010-08-24 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/x86-64.exp: Fix typos.
diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp
index c23da54..ef5f0f4 100644
--- a/ld/testsuite/ld-arm/arm-elf.exp
+++ b/ld/testsuite/ld-arm/arm-elf.exp
@@ -221,6 +221,10 @@ set armelftests {
"-EL -mcpu=cortex-a8" {cortex-a8-fix-hdr.s}
{{objdump -dr cortex-a8-fix-hdr.d}}
"cortex-a8-fix-hdr"}
+ {"Cortex-A8 erratum fix, blx.w and b<cond>.w together"
+ "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx-bcond.s}
+ {{objdump -dr cortex-a8-fix-blx-bcond.d}}
+ "cortex-a8-fix-blx-bcond"}
{"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}
{{objdump -sj.data gc-unwind.d}}
"gc-unwind"}
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d
new file mode 100644
index 0000000..692a606
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d
@@ -0,0 +1,1107 @@
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
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+ 9d84: f3af 8000 nop\.w
+ 9d88: f3af 8000 nop\.w
+ 9d8c: f3af 8000 nop\.w
+ 9d90: f3af 8000 nop\.w
+ 9d94: f3af 8000 nop\.w
+ 9d98: f3af 8000 nop\.w
+ 9d9c: f3af 8000 nop\.w
+ 9da0: f3af 8000 nop\.w
+ 9da4: f3af 8000 nop\.w
+ 9da8: f3af 8000 nop\.w
+ 9dac: f3af 8000 nop\.w
+ 9db0: f3af 8000 nop\.w
+ 9db4: f3af 8000 nop\.w
+ 9db8: f3af 8000 nop\.w
+ 9dbc: f3af 8000 nop\.w
+ 9dc0: f3af 8000 nop\.w
+ 9dc4: f3af 8000 nop\.w
+ 9dc8: f3af 8000 nop\.w
+ 9dcc: f3af 8000 nop\.w
+ 9dd0: f3af 8000 nop\.w
+ 9dd4: f3af 8000 nop\.w
+ 9dd8: f3af 8000 nop\.w
+ 9ddc: f3af 8000 nop\.w
+ 9de0: f3af 8000 nop\.w
+ 9de4: f3af 8000 nop\.w
+ 9de8: f3af 8000 nop\.w
+ 9dec: f3af 8000 nop\.w
+ 9df0: f3af 8000 nop\.w
+ 9df4: f3af 8000 nop\.w
+ 9df8: f3af 8000 nop\.w
+ 9dfc: f3af 8000 nop\.w
+ 9e00: f3af 8000 nop\.w
+ 9e04: f3af 8000 nop\.w
+ 9e08: f3af 8000 nop\.w
+ 9e0c: f3af 8000 nop\.w
+ 9e10: f3af 8000 nop\.w
+ 9e14: f3af 8000 nop\.w
+ 9e18: f3af 8000 nop\.w
+ 9e1c: f3af 8000 nop\.w
+ 9e20: f3af 8000 nop\.w
+ 9e24: f3af 8000 nop\.w
+ 9e28: f3af 8000 nop\.w
+ 9e2c: f3af 8000 nop\.w
+ 9e30: f3af 8000 nop\.w
+ 9e34: f3af 8000 nop\.w
+ 9e38: f3af 8000 nop\.w
+ 9e3c: f3af 8000 nop\.w
+ 9e40: f3af 8000 nop\.w
+ 9e44: f3af 8000 nop\.w
+ 9e48: f3af 8000 nop\.w
+ 9e4c: f3af 8000 nop\.w
+ 9e50: f3af 8000 nop\.w
+ 9e54: f3af 8000 nop\.w
+ 9e58: f3af 8000 nop\.w
+ 9e5c: f3af 8000 nop\.w
+ 9e60: f3af 8000 nop\.w
+ 9e64: f3af 8000 nop\.w
+ 9e68: f3af 8000 nop\.w
+ 9e6c: f3af 8000 nop\.w
+ 9e70: f3af 8000 nop\.w
+ 9e74: f3af 8000 nop\.w
+ 9e78: f3af 8000 nop\.w
+ 9e7c: f3af 8000 nop\.w
+ 9e80: f3af 8000 nop\.w
+ 9e84: f3af 8000 nop\.w
+ 9e88: f3af 8000 nop\.w
+ 9e8c: f3af 8000 nop\.w
+ 9e90: f3af 8000 nop\.w
+ 9e94: f3af 8000 nop\.w
+ 9e98: f3af 8000 nop\.w
+ 9e9c: f3af 8000 nop\.w
+ 9ea0: f3af 8000 nop\.w
+ 9ea4: f3af 8000 nop\.w
+ 9ea8: f3af 8000 nop\.w
+ 9eac: f3af 8000 nop\.w
+ 9eb0: f3af 8000 nop\.w
+ 9eb4: f3af 8000 nop\.w
+ 9eb8: f3af 8000 nop\.w
+ 9ebc: f3af 8000 nop\.w
+ 9ec0: f3af 8000 nop\.w
+ 9ec4: f3af 8000 nop\.w
+ 9ec8: f3af 8000 nop\.w
+ 9ecc: f3af 8000 nop\.w
+ 9ed0: f3af 8000 nop\.w
+ 9ed4: f3af 8000 nop\.w
+ 9ed8: f3af 8000 nop\.w
+ 9edc: f3af 8000 nop\.w
+ 9ee0: f3af 8000 nop\.w
+ 9ee4: f3af 8000 nop\.w
+ 9ee8: f3af 8000 nop\.w
+ 9eec: f3af 8000 nop\.w
+ 9ef0: f3af 8000 nop\.w
+ 9ef4: f3af 8000 nop\.w
+
+00009ef8 <arm_target>:
+ 9ef8: e0843005 add r3, r4, r5
+ 9efc: e12fff1e bx lr
+
+00009f00 <bl_insns>:
+ 9f00: bf00 nop
+ 9f02: eb01 0002 add\.w r0, r1, r2
+ 9f06: f7ff eff8 blx 9ef8 <arm_target>
+ 9f0a: eb01 0002 add\.w r0, r1, r2
+ 9f0e: f7ff eff4 blx 9ef8 <arm_target>
+ 9f12: eb01 0002 add\.w r0, r1, r2
+ 9f16: f7ff eff0 blx 9ef8 <arm_target>
+ 9f1a: eb01 0002 add\.w r0, r1, r2
+ 9f1e: f7ff efec blx 9ef8 <arm_target>
+ 9f22: eb01 0002 add\.w r0, r1, r2
+ 9f26: f7ff efe8 blx 9ef8 <arm_target>
+ 9f2a: eb01 0002 add\.w r0, r1, r2
+ 9f2e: f7ff efe4 blx 9ef8 <arm_target>
+ 9f32: eb01 0002 add\.w r0, r1, r2
+ 9f36: f7ff efe0 blx 9ef8 <arm_target>
+ 9f3a: eb01 0002 add\.w r0, r1, r2
+ 9f3e: f7ff efdc blx 9ef8 <arm_target>
+ 9f42: eb01 0002 add\.w r0, r1, r2
+ 9f46: f7ff efd8 blx 9ef8 <arm_target>
+ 9f4a: eb01 0002 add\.w r0, r1, r2
+ 9f4e: f7ff efd4 blx 9ef8 <arm_target>
+ 9f52: eb01 0002 add\.w r0, r1, r2
+ 9f56: f7ff efd0 blx 9ef8 <arm_target>
+ 9f5a: eb01 0002 add\.w r0, r1, r2
+ 9f5e: f7ff efcc blx 9ef8 <arm_target>
+ 9f62: eb01 0002 add\.w r0, r1, r2
+ 9f66: f7ff efc8 blx 9ef8 <arm_target>
+ 9f6a: eb01 0002 add\.w r0, r1, r2
+ 9f6e: f7ff efc4 blx 9ef8 <arm_target>
+ 9f72: eb01 0002 add\.w r0, r1, r2
+ 9f76: f7ff efc0 blx 9ef8 <arm_target>
+ 9f7a: eb01 0002 add\.w r0, r1, r2
+ 9f7e: f7ff efbc blx 9ef8 <arm_target>
+ 9f82: eb01 0002 add\.w r0, r1, r2
+ 9f86: f7ff efb8 blx 9ef8 <arm_target>
+ 9f8a: eb01 0002 add\.w r0, r1, r2
+ 9f8e: f7ff efb4 blx 9ef8 <arm_target>
+ 9f92: eb01 0002 add\.w r0, r1, r2
+ 9f96: f7ff efb0 blx 9ef8 <arm_target>
+ 9f9a: eb01 0002 add\.w r0, r1, r2
+ 9f9e: f7ff efac blx 9ef8 <arm_target>
+ 9fa2: eb01 0002 add\.w r0, r1, r2
+ 9fa6: f7ff efa8 blx 9ef8 <arm_target>
+ 9faa: eb01 0002 add\.w r0, r1, r2
+ 9fae: f7ff efa4 blx 9ef8 <arm_target>
+ 9fb2: eb01 0002 add\.w r0, r1, r2
+ 9fb6: f7ff efa0 blx 9ef8 <arm_target>
+ 9fba: eb01 0002 add\.w r0, r1, r2
+ 9fbe: f7ff ef9c blx 9ef8 <arm_target>
+ 9fc2: eb01 0002 add\.w r0, r1, r2
+ 9fc6: f7ff ef98 blx 9ef8 <arm_target>
+ 9fca: eb01 0002 add\.w r0, r1, r2
+ 9fce: f7ff ef94 blx 9ef8 <arm_target>
+ 9fd2: eb01 0002 add\.w r0, r1, r2
+ 9fd6: f7ff ef90 blx 9ef8 <arm_target>
+ 9fda: eb01 0002 add\.w r0, r1, r2
+ 9fde: f7ff ef8c blx 9ef8 <arm_target>
+ 9fe2: eb01 0002 add\.w r0, r1, r2
+ 9fe6: f7ff ef88 blx 9ef8 <arm_target>
+ 9fea: eb01 0002 add\.w r0, r1, r2
+ 9fee: f7ff ef84 blx 9ef8 <arm_target>
+ 9ff2: eb01 0002 add\.w r0, r1, r2
+ 9ff6: f7ff ef80 blx 9ef8 <arm_target>
+ 9ffa: eb01 0002 add\.w r0, r1, r2
+ 9ffe: f000 e804 blx a008 <bl_insns\+0x108>
+ a002: 4770 bx lr
+ a004: f3af 8000 nop\.w
+ a008: eaffffba b 9ef8 <arm_target>
+ a00c: d101 bne\.n a012 <bl_insns\+0x112>
+ a00e: f7fe bff8 b\.w 9002 <_start\+0x102>
+ a012: f7fe bfe6 b\.w 8fe2 <_start\+0xe2>
diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s b/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s
new file mode 100644
index 0000000..cb40fb4
--- /dev/null
+++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s
@@ -0,0 +1,81 @@
+ .syntax unified
+ .cpu cortex-a8
+ .thumb
+ .text
+
+ @ expansion 32 bytes
+ .macro bw1
+1:
+ add.w r0, r1, r2
+ blx.w arm_target
+ add.w r0, r1, r2
+ blx.w arm_target
+ add.w r0, r1, r2
+ blx.w arm_target
+ add.w r0, r1, r2
+ blx.w arm_target
+ .endm
+
+ @ expansion 128 bytes
+ .macro bw2
+ bw1
+ bw1
+ bw1
+ bw1
+ .endm
+
+ @ expansion 32 bytes
+ .macro bw3
+1:
+ add.w r0, r1, r2
+ bne.w 1b
+ add.w r0, r1, r2
+ bne.w 1b
+ add.w r0, r1, r2
+ bne.w 1b
+ add.w r0, r1, r2
+ bne.w 1b
+ .endm
+
+ @ expansion 128 bytes
+ .macro bw4
+ bw3
+ bw3
+ bw3
+ bw3
+ .endm
+
+ .align 3
+ .global _start
+
+ .thumb
+ .thumb_func
+ .type _start, %function
+_start:
+ nop
+
+ @ Trigger Cortex-A8 erratum workaround with b<cond> instructions.
+ bw4
+ bw4
+
+ nop
+
+ .rept 957
+ nop.w
+ .endr
+
+ .arm
+arm_target:
+ add r3, r4, r5
+ bx lr
+
+ .thumb
+bl_insns:
+
+ nop
+
+ @ ...and again with bl instructions.
+ bw2
+ bw2
+
+ bx lr
generated by cgit v1.1 at 2024-11-27 17:21:10 +0000