diff options
-rw-r--r-- | gas/config/tc-ppc.c | 4 | ||||
-rw-r--r-- | gas/testsuite/gas/ppc/prefix-reloc.d | 2 | ||||
-rw-r--r-- | gas/testsuite/gas/ppc/simpshft.d | 26 | ||||
-rw-r--r-- | include/opcode/ppc.h | 8 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/elfv2so.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/notoc.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/notoc3.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/tlsdesc2.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/tlsget.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/tlsget2.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/tlsopt5.d | 2 | ||||
-rw-r--r-- | ld/testsuite/ld-powerpc/tlsopt6.d | 2 | ||||
-rw-r--r-- | opcodes/ppc-opc.c | 264 |
13 files changed, 274 insertions, 46 deletions
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c index 89bc7d3..cf11f7a 100644 --- a/gas/config/tc-ppc.c +++ b/gas/config/tc-ppc.c @@ -1589,10 +1589,10 @@ insn_validate (const struct powerpc_opcode *op) val = -1; if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) val = -val; - else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) - val += 1; mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); } + else if (operand->shift == (int) PPC_OPSHIFT_SH6) + mask = (0x1f << 11) | 0x2; else if (operand->shift >= 0) mask = operand->bitm << operand->shift; else diff --git a/gas/testsuite/gas/ppc/prefix-reloc.d b/gas/testsuite/gas/ppc/prefix-reloc.d index b442419..e79f4aa 100644 --- a/gas/testsuite/gas/ppc/prefix-reloc.d +++ b/gas/testsuite/gas/ppc/prefix-reloc.d @@ -10,7 +10,7 @@ Disassembly of section \.text: 0: (00 00 00 06|06 00 00 00) pli r9,0 4: (00 00 20 39|39 20 00 00) 0: R_PPC64_D34_HA30 ext - 8: (46 17 29 79|79 29 17 46) rldicr r9,r9,34,29 + 8: (46 17 29 79|79 29 17 46) sldi r9,r9,34 c: (00 00 00 06|06 00 00 00) paddi r9,r9,0 10: (00 00 29 39|39 29 00 00) c: R_PPC64_D34_LO ext diff --git a/gas/testsuite/gas/ppc/simpshft.d b/gas/testsuite/gas/ppc/simpshft.d index b4cccd5..b88752c8 100644 --- a/gas/testsuite/gas/ppc/simpshft.d +++ b/gas/testsuite/gas/ppc/simpshft.d @@ -7,19 +7,19 @@ Disassembly of section .text: 0+ <.text>: - 0: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63 + 0: (e0 0f 64 78|78 64 0f e0) srdi r4,r3,63 4: (0e f8 83 78|78 83 f8 0e) rldimi r3,r4,63,0 - 8: (e4 45 a5 78|78 a5 45 e4) rldicr r5,r5,8,55 + 8: (e4 45 a5 78|78 a5 45 e4) sldi r5,r5,8 c: (20 00 64 78|78 64 00 20) clrldi r4,r3,32 10: (fe 0f 64 54|54 64 0f fe) rlwinm r4,r3,1,31,31 14: (00 f8 83 50|50 83 f8 00) rlwimi r3,r4,31,0,0 18: (2e 40 a5 54|54 a5 40 2e) rlwinm r5,r5,8,0,23 1c: (3e 04 64 54|54 64 04 3e) clrlwi r4,r3,16 - 20: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0 - 24: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63 - 28: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0 + 20: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63 + 24: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0 + 28: (06 f8 64 78|78 64 f8 06) sldi r4,r3,63 2c: (e6 ff 64 78|78 64 ff e6) rldicr r4,r3,63,63 - 30: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1 + 30: (42 f8 64 78|78 64 f8 42) srdi r4,r3,1 34: (e2 ff 64 78|78 64 ff e2) rldicl r4,r3,63,63 38: (0c 00 64 78|78 64 00 0c) rldimi r4,r3,0,0 3c: (0c 08 64 78|78 64 08 0c) rldimi r4,r3,1,0 @@ -32,17 +32,17 @@ Disassembly of section .text: 58: (02 f8 64 78|78 64 f8 02) rotldi r4,r3,63 5c: (00 08 64 78|78 64 08 00) rotldi r4,r3,1 60: (10 20 65 78|78 65 20 10) rotld r5,r3,r4 - 64: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63 - 68: (06 f8 64 78|78 64 f8 06) rldicr r4,r3,63,0 + 64: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0 + 68: (06 f8 64 78|78 64 f8 06) sldi r4,r3,63 6c: (00 00 64 78|78 64 00 00) rotldi r4,r3,0 - 70: (42 f8 64 78|78 64 f8 42) rldicl r4,r3,63,1 - 74: (e0 0f 64 78|78 64 0f e0) rldicl r4,r3,1,63 + 70: (42 f8 64 78|78 64 f8 42) srdi r4,r3,1 + 74: (e0 0f 64 78|78 64 0f e0) srdi r4,r3,63 78: (00 00 64 78|78 64 00 00) rotldi r4,r3,0 7c: (40 00 64 78|78 64 00 40) clrldi r4,r3,1 80: (e0 07 64 78|78 64 07 e0) clrldi r4,r3,63 - 84: (e4 07 64 78|78 64 07 e4) rldicr r4,r3,0,63 - 88: (a4 07 64 78|78 64 07 a4) rldicr r4,r3,0,62 - 8c: (04 00 64 78|78 64 00 04) rldicr r4,r3,0,0 + 84: (e4 07 64 78|78 64 07 e4) clrrdi r4,r3,0 + 88: (a4 07 64 78|78 64 07 a4) clrrdi r4,r3,1 + 8c: (04 00 64 78|78 64 00 04) clrrdi r4,r3,63 90: (08 00 64 78|78 64 00 08) rldic r4,r3,0,0 94: (48 00 64 78|78 64 00 48) rldic r4,r3,0,1 98: (e8 07 64 78|78 64 07 e8) rldic r4,r3,0,63 diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index a236b6b..463965d 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -336,9 +336,11 @@ extern const struct powerpc_operand powerpc_operands[]; extern const unsigned int num_powerpc_operands; /* Use with the shift field of a struct powerpc_operand to indicate - that BITM and SHIFT cannot be used to determine where the operand - goes in the insn. */ -#define PPC_OPSHIFT_INV (-1U << 31) + that BITM and SHIFT cannot be used to determine where the operand + goes in the insn. */ +#define PPC_OPSHIFT_INV (1U << 30) +/* A special case, 6-bit SH field. */ +#define PPC_OPSHIFT_SH6 (2U << 30) /* Values defined for the flags field of a struct powerpc_operand. Keep the register bits low: They need to fit in an unsigned short. */ diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d index 4018f05..0005710 100644 --- a/ld/testsuite/ld-powerpc/elfv2so.d +++ b/ld/testsuite/ld-powerpc/elfv2so.d @@ -80,7 +80,7 @@ Disassembly of section \.text: .*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11 .*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44 .*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\) -.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2 +.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2 .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\) .*: (4e 80 04 20|20 04 80 4e) bctr diff --git a/ld/testsuite/ld-powerpc/notoc.d b/ld/testsuite/ld-powerpc/notoc.d index 3555be7..69f1721 100644 --- a/ld/testsuite/ld-powerpc/notoc.d +++ b/ld/testsuite/ld-powerpc/notoc.d @@ -23,7 +23,7 @@ Disassembly of section \.text: .*: (a6 03 88 7d|7d 88 03 a6) mtlr r12 .*: (ff 7f 80 3d|3d 80 7f ff) lis r12,32767 .*: (ff ff 8c 61|61 8c ff ff) ori r12,r12,65535 -.*: (c6 07 9c 79|79 9c 07 c6) rldicr r28,r12,32,31 +.*: (c6 07 9c 79|79 9c 07 c6) sldi r28,r12,32 .*: (ff ef 8c 65|65 8c ef ff) oris r12,r12,61439 .*: (28 ff 8c 61|61 8c ff 28) ori r12,r12,65320 .*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12 diff --git a/ld/testsuite/ld-powerpc/notoc3.d b/ld/testsuite/ld-powerpc/notoc3.d index 134bba3..24cf9bb 100644 --- a/ld/testsuite/ld-powerpc/notoc3.d +++ b/ld/testsuite/ld-powerpc/notoc3.d @@ -20,7 +20,7 @@ Disassembly of section \.text: .*: (00 00 6b 61|61 6b 00 00) ori r11,r11,0 .*: (ff ef 13 06|06 13 ef ff) pla r12,-268435736 # 0 .*: (e8 fe 80 39|39 80 fe e8) -.*: (46 17 6b 79|79 6b 17 46) rldicr r11,r11,34,29 +.*: (46 17 6b 79|79 6b 17 46) sldi r11,r11,34 .*: (14 62 8b 7d|7d 8b 62 14) add r12,r11,r12 .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 .*: (20 04 80 4e|4e 80 04 20) bctr diff --git a/ld/testsuite/ld-powerpc/tlsdesc2.d b/ld/testsuite/ld-powerpc/tlsdesc2.d index c271c94..cd2663a 100644 --- a/ld/testsuite/ld-powerpc/tlsdesc2.d +++ b/ld/testsuite/ld-powerpc/tlsdesc2.d @@ -59,7 +59,7 @@ Disassembly of section \.text: .*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11 .*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44 .*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\) -.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2 +.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2 .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\) .*: (4e 80 04 20|20 04 80 4e) bctr diff --git a/ld/testsuite/ld-powerpc/tlsget.d b/ld/testsuite/ld-powerpc/tlsget.d index f419fca..f16febc 100644 --- a/ld/testsuite/ld-powerpc/tlsget.d +++ b/ld/testsuite/ld-powerpc/tlsget.d @@ -80,7 +80,7 @@ Disassembly of section \.text: .*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11 .*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44 .*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\) -.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2 +.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2 .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\) .*: (4e 80 04 20|20 04 80 4e) bctr diff --git a/ld/testsuite/ld-powerpc/tlsget2.d b/ld/testsuite/ld-powerpc/tlsget2.d index 13dc64b..910e048 100644 --- a/ld/testsuite/ld-powerpc/tlsget2.d +++ b/ld/testsuite/ld-powerpc/tlsget2.d @@ -67,7 +67,7 @@ Disassembly of section \.text: .*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11 .*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44 .*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\) -.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2 +.*: (78 00 f0 82|82 f0 00 78) srdi r0,r0,2 .*: (7d 89 03 a6|a6 03 89 7d) mtctr r12 .*: (e9 6b 00 08|08 00 6b e9) ld r11,8\(r11\) .*: (4e 80 04 20|20 04 80 4e) bctr diff --git a/ld/testsuite/ld-powerpc/tlsopt5.d b/ld/testsuite/ld-powerpc/tlsopt5.d index efd6deb..2ea1f7f 100644 --- a/ld/testsuite/ld-powerpc/tlsopt5.d +++ b/ld/testsuite/ld-powerpc/tlsopt5.d @@ -55,7 +55,7 @@ Disassembly of section \.text: .*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11 .*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44 .*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\) -.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2 +.*: (82 f0 00 78|78 00 f0 82) srdi r0,r0,2 .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 .*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\) .*: (20 04 80 4e|4e 80 04 20) bctr diff --git a/ld/testsuite/ld-powerpc/tlsopt6.d b/ld/testsuite/ld-powerpc/tlsopt6.d index 15def71..38a2068 100644 --- a/ld/testsuite/ld-powerpc/tlsopt6.d +++ b/ld/testsuite/ld-powerpc/tlsopt6.d @@ -73,7 +73,7 @@ Disassembly of section \.text: .*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11 .*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44 .*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\) -.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2 +.*: (82 f0 00 78|78 00 f0 82) srdi r0,r0,2 .*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 .*: (08 00 6b e9|e9 6b 00 08) ld r11,8\(r11\) .*: (20 04 80 4e|4e 80 04 20) bctr diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index a424dd9..2084487 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -1166,6 +1166,63 @@ extract_mb6 (uint64_t insn, return ((insn >> 6) & 0x1f) | (insn & 0x20); } +/* The n operand of extrdi, which sets MB field. */ + +static uint64_t +insert_erdn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_mb6 (insn, -value, dialect, errmsg); +} + +static int64_t +extract_erdn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + return (~extract_mb6 (insn, dialect, invalid) & 63) + 1; +} + +/* The n operand of extldi, which sets ME field. */ + +static uint64_t +insert_eldn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_mb6 (insn, value - 1, dialect, errmsg); +} + +static int64_t +extract_eldn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + return extract_mb6 (insn, dialect, invalid) + 1; +} + +/* The n operand of clrrdi, which set ME field. */ + +static uint64_t +insert_crdn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_mb6 (insn, 63 - value, dialect, errmsg); +} + +static int64_t +extract_crdn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + return 63 - extract_mb6 (insn, dialect, invalid); +} + /* The NB field in an X form instruction. The value 32 is stored as 0. */ @@ -1551,6 +1608,143 @@ extract_sh6 (uint64_t insn, return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); } +/* The n operand of rotrdi, which writes to SH field. */ + +static uint64_t +insert_rrdn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + return insert_sh6 (insn, -value, dialect, errmsg); +} + +static int64_t +extract_rrdn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + return -extract_sh6 (insn, dialect, invalid) & 63; +} + +/* The n operand of sldi, which writes to SH and ME fields. */ + +static uint64_t +insert_sldn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + insn = insert_sh6 (insn, value, dialect, errmsg); + return insert_crdn (insn, value, dialect, errmsg); +} + +static int64_t +extract_sldn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + int64_t sh = extract_sh6 (insn, dialect, invalid); + int64_t me = extract_crdn (insn, dialect, invalid); + if (me != sh) + *invalid = 1; + return sh; +} + +/* The n operand of srdi, which writes to SH and MB fields. */ + +static uint64_t +insert_srdn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + insn = insert_rrdn (insn, value, dialect, errmsg); + return insert_mb6 (insn, value, dialect, errmsg); +} + +static int64_t +extract_srdn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + int64_t sh = extract_rrdn (insn, dialect, invalid); + int64_t mb = extract_mb6 (insn, dialect, invalid); + if (mb != sh) + *invalid = 1; + return sh; +} + +/* The b operand of extrdi, which sets SH field. */ + +static uint64_t +insert_erdb (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + int64_t n = extract_erdn (insn, dialect, NULL); + return insert_sh6 (insn, value + n, dialect, errmsg); +} + +static int64_t +extract_erdb (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + int64_t sh = extract_sh6 (insn, dialect, invalid); + int64_t n = extract_erdn (insn, dialect, invalid); + return (sh - n) & 63; +} + +/* The b and n operands of clrlsldi. */ + +static uint64_t +insert_csldn (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + uint64_t mb6 = 0x3f << 5; + int64_t b = extract_mb6 (insn, dialect, NULL); + insn = insert_mb6 (insn & ~mb6, b - value, dialect, errmsg); + return insert_sh6 (insn, value, dialect, errmsg); +} + +static int64_t +extract_csldb (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + int64_t sh = extract_sh6 (insn, dialect, invalid); + int64_t mb = extract_mb6 (insn, dialect, invalid); + return (mb + sh) & 63; +} + +/* The b and n operands of insrdi. */ + +static uint64_t +insert_irdb (uint64_t insn, + int64_t value, + ppc_cpu_t dialect, + const char **errmsg) +{ + uint64_t sh6 = (0x1f << 11) | 2; + int64_t n = extract_sh6 (insn, dialect, NULL); + insn = insert_sh6 (insn & ~sh6, -(value + n), dialect, errmsg); + return insert_mb6 (insn, value, dialect, errmsg); +} + +static int64_t +extract_irdn (uint64_t insn, + ppc_cpu_t dialect, + int *invalid) +{ + int64_t sh = extract_sh6 (insn, dialect, invalid); + int64_t mb = extract_mb6 (insn, dialect, invalid); + return (~(mb + sh) & 63) + 1; +} + /* The SPR field in an XFX form instruction. This is flipped--the lower 5 bits are stored in the upper 5 and vice- versa. */ @@ -2754,9 +2948,18 @@ const struct powerpc_operand powerpc_operands[] = #define MB6_MASK (0x3f << 5) { 0x3f, 5, insert_mb6, extract_mb6, 0 }, +#define ELDn MB6 + 1 + { 0x3f, 5, insert_eldn, extract_eldn, PPC_OPERAND_PLUS1 }, + +#define ERDn ELDn + 1 + { 0x3f, 5, insert_erdn, extract_erdn, 0 }, + +#define CRDn ERDn + 1 + { 0x3f, 5, insert_crdn, extract_crdn, 0 }, + /* The NB field in an X form instruction. The value 32 is stored as 0. */ -#define NB MB6 + 1 +#define NB CRDn + 1 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, /* The NBI field in an lswi instruction, which has special value @@ -2942,9 +3145,33 @@ const struct powerpc_operand powerpc_operands[] = #define SH6_MASK ((0x1f << 11) | (1 << 1)) { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, +#define RRDn SH6 + 1 + { 0x3f, PPC_OPSHIFT_INV, insert_rrdn, extract_rrdn, 0 }, + +#define SLDn RRDn + 1 + { 0x3f, PPC_OPSHIFT_INV, insert_sldn, extract_sldn, 0 }, + +#define SRDn SLDn + 1 + { 0x3f, PPC_OPSHIFT_INV, insert_srdn, extract_srdn, 0 }, + +#define ERDb SRDn + 1 + { 0x3f, PPC_OPSHIFT_INV, insert_erdb, extract_erdb, 0 }, + +#define CSLDn ERDb + 1 + { 0x3f, PPC_OPSHIFT_SH6, insert_csldn, extract_sh6, 0 }, + +#define CSLDb CSLDn + 1 + { 0x3f, 5, insert_mb6, extract_csldb, 0 }, + +#define IRDn CSLDb + 1 + { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_irdn, PPC_OPERAND_PLUS1 }, + +#define IRDb IRDn + 1 + { 0x3f, 5, insert_irdb, extract_mb6, 0 }, + /* The SH field of some variants of the tlbre and tlbwe instructions, and the ELEV field of the e_sc instruction. */ -#define SHO SH6 + 1 +#define SHO IRDb + 1 #define ELEV SHO { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, @@ -6244,20 +6471,36 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, {"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}}, +{"rotrdi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}}, {"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}}, +{"srdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}}, {"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, +{"extrdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}}, {"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}}, +{"rotrdi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}}, {"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}}, +{"srdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}}, {"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, +{"extrdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}}, +{"clrrdi", MD(30,1,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}}, +{"sldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}}, {"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, +{"extldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}}, +{"clrrdi.", MD(30,1,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}}, +{"sldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}}, {"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, +{"extldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}}, {"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, +{"clrlsldi", MD(30,2,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}}, {"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, +{"clrlsldi.", MD(30,2,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}}, {"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, +{"insrdi", MD(30,3,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}}, {"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, +{"insrdi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}}, {"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}}, {"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, @@ -9949,23 +10192,6 @@ const unsigned int vle_num_opcodes = support extracting the whole word (32 bits in this case). */ const struct powerpc_macro powerpc_macros[] = { -{"extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1"}, -{"extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1"}, -{"extrdi", 4, PPC64, "rldicl %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, -{"extrdi.", 4, PPC64, "rldicl. %0,%1,((%2)+(%3))&((%2)+(%3)<>64),64-(%2)"}, -{"insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3"}, -{"insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3"}, -{"rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0"}, -{"rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0"}, -{"sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)"}, -{"sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)"}, -{"srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2"}, -{"srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2"}, -{"clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)"}, -{"clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)"}, -{"clrlsldi", 4, PPC64, "rldic %0,%1,%3,(%2)-(%3)"}, -{"clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)"}, - {"extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1"}, {"extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1"}, {"extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31"}, |