diff options
| -rw-r--r-- | binutils/ChangeLog | 4 | ||||
| -rw-r--r-- | binutils/readelf.c | 4 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/nds32.h | 10 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 18 | ||||
| -rw-r--r-- | opcodes/nds32-asm.c | 2030 | ||||
| -rw-r--r-- | opcodes/nds32-asm.h | 111 | ||||
| -rw-r--r-- | opcodes/nds32-dis.c | 2010 |
8 files changed, 2344 insertions, 1847 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index ea63218..c55382e 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,7 @@ +2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * readelf.c (decode_NDS32_machine_flags): Display ABI2 FP+. + 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> Matthew Fortune <matthew.fortune@imgtec.com> diff --git a/binutils/readelf.c b/binutils/readelf.c index f7eaf7c..ef3a68d 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -2326,7 +2326,8 @@ decode_NDS32_machine_flags (unsigned e_flags, char buf[], size_t size) "ABI v1", /* use r0 as return register */ "ABI v2", /* use r0 as return register and don't reserve 24 bytes for arguments */ "ABI v2fp", /* for FPU */ - "AABI" + "AABI", + "ABI2 FP+" }; static const char *VER_STRINGS[] = { @@ -2357,6 +2358,7 @@ decode_NDS32_machine_flags (unsigned e_flags, char buf[], size_t size) case E_NDS_ABI_V2: case E_NDS_ABI_V2FP: case E_NDS_ABI_AABI: + case E_NDS_ABI_V2FP_PLUS: /* In case there are holes in the array. */ r += snprintf (buf + r, size - r, ", %s", ABI_STRINGS[abi >> EF_NDS_ABI_SHIFT]); break; diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index c7425bb..e16393f 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,7 @@ +2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * nds32.h: Add new opcode declaration. + 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> Matthew Fortune <matthew.fortune@imgtec.com> diff --git a/include/opcode/nds32.h b/include/opcode/nds32.h index 47b1c49..9592be6 100644 --- a/include/opcode/nds32.h +++ b/include/opcode/nds32.h @@ -29,6 +29,7 @@ #define REG_R16 16 #define REG_R20 20 #define REG_TA 15 +#define REG_TP 27 #define REG_FP 28 #define REG_GP 29 #define REG_LP 30 @@ -358,12 +359,13 @@ enum n32_opcodes N32_ALU2_SUB_SC, N32_ALU2_ADD_WC, N32_ALU2_SUB_WC, - N32_ALU2_0x14, + N32_ALU2_KMxy, N32_ALU2_0x15, N32_ALU2_0x16, N32_ALU2_FFZMISM, - N32_ALU2_QADD = 0x18, - N32_ALU2_QSUB, + N32_ALU2_KADD = 0x18, + N32_ALU2_KSUB, + N32_ALU2_KSLRA, N32_ALU2_MFUSR = 0x20, N32_ALU2_MTUSR, N32_ALU2_0x22, @@ -459,7 +461,7 @@ enum n32_opcodes N32_MISC_TLBOP, N32_MISC_0xf, - /* bit[0;4] */ + /* bit[0:4] */ N32_SIMD_PBSAD = 0, N32_SIMD_PBSADA = 1, diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ecab314..42e09dd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,21 @@ +2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i, + keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2, + keyword_aridxi): Add audio ISA extension. + (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr, + keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st, + keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope + for nds32-dis.c using. + (build_opcode_syntax): Remove dead code. + (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end, + parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr, + parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA + operand parser. + * nds32-asm.h: Declare. + * nds32-dis.c: Use array nds32_opcodes to disassemble instead of + decoding by switch. + 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> Matthew Fortune <matthew.fortune@imgtec.com> diff --git a/opcodes/nds32-asm.c b/opcodes/nds32-asm.c index 83b2547..1c5e691 100644 --- a/opcodes/nds32-asm.c +++ b/opcodes/nds32-asm.c @@ -17,7 +17,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA.*/ + 02110-1301, USA. */ #include <config.h> @@ -38,7 +38,7 @@ /* There at at most MAX_LEX_NUM lexical elements in a syntax. */ #define MAX_LEX_NUM 32 /* A operand in syntax string should be at most this long. */ -#define MAX_LEX_LEN 32 +#define MAX_LEX_LEN 64 /* The max length of a keyword can be. */ #define MAX_KEYWORD_LEN 32 /* This LEX is a plain char or operand. */ @@ -50,59 +50,42 @@ #define USRIDX(group, usr) ((group) | ((usr) << 5)) #define SRIDX(major, minor, ext) \ - (((major) << 7) | ((minor) << 3) | (ext)) + (((major) << 7) | ((minor) << 3) | (ext)) +static int parse_re (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); static int parse_re2 (struct nds32_asm_desc *, struct nds32_asm_insn *, char **, int64_t *); static int parse_fe5 (struct nds32_asm_desc *, struct nds32_asm_insn *, char **, int64_t *); static int parse_pi5 (struct nds32_asm_desc *, struct nds32_asm_insn *, char **, int64_t *); +static int parse_aext_reg (char **, int *, int); +static int parse_a30b20 (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_rt21 (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_rte_start (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_rte_end (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_rte69_start (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_rte69_end (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_im5_ip (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_im5_mr (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_im6_ip (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_im6_iq (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_im6_mr (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); +static int parse_im6_ms (struct nds32_asm_desc *, struct nds32_asm_insn *, + char **, int64_t *); - -enum -{ - /* This is a field (operand) of just a separator char. */ - SYN_FIELD = 0x100, - - /* This operand is used for input or output. (define or use) */ - SYN_INPUT = 0x1000, - SYN_OUTPUT = 0x2000, - SYN_LOPT = 0x4000, - SYN_ROPT = 0x8000, - - /* Hardware resources. */ - HW_GPR = 0, - HW_USR, - HW_DXR, - HW_SR, - HW_FSR, - HW_FDR, - HW_CP, /* Co-processor ID. */ - HW_CPR, /* Co-processor registers. */ - HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */ - HW_ABM, /* [ab]m? flag for LSMWZB. */ - HW_DTITON, - HW_DTITOFF, - HW_DPREF_ST, - HW_CCTL_ST0, - HW_CCTL_ST1, - HW_CCTL_ST2, - HW_CCTL_ST3, - HW_CCTL_ST4, - HW_CCTL_ST5, - HW_CCTL_LV, - HW_TLBOP_ST, - HW_STANDBY_ST, - HW_MSYNC_ST, - _HW_LAST, - /* TODO: Maybe we should add a new type to distinguish address and - const int. Only the former allows symbols and relocations. */ - HW_INT, - HW_UINT -}; - - /* These are operand prefixes for input/output semantic. % input @@ -112,12 +95,13 @@ enum Field table for operands and bit-fields. */ -static const field_t operand_fields[] = +const field_t operand_fields[] = { {"rt", 20, 5, 0, HW_GPR, NULL}, {"ra", 15, 5, 0, HW_GPR, NULL}, {"rb", 10, 5, 0, HW_GPR, NULL}, {"rd", 5, 5, 0, HW_GPR, NULL}, + {"re", 10, 5, 0, HW_GPR, parse_re}, /* lmw smw lmwa smwa. */ {"fst", 20, 5, 0, HW_FSR, NULL}, {"fsa", 15, 5, 0, HW_FSR, NULL}, {"fsb", 10, 5, 0, HW_FSR, NULL}, @@ -132,7 +116,7 @@ static const field_t operand_fields[] = {"usr", 10, 10, 0, HW_USR, NULL}, /* User Special Registers. */ {"sr", 10, 10, 0, HW_SR, NULL}, /* System Registers. */ {"ridx", 10, 10, 0, HW_UINT, NULL}, /* Raw value for mfusr/mfsr. */ - {"enb4", 6, 9, 0, HW_UINT, NULL}, /* Enable4 for LSMW. */ + {"enb4", 6, 4, 0, HW_UINT, NULL}, /* Enable4 for LSMW. */ {"swid", 5, 15, 0, HW_UINT, NULL}, {"stdby_st", 5, 2, 0, HW_STANDBY_ST, NULL}, {"tlbop_st", 5, 5, 0, HW_TLBOP_ST, NULL}, @@ -147,7 +131,7 @@ static const field_t operand_fields[] = {"cctl_lv", 10, 1, 0, HW_CCTL_LV, NULL}, {"msync_st", 5, 3, 0, HW_MSYNC_ST, NULL}, {"msync_stx", 5, 3, 0, HW_UINT, NULL}, - {"dpref_st", 20, 5, 0, HW_DPREF_ST, NULL}, + {"dpref_st", 20, 4, 0, HW_DPREF_ST, NULL}, {"rt5", 5, 5, 0, HW_GPR, NULL}, {"ra5", 0, 5, 0, HW_GPR, NULL}, {"rt4", 5, 4, 0, HW_GPR, NULL}, @@ -155,8 +139,8 @@ static const field_t operand_fields[] = {"rt38", 8, 3, 0, HW_GPR, NULL}, /* rt3 used in 38 form. */ {"ra3", 3, 3, 0, HW_GPR, NULL}, {"rb3", 0, 3, 0, HW_GPR, NULL}, - {"rt5e", 4, 4, 1, HW_GPR, NULL}, /* movd44 */ - {"ra5e", 0, 4, 1, HW_GPR, NULL}, /* movd44 */ + {"rt5e", 4, 4, 1, HW_GPR, NULL}, /* for movd44. */ + {"ra5e", 0, 4, 1, HW_GPR, NULL}, /* for movd44. */ {"re2", 5, 2, 0, HW_GPR, parse_re2}, /* re in push25/pop25. */ {"fe5", 0, 5, 2, HW_UINT, parse_fe5}, /* imm5u in lwi45.fe. */ {"pi5", 0, 5, 0, HW_UINT, parse_pi5}, /* imm5u in movpi45. */ @@ -186,9 +170,10 @@ static const field_t operand_fields[] = {"i5u", 0, 5, 0, HW_UINT, NULL}, {"ib5u", 10, 5, 0, HW_UINT, NULL}, /* imm5 field in ALU. */ {"ib5s", 10, 5, 0, HW_INT, NULL}, /* imm5 field in ALU. */ - {"i9u", 0, 9, 0, HW_UINT, NULL}, /* break16/ex9.it */ - {"ia3u", 3, 3, 0, HW_UINT, NULL}, /* bmski33, fexti33 */ + {"i9u", 0, 9, 0, HW_UINT, NULL}, /* for ex9.it. */ + {"ia3u", 3, 3, 0, HW_UINT, NULL}, /* for bmski33, fexti33. */ {"i8u", 0, 8, 0, HW_UINT, NULL}, + {"ib8u", 7, 8, 0, HW_UINT, NULL}, /* for ffbi. */ {"i15u", 0, 15, 0, HW_UINT, NULL}, {"i20u", 0, 20, 0, HW_UINT, NULL}, {"i3u1", 0, 3, 1, HW_UINT, NULL}, @@ -196,14 +181,37 @@ static const field_t operand_fields[] = {"i3u2", 0, 3, 2, HW_UINT, NULL}, {"i6u2", 0, 6, 2, HW_UINT, NULL}, {"i7u2", 0, 7, 2, HW_UINT, NULL}, - {"i5u3", 0, 5, 3, HW_UINT, NULL}, /* pop25/pop25 */ - {"i15s3", 0, 15, 3, HW_UINT, NULL}, /* dprefi.d */ - + {"i5u3", 0, 5, 3, HW_UINT, NULL}, /* for pop25/pop25. */ + {"i15s3", 0, 15, 3, HW_INT, NULL}, /* for dprefi.d. */ + + {"a_rt", 15, 5, 0, HW_GPR, NULL}, /* for audio-extension. */ + {"a_ru", 10, 5, 0, HW_GPR, NULL}, /* for audio-extension. */ + {"a_dx", 9, 1, 0, HW_DXR, NULL}, /* for audio-extension. */ + {"a_a30", 16, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */ + {"a_b20", 12, 4, 0, HW_GPR, parse_a30b20}, /* for audio-extension. */ + {"a_rt21", 5, 7, 0, HW_GPR, parse_rt21}, /* for audio-extension. */ + {"a_rte", 5, 7, 0, HW_GPR, parse_rte_start}, /* for audio-extension. */ + {"a_rte1", 5, 7, 0, HW_GPR, parse_rte_end}, /* for audio-extension. */ + {"a_rte69", 6, 4, 0, HW_GPR, parse_rte69_start}, /* for audio-extension. */ + {"a_rte69_1", 6, 4, 0, HW_GPR, parse_rte69_end}, /* for audio-extension. */ + {"dhy", 5, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */ + {"dxh", 15, 2, 0, HW_AEXT_ACC, NULL}, /* for audio-extension. */ + {"aridx", 0, 5, 0, HW_AEXT_ARIDX, NULL}, /* for audio-extension. */ + {"aridx2", 0, 5, 0, HW_AEXT_ARIDX2, NULL}, /* for audio-extension. */ + {"aridxi", 16, 4, 0, HW_AEXT_ARIDXI, NULL}, /* for audio-extension. */ + {"imm16", 0, 16, 0, HW_UINT, NULL}, /* for audio-extension. */ + {"im5_i", 0, 5, 0, HW_AEXT_IM_I, parse_im5_ip}, /* for audio-extension. */ + {"im5_m", 0, 5, 0, HW_AEXT_IM_M, parse_im5_mr}, /* for audio-extension. */ + {"im6_ip", 0, 2, 0, HW_AEXT_IM_I, parse_im6_ip}, /* for audio-extension. */ + {"im6_iq", 0, 2, 0, HW_AEXT_IM_I, parse_im6_iq}, /* for audio-extension. */ + {"im6_mr", 2, 2, 0, HW_AEXT_IM_M, parse_im6_mr}, /* for audio-extension. */ + {"im6_ms", 4, 2, 0, HW_AEXT_IM_M, parse_im6_ms}, /* for audio-extension. */ + {"cp45", 4, 2, 0, HW_CP, NULL}, /* for cop-extension. */ + {"i12u", 8, 12, 0, HW_UINT, NULL}, /* for cop-extension. */ + {"cpi19", 6, 19, 0, HW_UINT, NULL}, /* for cop-extension. */ {NULL, 0, 0, 0, 0, NULL} }; - -#define OP6(op6) (N32_OP6_ ## op6 << 25) #define DEF_REG(r) (__BIT (r)) #define USE_REG(r) (__BIT (r)) #define RT(r) (r << 20) @@ -211,55 +219,154 @@ static const field_t operand_fields[] = #define RB(r) (r << 10) #define RA5(r) (r) -static struct nds32_opcode nds32_opcodes[] = +struct nds32_opcode nds32_opcodes[] = { - /* ALU1 */ -#define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub) - {"add", "=rt,%ra,%rb", ALU1 (ADD), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sub", "=rt,%ra,%rb", ALU1 (SUB), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"and", "=rt,%ra,%rb", ALU1 (AND), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"xor", "=rt,%ra,%rb", ALU1 (XOR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"or", "=rt,%ra,%rb", ALU1 (OR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"nor", "=rt,%ra,%rb", ALU1 (NOR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"slt", "=rt,%ra,%rb", ALU1 (SLT), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"slts", "=rt,%ra,%rb", ALU1 (SLTS), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"slli", "=rt,%ra,%ib5u", ALU1 (SLLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"srli", "=rt,%ra,%ib5u", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"srai", "=rt,%ra,%ib5u", ALU1 (SRAI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"rotri", "=rt,%ra,%ib5u", ALU1 (ROTRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sll", "=rt,%ra,%rb", ALU1 (SLL), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"srl", "=rt,%ra,%rb", ALU1 (SRL), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sra", "=rt,%ra,%rb", ALU1 (SRA), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"rotr", "=rt,%ra,%rb", ALU1 (ROTR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"seb", "=rt,%ra", ALU1 (SEB), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"seh", "=rt,%ra", ALU1 (SEH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"bitc", "=rt,%ra,%rb", ALU1 (BITC), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"zeh", "=rt,%ra", ALU1 (ZEH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"wsbh", "=rt,%ra", ALU1 (WSBH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"divsr", "=rt,=rd,%ra,%rb", ALU1 (DIVSR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL}, - {"divr", "=rt,=rd,%ra,%rb", ALU1 (DIVR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL}, - {"sva", "=rt,%ra,%rb", ALU1 (SVA), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"svs", "=rt,%ra,%rb", ALU1 (SVS), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"cmovz", "=rt,%ra,%rb", ALU1 (CMOVZ), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"cmovn", "=rt,%ra,%rb", ALU1 (CMOVN), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"add_slli", "=rt,%ra,%rb,%sh", ALU1 (ADD), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"sub_slli", "=rt,%ra,%rb,%sh", ALU1 (SUB), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"and_slli", "=rt,%ra,%rb,%sh", ALU1 (AND), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"xor_slli", "=rt,%ra,%rb,%sh", ALU1 (XOR), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"or_slli", "=rt,%ra,%rb,%sh", ALU1 (OR), 4, ATTR_V3, 0, NULL, 0, NULL}, + /* opc6_encoding table OPC_6. */ + {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"swi", "%rt,[%ra{+%i15s2}]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sbi.bi", "%rt,[%ra],%i15s", OP6 (SBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"shi.bi", "%rt,[%ra],%i15s1", OP6 (SHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"swi.bi", "%rt,[%ra],%i15s2", OP6 (SWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + + {"lbsi", "=rt,[%ra{+%i15s}]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhsi", "=rt,[%ra{+%i15s1}]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbsi.bi", "=rt,[%ra],%i15s", OP6 (LBSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhsi.bi", "=rt,[%ra],%i15s1", OP6 (LHSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"movi", "=rt,%i20s", OP6 (MOVI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sethi", "=rt,%i20u", OP6 (SETHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"addi", "=rt,%ra,%i15s", OP6 (ADDI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"subri", "=rt,%ra,%i15s", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"andi", "=rt,%ra,%i15u", OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"xori", "=rt,%ra,%i15u", OP6 (XORI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"ori", "=rt,%ra,%i15u", OP6 (ORI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"slti", "=rt,%ra,%i15s", OP6 (SLTI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sltsi", "=rt,%ra,%i15s", OP6 (SLTSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"bitci", "=rt,%ra,%i15u", OP6 (BITCI), 4, ATTR_V3, 0, NULL, 0, NULL}, + + /* seg-DPREFI. */ + {"dprefi.w", "%dpref_st,[%ra{+%i15s2}]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | __BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + /* seg-LBGP. */ + {"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + /* seg-LWC/0. */ + {"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL}, + {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, + /* seg-SWC/0. */ + {"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL}, + {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, + /* seg-LDC/0. */ + {"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL}, + {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, + /* seg-SDC/0. */ + {"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL}, + {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, + /* seg-LSMW. */ + {"lmw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lmwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + {"lmwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, + {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | __BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | __BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, + /* seg-HWGP. */ + {"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + {"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + {"shi.gp", "%rt,[+%i18s1]", OP6 (HWGP) | (4 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + {"lwi.gp", "=rt,[+%i17s2]", OP6 (HWGP) | (6 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + {"swi.gp", "%rt,[+%i17s2]", OP6 (HWGP) | (7 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + + /* seg-SBGP. */ + {"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, + /* seg-JI. */ + {"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"jal", "%i24s1", OP6 (JI) | __BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-JREG. */ + {"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + {"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + {"jrnez", "%rb", JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, + {"jralnez", "%rt,%rb", JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, + {"ret", "%rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + {"ifret", "", JREG (JR) | JREG_IFC | JREG_RET, 4, ATTR (BRANCH) | ATTR (IFC_EXT), 0, NULL, 0, NULL}, + {"jral", "%rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + {"jralnez", "%rb", JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, + {"ret", "", JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + {"jr", "%dtitoff %rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"ret", "%dtitoff %rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"jral", "%dtiton %rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + {"jral", "%dtiton %rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-BR1. */ + {"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-BR2. */ +#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16)) + {"ifcall", "%i16s1", BR2 (IFCALL), 4, ATTR (IFC_EXT), 0, NULL, 0, NULL}, + {"beqz", "%rt,%i16s1", BR2 (BEQZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bnez", "%rt,%i16s1", BR2 (BNEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bgez", "%rt,%i16s1", BR2 (BGEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bltz", "%rt,%i16s1", BR2 (BLTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bgtz", "%rt,%i16s1", BR2 (BGTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"blez", "%rt,%i16s1", BR2 (BLEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bgezal", "%rt,%i16s1", BR2 (BGEZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bltzal", "%rt,%i16s1", BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-BR3. */ + {"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL}, + {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL}, + /* seg-SIMD. */ + {"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, + {"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, + /* seg-ALU1. */ + {"add", "=rt,%ra,%rb", ALU1 (ADD), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sub", "=rt,%ra,%rb", ALU1 (SUB), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"and", "=rt,%ra,%rb", ALU1 (AND), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"xor", "=rt,%ra,%rb", ALU1 (XOR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"or", "=rt,%ra,%rb", ALU1 (OR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"nor", "=rt,%ra,%rb", ALU1 (NOR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"slt", "=rt,%ra,%rb", ALU1 (SLT), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"slts", "=rt,%ra,%rb", ALU1 (SLTS), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"slli", "=rt,%ra,%ib5u", ALU1 (SLLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"srli", "=rt,%ra,%ib5u", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"srai", "=rt,%ra,%ib5u", ALU1 (SRAI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"rotri", "=rt,%ra,%ib5u", ALU1 (ROTRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sll", "=rt,%ra,%rb", ALU1 (SLL), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"srl", "=rt,%ra,%rb", ALU1 (SRL), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sra", "=rt,%ra,%rb", ALU1 (SRA), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"rotr", "=rt,%ra,%rb", ALU1 (ROTR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"seb", "=rt,%ra", ALU1 (SEB), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"seh", "=rt,%ra", ALU1 (SEH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"bitc", "=rt,%ra,%rb", ALU1 (BITC), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"zeh", "=rt,%ra", ALU1 (ZEH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"wsbh", "=rt,%ra", ALU1 (WSBH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"divsr", "=rt,=rd,%ra,%rb", ALU1 (DIVSR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL}, + {"divr", "=rt,=rd,%ra,%rb", ALU1 (DIVR), 4, ATTR (DIV) | ATTR_V2UP, 0, NULL, 0, NULL}, + {"sva", "=rt,%ra,%rb", ALU1 (SVA), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"svs", "=rt,%ra,%rb", ALU1 (SVS), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cmovz", "=rt,%ra,%rb", ALU1 (CMOVZ), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cmovn", "=rt,%ra,%rb", ALU1 (CMOVN), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"or_srli", "=rt,%ra,%rb,%sh", ALU1 (OR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, {"add_srli", "=rt,%ra,%rb,%sh", ALU1 (ADD_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, {"sub_srli", "=rt,%ra,%rb,%sh", ALU1 (SUB_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, {"and_srli", "=rt,%ra,%rb,%sh", ALU1 (AND_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, {"xor_srli", "=rt,%ra,%rb,%sh", ALU1 (XOR_SRLI), 4, ATTR_V3, 0, NULL, 0, NULL}, - - /* ALU2 */ -#define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub) + {"add_slli", "=rt,%ra,%rb,%sh", ALU1 (ADD), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"sub_slli", "=rt,%ra,%rb,%sh", ALU1 (SUB), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"and_slli", "=rt,%ra,%rb,%sh", ALU1 (AND), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"xor_slli", "=rt,%ra,%rb,%sh", ALU1 (XOR), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"or_slli", "=rt,%ra,%rb,%sh", ALU1 (OR), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"nop", "", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-ALU2. */ {"max", "=rt,%ra,%rb", ALU2 (MAX), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"min", "=rt,%ra,%rb", ALU2 (MIN), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"ave", "=rt,%ra,%rb", ALU2 (AVE), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"abs", "=rt,%ra", ALU2 (ABS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, - {"clips", "=rt,%ra,%ib5s", ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, + {"clips", "=rt,%ra,%ib5u", ALU2 (CLIPS), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"clip", "=rt,%ra,%ib5u", ALU2 (CLIP), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"clo", "=rt,%ra", ALU2 (CLO), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"clz", "=rt,%ra", ALU2 (CLZ), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, @@ -269,16 +376,12 @@ static struct nds32_opcode nds32_opcodes[] = {"btst", "=rt,%ra,%ib5u", ALU2 (BTST), 4, ATTR (PERF_EXT), 0, NULL, 0, NULL}, {"bse", "=rt,%ra,=rb", ALU2 (BSE), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, {"bsp", "=rt,%ra,=rb", ALU2 (BSP), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, - {"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, - {"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, {"ffzmism", "=rt,%ra,%rb", ALU2 (FFZMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, {"mfusr", "=rt,%usr", ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"mtusr", "%rt,%usr", ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"mfusr", "=rt,%ridx", ALU2 (MFUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"mtusr", "%rt,%ridx", ALU2 (MTUSR), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"mul", "=rt,%ra,%rb", ALU2 (MUL), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"madds64", "=dt,%ra,%rb", ALU2 (MADDS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, {"madd64", "=dt,%ra,%rb", ALU2 (MADD64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, {"msubs64", "=dt,%ra,%rb", ALU2 (MSUBS64), 4, ATTR (MAC) | ATTR_ALL, 0, NULL, 0, NULL}, @@ -286,459 +389,598 @@ static struct nds32_opcode nds32_opcodes[] = {"divs", "=dt,%ra,%rb", ALU2 (DIVS), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL}, {"div", "=dt,%ra,%rb", ALU2 (DIV), 4, ATTR (DIV) | ATTR (DXREG), 0, NULL, 0, NULL}, {"mult32", "=dt,%ra,%rb", ALU2 (MULT32), 4, ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, - {"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, - {"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, - {"ffbi", "=rt,%ra,%ib5u", ALU2 (FFBI) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, + + /* seg-ALU2_FFBI. */ + {"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, + {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, + /* seg-ALU2_FLMISM. */ + {"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, + /* seg-ALU2_MULSR64. */ + {"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + /* seg-ALU2_MULR64. */ + {"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + /* seg-ALU2_MADDR32. */ + {"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL}, + /* seg-ALU2_MSUBR32. */ + {"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL}, {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL}, - /* MISC */ -#define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub) + /* seg-MISC. */ {"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"cctl", "%ra,%cctl_st0", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"cctl", "=rt,%ra,%cctl_st2", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"cctl", "%rt,%ra,%cctl_st3", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"cctl", "%cctl_st4", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"mfsr", "=rt,%sr", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"iret", "", MISC (IRET), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"trap", "%swid", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"teqz", "%rt,%swid", MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"tnez", "%rt,%swid", MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"teqz", "%rt{,%swid}", MISC (TEQZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"tnez", "%rt{,%swid}", MISC (TNEZ), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"dsb", "", MISC (DSB), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"isb", "", MISC (ISB), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"break", "%swid", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"break", "", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"syscall", "%swid", MISC (SYSCALL), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"msync", "%msync_st", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"msync", "%msync_stx", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, {"isync", "%rt", MISC (ISYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"tlbop", "%ra,%tlbop_st", MISC (TLBOP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"tlbop", "%ra,%tlbop_stx", MISC (TLBOP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"tlbop", "%rt,%ra,pb", MISC (TLBOP) | (5 << 5), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"tlbop", "flua", MISC (TLBOP) | (7 << 5), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - - {"setend.l", "", MISC (MTSR) - | (SRIDX (1, 0, 0) << 10) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"setend.b", "", MISC (MTSR) - | (SRIDX (1, 0, 0) << 10) | __BIT (5) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"setgie.d", "", MISC (MTSR) - | (SRIDX (1, 0, 0) << 10) | __BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"setgie.e", "", MISC (MTSR) - | (SRIDX (1, 0, 0) << 10) | __BIT (6) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL}, - - /* JI */ - {"jal", "%i24s1", OP6 (JI) | __BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - - /* BR1 */ - {"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - - /* BR2 */ -#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16)) - {"beqz", "%rt,%i16s1", BR2 (BEQZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bnez", "%rt,%i16s1", BR2 (BNEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bgez", "%rt,%i16s1", BR2 (BGEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bltz", "%rt,%i16s1", BR2 (BLTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bgtz", "%rt,%i16s1", BR2 (BGTZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"blez", "%rt,%i16s1", BR2 (BLEZ), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bgezal", "%rt,%i16s1", BR2 (BGEZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bltzal", "%rt,%i16s1", BR2 (BLTZAL), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - - /* BR3 */ - {"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL}, - {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL}, - -#define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub) - /* JREG */ - {"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"jral", "%rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"jrnez", "%rb", JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, - {"jralnez", "%rt,%rb", JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, - {"jralnez", "%rb", JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL}, - -#define JREG_RET (1 << 5) -#define JREG_IFC (1 << 6) - {"ret", "%rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"ret", "", JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"jral", "%dtiton %rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"jral", "%dtiton %rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}, - {"jr", "%dtitoff %rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"ret", "%dtitoff %rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"ifret", "", JREG (JR) | JREG_IFC | JREG_RET, 4, ATTR (BRANCH) | ATTR (IFC_EXT), 0, NULL, 0, NULL}, - - /* MEM */ -#define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub) - {"lb", "=rt,[%ra+(%rb<<%sv)]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lb", "=rt,[%ra+%rb{<<%sv}]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lh", "=rt,[%ra+(%rb<<%sv)]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lh", "=rt,[%ra+%rb{<<%sv}]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lw", "=rt,[%ra+(%rb<<%sv)]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lw", "=rt,[%ra+%rb{<<%sv}]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sb", "=rt,[%ra+(%rb<<%sv)]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sb", "%rt,[%ra+%rb{<<%sv}]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sh", "=rt,[%ra+(%rb<<%sv)]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sh", "%rt,[%ra+%rb{<<%sv}]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sw", "=rt,[%ra+(%rb<<%sv)]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sw", "%rt,[%ra+%rb{<<%sv}]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lb.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lh.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lw.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sb.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sh.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sw.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbs", "=rt,[%ra+(%rb<<%sv)]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbs", "=rt,[%ra+%rb{<<%sv}]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhs", "=rt,[%ra+(%rb<<%sv)]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhs", "=rt,[%ra+%rb{<<%sv}]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"llw", "=rt,[%ra+(%rb<<%sv)]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"llw", "=rt,[%ra+%rb{<<%sv}]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"scw", "%rt,[%ra+(%rb<<%sv)]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"scw", "%rt,[%ra+%rb{<<%sv}]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"lbup", "=rt,[%ra+(%rb<<%sv)]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, - {"lbup", "=rt,[%ra+%rb{<<%sv}]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, - {"lwup", "=rt,[%ra+(%rb<<%sv)]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"lwup", "=rt,[%ra+%rb{<<%sv}]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"sbup", "%rt,[%ra+(%rb<<%sv)]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, - {"sbup", "%rt,[%ra+%rb{<<%sv}]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, - {"swup", "%rt,[%ra+(%rb<<%sv)]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"swup", "%rt,[%ra+%rb{<<%sv}]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + /* seg-MISC_MTSR. */ + {"mtsr", "%rt,%sr", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-MISC_SETEND. */ + {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-MISC_SETGIE. */ + {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"break", "", MISC (BREAK), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"msync", "", MISC (MSYNC), 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-MISC_TLBOP. */ + {"tlbop", "%ra,%tlbop_st", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"tlbop", "%ra,%tlbop_stx", MISC (TLBOP), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"tlbop", "%rt,%ra,pb", MISC (TLBOP) | (5 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"tlbop", "flua", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"tlbop", "flushall", MISC (TLBOP) | (7 << 5), 4, ATTR_ALL, 0, NULL, 0, NULL}, + + /* seg-MEM. */ + {"lb", "=rt,[%ra+(%rb<<%sv)]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lb", "=rt,[%ra+%rb{<<%sv}]", MEM (LB), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lh", "=rt,[%ra+(%rb<<%sv)]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lh", "=rt,[%ra+%rb{<<%sv}]", MEM (LH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lw", "=rt,[%ra+(%rb<<%sv)]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lw", "=rt,[%ra+%rb{<<%sv}]", MEM (LW), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"ld", "=rt,[%ra+(%rb<<%sv)]", MEM (LD), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lb.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lb.p", "=rt,[%ra],%rb{<<%sv}", MEM (LB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lh.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lh.p", "=rt,[%ra],%rb{<<%sv}", MEM (LH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lw.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lw.p", "=rt,[%ra],%rb{<<%sv}", MEM (LW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"ld.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sb", "=rt,[%ra+(%rb<<%sv)]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sb", "%rt,[%ra+%rb{<<%sv}]", MEM (SB), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sh", "=rt,[%ra+(%rb<<%sv)]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sh", "%rt,[%ra+%rb{<<%sv}]", MEM (SH), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sw", "=rt,[%ra+(%rb<<%sv)]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sw", "%rt,[%ra+%rb{<<%sv}]", MEM (SW), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sd", "=rt,[%ra+(%rb<<%sv)]", MEM (SD), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sb.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sb.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sb.p", "%rt,[%ra],%rb{<<%sv}", MEM (SB_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sh.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sh.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sh.p", "%rt,[%ra],%rb{<<%sv}", MEM (SH_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sw.bi", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sw.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sw.p", "%rt,[%ra],%rb{<<%sv}", MEM (SW_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sd.bi", "=rt,[%ra],(%rb<<%sv)", MEM (SD_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + + {"lbs", "=rt,[%ra+(%rb<<%sv)]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbs", "=rt,[%ra+%rb{<<%sv}]", MEM (LBS), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhs", "=rt,[%ra+(%rb<<%sv)]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhs", "=rt,[%ra+%rb{<<%sv}]", MEM (LHS), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LBS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LBS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhs.bi", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhs.bi", "=rt,[%ra],(%rb<<%sv)", MEM (LHS_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhs.p", "=rt,[%ra],%rb{<<%sv}", MEM (LHS_BI),4, ATTR_ALL, 0, NULL, 0, NULL}, + {"llw", "=rt,[%ra+(%rb<<%sv)]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"llw", "=rt,[%ra+%rb{<<%sv}]", MEM (LLW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"scw", "%rt,[%ra+(%rb<<%sv)]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"scw", "%rt,[%ra+%rb{<<%sv}]", MEM (SCW), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + + {"lbup", "=rt,[%ra+(%rb<<%sv)]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + {"lbup", "=rt,[%ra+%rb{<<%sv}]", MEM (LBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + {"lwup", "=rt,[%ra+(%rb<<%sv)]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"lwup", "=rt,[%ra+%rb{<<%sv}]", MEM (LWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"sbup", "%rt,[%ra+(%rb<<%sv)]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + {"sbup", "%rt,[%ra+%rb{<<%sv}]", MEM (SBUP), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, + {"swup", "%rt,[%ra+(%rb<<%sv)]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"swup", "%rt,[%ra+%rb{<<%sv}]", MEM (SWUP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + + {"dpref", "%dpref_st,[%ra]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"dpref", "%dpref_st,[%ra+(%rb<<%sv)]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, {"dpref", "%dpref_st,[%ra+%rb{<<%sv}]", MEM (DPREF), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - /* LBGP */ - {"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - - /* SBGP */ - {"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - - /* HWGP */ - {"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - {"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - {"shi.gp", "%rt,[+%i18s1]", OP6 (HWGP) | (4 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - {"lwi.gp", "=rt,[+%i17s2]", OP6 (HWGP) | (6 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - {"swi.gp", "%rt,[+%i17s2]", OP6 (HWGP) | (7 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL}, - -#define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub) - {"lmw", "%abdim %rt,[%ra],%rb{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"smw", "%abdim %rt,[%ra],%rb{,%enb4}", LSMW (LSMW) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lmwa", "%abdim %rt,[%ra],%rb{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, - {"smwa", "%abdim %rt,[%ra],%rb{,%enb4}", LSMW (LSMWA) | __BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL}, - {"lmwzb", "%abm %rt,[%ra],%rb{,%enb4}", LSMW (LSMWZB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, - {"smwzb", "%abm %rt,[%ra],%rb{,%enb4}", LSMW (LSMWZB) | __BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL}, - - -#define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub) - {"pbsad", "%rt,%rb,%ra", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, - {"pbsada", "%rt,%rb,%ra", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL}, - - /* COP */ -#if 0 - {"cpe1", 0, 0, NULL, 0, NULL}, - {"mfcp", 0, 0, NULL, 0, NULL}, - {"cplw", 0, 0, NULL, 0, NULL}, - {"cplw.bi", 0, 0, NULL, 0, NULL}, - {"cpld", 0, 0, NULL, 0, NULL}, - {"cpld.bi", 0, 0, NULL, 0, NULL}, - {"cpe2", 0, 0, NULL, 0, NULL}, - - {"cpe3", 0, 0, NULL, 0, NULL}, - {"mtcp", 0, 0, NULL, 0, NULL}, - {"cpsw", 0, 0, NULL, 0, NULL}, - {"cpsw.bi", 0, 0, NULL, 0, NULL}, - {"cpsd", 0, 0, NULL, 0, NULL}, - {"cpsd.bi", 0, 0, NULL, 0, NULL}, - {"cpe4", 0, 0, NULL, 0, NULL}, -#endif - - /* FPU */ -#define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6)) - {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcpynss", "=fst,%fsa,%fsb", FS1 (FCPYNSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcpyss", "=fst,%fsa,%fsb", FS1 (FCPYSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fmadds", "=fst,%fsa,%fsb", FS1 (FMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fmsubs", "=fst,%fsa,%fsb", FS1 (FMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmovns", "=fst,%fsa,%fsb", FS1 (FCMOVNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmovzs", "=fst,%fsa,%fsb", FS1 (FCMOVZS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fnmadds", "=fst,%fsa,%fsb", FS1 (FNMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fnmsubs", "=fst,%fsa,%fsb", FS1 (FNMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fmuls", "=fst,%fsa,%fsb", FS1 (FMULS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fdivs", "=fst,%fsa,%fsb", FS1 (FDIVS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - -#define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \ - | (N32_FPU_FS1_F2OP_ ## sub << 10)) - {"fs2d", "=fdt,%fsa", FS1_F2OP (FS2D), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fsqrts", "=fst,%fsa", FS1_F2OP (FSQRTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fabss", "=fst,%fsa", FS1_F2OP (FABSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fui2s", "=fst,%fsa", FS1_F2OP (FUI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fsi2s", "=fst,%fsa", FS1_F2OP (FSI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fs2ui", "=fst,%fsa", FS1_F2OP (FS2UI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + /* For missing-operand-load/store instructions. */ + {"lb", "=rt,[%ra]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lh", "=rt,[%ra]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lw", "=rt,[%ra]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lbs", "=rt,[%ra]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"lhs", "=rt,[%ra]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sb", "%rt,[%ra]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sh", "%rt,[%ra]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"sw", "%rt,[%ra]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + + /* seg-LWC0. */ + {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-SWC0. */ + {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-LDC0. */ + {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-SDC0. */ + {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, + + /* seg-FPU_FS1. */ + {"fadds", "=fst,%fsa,%fsb", FS1 (FADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fsubs", "=fst,%fsa,%fsb", FS1 (FSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcpynss", "=fst,%fsa,%fsb", FS1 (FCPYNSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcpyss", "=fst,%fsa,%fsb", FS1 (FCPYSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fmadds", "=fst,%fsa,%fsb", FS1 (FMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fmsubs", "=fst,%fsa,%fsb", FS1 (FMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmovns", "=fst,%fsa,%fsb", FS1 (FCMOVNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmovzs", "=fst,%fsa,%fsb", FS1 (FCMOVZS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fnmadds", "=fst,%fsa,%fsb", FS1 (FNMADDS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fnmsubs", "=fst,%fsa,%fsb", FS1 (FNMSUBS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fmuls", "=fst,%fsa,%fsb", FS1 (FMULS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fdivs", "=fst,%fsa,%fsb", FS1 (FDIVS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + + /* seg-FPU_FS1_F2OP. */ + {"fs2d", "=fdt,%fsa", FS1_F2OP (FS2D), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fsqrts", "=fst,%fsa", FS1_F2OP (FSQRTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fabss", "=fst,%fsa", FS1_F2OP (FABSS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fui2s", "=fst,%fsa", FS1_F2OP (FUI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fsi2s", "=fst,%fsa", FS1_F2OP (FSI2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fs2ui", "=fst,%fsa", FS1_F2OP (FS2UI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, {"fs2ui.z", "=fst,%fsa", FS1_F2OP (FS2UI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fs2si", "=fst,%fsa", FS1_F2OP (FS2SI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fs2si", "=fst,%fsa", FS1_F2OP (FS2SI), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, {"fs2si.z", "=fst,%fsa", FS1_F2OP (FS2SI_Z), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - -#define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6)) - {"fcmpeqs", "=fst,%fsa,%fsb", FS2 (FCMPEQS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmplts", "=fst,%fsa,%fsb", FS2 (FCMPLTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmples", "=fst,%fsa,%fsb", FS2 (FCMPLES), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmpuns", "=fst,%fsa,%fsb", FS2 (FCMPUNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmpeqs.e", "=fst,%fsa,%fsb", FS2 (FCMPEQS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmplts.e", "=fst,%fsa,%fsb", FS2 (FCMPLTS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmples.e", "=fst,%fsa,%fsb", FS2 (FCMPLES_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - {"fcmpuns.e", "=fst,%fsa,%fsb", FS2 (FCMPUNS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, - -#define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6)) - {"faddd", "=fdt,%fda,%fdb", FD1 (FADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fsubd", "=fdt,%fda,%fdb", FD1 (FSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcpynsd", "=fdt,%fda,%fdb", FD1 (FCPYNSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcpysd", "=fdt,%fda,%fdb", FD1 (FCPYSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fmaddd", "=fdt,%fda,%fdb", FD1 (FMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fmsubd", "=fdt,%fda,%fdb", FD1 (FMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmovnd", "=fdt,%fda,%fsb", FD1 (FCMOVND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmovzd", "=fdt,%fda,%fsb", FD1 (FCMOVZD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fnmaddd", "=fdt,%fda,%fdb", FD1 (FNMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fnmsubd", "=fdt,%fda,%fdb", FD1 (FNMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fmuld", "=fdt,%fda,%fdb", FD1 (FMULD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fdivd", "=fdt,%fda,%fdb", FD1 (FDIVD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - -#define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \ - | (N32_FPU_FD1_F2OP_ ## sub << 10)) - {"fd2s", "=fst,%fda", FD1_F2OP (FD2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fsqrtd", "=fdt,%fda", FD1_F2OP (FSQRTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fabsd", "=fdt,%fda", FD1_F2OP (FABSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fui2d", "=fdt,%fsa", FD1_F2OP (FUI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fsi2d", "=fdt,%fsa", FD1_F2OP (FSI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fd2ui", "=fst,%fda", FD1_F2OP (FD2UI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + /* seg-FPU_FS2. */ + {"fcmpeqs", "=fst,%fsa,%fsb", FS2 (FCMPEQS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmpeqs.e", "=fst,%fsa,%fsb", FS2 (FCMPEQS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmplts", "=fst,%fsa,%fsb", FS2 (FCMPLTS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmplts.e", "=fst,%fsa,%fsb", FS2 (FCMPLTS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmples", "=fst,%fsa,%fsb", FS2 (FCMPLES), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmples.e", "=fst,%fsa,%fsb", FS2 (FCMPLES_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmpuns", "=fst,%fsa,%fsb", FS2 (FCMPUNS), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + {"fcmpuns.e", "=fst,%fsa,%fsb", FS2 (FCMPUNS_E), 4, ATTR (FPU) | ATTR (FPU_SP_EXT), 0, NULL, 0, NULL}, + /* seg-FPU_FD1. */ + {"faddd", "=fdt,%fda,%fdb", FD1 (FADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fsubd", "=fdt,%fda,%fdb", FD1 (FSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcpynsd", "=fdt,%fda,%fdb", FD1 (FCPYNSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcpysd", "=fdt,%fda,%fdb", FD1 (FCPYSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fmaddd", "=fdt,%fda,%fdb", FD1 (FMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fmsubd", "=fdt,%fda,%fdb", FD1 (FMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmovnd", "=fdt,%fda,%fsb", FD1 (FCMOVND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmovzd", "=fdt,%fda,%fsb", FD1 (FCMOVZD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fnmaddd", "=fdt,%fda,%fdb", FD1 (FNMADDD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fnmsubd", "=fdt,%fda,%fdb", FD1 (FNMSUBD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fmuld", "=fdt,%fda,%fdb", FD1 (FMULD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fdivd", "=fdt,%fda,%fdb", FD1 (FDIVD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + /* seg-FPU_FD1_F2OP. */ + {"fd2s", "=fst,%fda", FD1_F2OP (FD2S), 4, ATTR (FPU) | ATTR (FPU_SP_EXT) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fsqrtd", "=fdt,%fda", FD1_F2OP (FSQRTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fabsd", "=fdt,%fda", FD1_F2OP (FABSD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fui2d", "=fdt,%fsa", FD1_F2OP (FUI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fsi2d", "=fdt,%fsa", FD1_F2OP (FSI2D), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fd2ui", "=fst,%fda", FD1_F2OP (FD2UI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, {"fd2ui.z", "=fst,%fda", FD1_F2OP (FD2UI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fd2si", "=fst,%fda", FD1_F2OP (FD2SI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fd2si", "=fst,%fda", FD1_F2OP (FD2SI), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, {"fd2si.z", "=fst,%fda", FD1_F2OP (FD2SI_Z), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - -#define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6)) - {"fcmpeqd", "=fst,%fda,%fdb", FD2 (FCMPEQD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpltd", "=fst,%fda,%fdb", FD2 (FCMPLTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpled", "=fst,%fda,%fdb", FD2 (FCMPLED), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpund", "=fst,%fda,%fdb", FD2 (FCMPUND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpeqd.e", "=fst,%fda,%fdb", FD2 (FCMPEQD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpltd.e", "=fst,%fda,%fdb", FD2 (FCMPLTD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpled.e", "=fst,%fda,%fdb", FD2 (FCMPLED_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - {"fcmpund.e", "=fst,%fda,%fdb", FD2 (FCMPUND_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, - -#define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6)) - {"fmfsr", "=rt,%fsa", MFCP (FMFSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fmfdr", "=rt,%fda", MFCP (FMFDR), 4, ATTR (FPU), 0, NULL, 0, NULL}, - -#define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \ - | (N32_FPU_MFCP_XR_ ## sub << 10)) - {"fmfcfg", "=rt" , MFCP_XR(FMFCFG), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fmfcsr", "=rt" , MFCP_XR(FMFCSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, - -#define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6)) - {"fmtsr", "%rt,=fsa", MTCP (FMTSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fmtdr", "%rt,=fda", MTCP (FMTDR), 4, ATTR (FPU), 0, NULL, 0, NULL}, - -#define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \ - | (N32_FPU_MTCP_XR_ ## sub << 10)) - {"fmtcsr", "%rt" , MTCP_XR(FMTCSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, - -#define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub) -#define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x2 << 6) -#define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12)) - {"fls", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM (FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fls", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM (FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fls.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI (FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fls.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI (FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fss", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM (FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fss", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM (FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fss.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI (FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fss.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI (FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fld", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM (FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fld", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM (FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fld.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI (FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fld.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI (FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fsd", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM (FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fsd", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM (FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fsd.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI (FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fsd.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI (FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"flsi", "=fst,[%ra{+%i12s2}]", OP6 (LWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"flsi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (LWC),4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fssi", "=fst,[%ra{+%i12s2}]", OP6 (SWC), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fssi.bi", "=fst,[%ra],%i12s2", FPU_RA_IMMBI (SWC),4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fldi", "=fdt,[%ra{+%i12s2}]", OP6 (LDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fldi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (LDC),4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fsdi", "=fdt,[%ra{+%i12s2}]", OP6 (SDC), 4, ATTR (FPU), 0, NULL, 0, NULL}, - {"fsdi.bi", "=fdt,[%ra],%i12s2", FPU_RA_IMMBI (SDC),4, ATTR (FPU), 0, NULL, 0, NULL}, - - /* AEXT */ - - {"lbi", "=rt,[%ra{+%i15s}]", OP6 (LBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhi", "=rt,[%ra{+%i15s1}]", OP6 (LHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lwi", "=rt,[%ra{+%i15s2}]", OP6 (LWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbi.bi", "=rt,[%ra],%i15s", OP6 (LBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhi.bi", "=rt,[%ra],%i15s1", OP6 (LHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lwi.bi", "=rt,[%ra],%i15s2", OP6 (LWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sbi", "%rt,[%ra{+%i15s}]", OP6 (SBI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"shi", "%rt,[%ra{+%i15s1}]", OP6 (SHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"swi", "%rt,[%ra{+%i15s2}]", OP6 (SWI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sbi.bi", "%rt,[%ra],%i15s", OP6 (SBI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"shi.bi", "%rt,[%ra],%i15s1", OP6 (SHI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"swi.bi", "%rt,[%ra],%i15s2", OP6 (SWI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbsi", "=rt,[%ra{+%i15s}]", OP6 (LBSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhsi", "=rt,[%ra{+%i15s1}]", OP6 (LHSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lwsi", "=rt,[%ra{+%i15s2}]", OP6 (LWSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lbsi.bi", "=rt,[%ra],%i15s", OP6 (LBSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lhsi.bi", "=rt,[%ra],%i15s1", OP6 (LHSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"lwsi.bi", "=rt,[%ra],%i15s2", OP6 (LWSI_BI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL}, - {"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL}, - {"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL}, - {"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL}, - {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, - {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, - {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, - {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL}, - {"movi", "=rt,%i20s", OP6 (MOVI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sethi", "=rt,%i20u", OP6 (SETHI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"addi", "=rt,%ra,%i15s", OP6 (ADDI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"subri", "=rt,%ra,%i15s", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"andi", "=rt,%ra,%i15u", OP6 (ANDI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"xori", "=rt,%ra,%i15u", OP6 (XORI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"ori", "=rt,%ra,%i15u", OP6 (ORI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"slti", "=rt,%ra,%i15s", OP6 (SLTI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"sltsi", "=rt,%ra,%i15s", OP6 (SLTSI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"bitci", "=rt,%ra,%i15u", OP6 (BITCI), 4, ATTR_V3, 0, NULL, 0, NULL}, - {"dprefi.w", "%dpref_st,[%ra{+%i15s2]}", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, - {"dprefi.d", "%dpref_st,[%ra{+%i15s3]}", OP6 (DPREFI) | __BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + /* seg-FPU_FD2. */ + {"fcmpeqd", "=fst,%fda,%fdb", FD2 (FCMPEQD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpeqd.e", "=fst,%fda,%fdb", FD2 (FCMPEQD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpltd", "=fst,%fda,%fdb", FD2 (FCMPLTD), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpltd.e", "=fst,%fda,%fdb", FD2 (FCMPLTD_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpled", "=fst,%fda,%fdb", FD2 (FCMPLED), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpled.e", "=fst,%fda,%fdb", FD2 (FCMPLED_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpund", "=fst,%fda,%fdb", FD2 (FCMPUND), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + {"fcmpund.e", "=fst,%fda,%fdb", FD2 (FCMPUND_E), 4, ATTR (FPU) | ATTR (FPU_DP_EXT), 0, NULL, 0, NULL}, + /* seg-FPU_MFCP. */ + {"fmfsr", "=rt,%fsa", MFCP (FMFSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fmfdr", "=rt,%fda", MFCP (FMFDR), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_MFCP_XR. */ + {"fmfcfg", "=rt", MFCP_XR(FMFCFG), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fmfcsr", "=rt", MFCP_XR(FMFCSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_MTCP. */ + + {"fmtsr", "%rt,=fsa", MTCP (FMTSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fmtdr", "%rt,=fda", MTCP (FMTDR), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_MTCP_XR. */ + {"fmtcsr", "%rt", MTCP_XR(FMTCSR), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_FLS. */ + {"fls", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fls.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_FLD. */ + {"fld", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fld.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_FSS. */ + {"fss", "=fst,[%ra+(%rb<<%sv)]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fss.bi", "=fst,[%ra],(%rb<<%sv)", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + /* seg-FPU_FSD. */ + {"fsd", "=fdt,[%ra+(%rb<<%sv)]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fsd.bi", "=fdt,[%ra],(%rb<<%sv)", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fls", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fls.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FLS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fld", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fld.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FLD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fss", "=fst,[%ra+%rb{<<%sv}]", FPU_MEM(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fss.bi", "=fst,[%ra],%rb{<<%sv}", FPU_MEMBI(FSS), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fsd", "=fdt,[%ra+%rb{<<%sv}]", FPU_MEM(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"fsd.bi", "=fdt,[%ra],%rb{<<%sv}", FPU_MEMBI(FSD), 4, ATTR (FPU), 0, NULL, 0, NULL}, + {"cctl", "%ra,%cctl_st0", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"cctl", "%ra,%cctl_st1{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"cctl", "=rt,%ra,%cctl_st2", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"cctl", "%rt,%ra,%cctl_st3", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"cctl", "%cctl_st4", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + {"cctl", "%cctl_st5{,%cctl_lv}", MISC (CCTL), 4, ATTR_V3, 0, NULL, 0, NULL}, + {"cctl", "=rt,%ra,%cctl_stx,%cctl_lv", MISC (CCTL), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL}, + /* seg-Alias instructions. */ + {"neg", "=rt,%ra", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"zeb", "=rt,%ra", OP6 (ANDI) | 0xff, 4, ATTR_ALL, 0, NULL, 0, NULL}, + + /* seg-COP. */ + {"cpe1", "%cp45,%cpi19", OP6 (COP) | 0x00, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cpe2", "%cp45,%cpi19", OP6 (COP) | 0x04, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cpe3", "%cp45,%cpi19", OP6 (COP) | 0x08, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cpe4", "%cp45,%cpi19", OP6 (COP) | 0x0C, 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-COP-MFCPX. */ + {"mfcpw", "%cp45,=rt,%i12u", OP6 (COP) | 0x01, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"mfcpd", "%cp45,=rt,%i12u", OP6 (COP) | 0x41, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"mfcppw", "%cp45,=rt,%i12u", OP6 (COP) | 0xc1, 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-COP-CPLW. */ + {"cplw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x02, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cplw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x82, 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-COP-CPLD. */ + {"cpld", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x03, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cpld.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x83, 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-COP-MTCPX. */ + {"mtcpw", "%cp45,%rt,%i12u", OP6 (COP) | 0x09, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"mtcpd", "%cp45,%rt,%i12u", OP6 (COP) | 0x49, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"mtcppw", "%cp45,%rt,%i12u", OP6 (COP) | 0xc9, 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-COP-CPSW. */ + {"cpsw", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0a, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cpsw.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8a, 4, ATTR_ALL, 0, NULL, 0, NULL}, + /* seg-COP-CPSD. */ + {"cpsd", "%cp45,%cprt,[%ra+%rb<<%sv]", OP6 (COP) | 0x0b, 4, ATTR_ALL, 0, NULL, 0, NULL}, + {"cpsd.bi", "%cp45,%cprt,[%ra],%rb<<%sv", OP6 (COP) | 0x8b, 4, ATTR_ALL, 0, NULL, 0, NULL}, /* 16-bit instructions. */ - {"mov55", "=rt5,%ra5", 0x8000, 2, ATTR_ALL, 0, NULL, 0, NULL}, /* mov55, $sp, $sp == ifret */ - {"ifret16", "", 0x83ff, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL}, - {"movi55", "=rt5,%i5s", 0x8400, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"add45", "=rt4,%ra5", 0x8800, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"sub45", "=rt4,%ra5", 0x8a00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"addi45", "=rt4,%i5u", 0x8c00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"subi45", "=rt4,%i5u", 0x8e00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"srai45", "=rt4,%i5u", 0x9000, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"srli45", "=rt4,%i5u", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"slli333", "=rt3,%ra3,%i3u", 0x9400, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"zeb33", "=rt3,%ra3", 0x9600, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"zeh33", "=rt3,%ra3", 0x9601, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"seb33", "=rt3,%ra3", 0x9602, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"seh33", "=rt3,%ra3", 0x9603, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"xlsb33", "=rt3,%ra3", 0x9604, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"x11b33", "=rt3,%ra3", 0x9605, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"bmski33", "=rt3,%ia3u", 0x9606, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"fexti33", "=rt3,%ia3u", 0x9607, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"add333", "=rt3,%ra3,%rb3", 0x9800, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"sub333", "=rt3,%ra3,%rb3", 0x9a00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"addi333", "=rt3,%ra3,%i3u", 0x9c00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"subi333", "=rt3,%ra3,%i3u", 0x9e00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* get bit14~bit11 of 16-bit instruction. */ + {"beqz38", "%rt38,%i8s1", 0xc000, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"bnez38", "%rt38,%i8s1", 0xc800, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + {"beqs38", "%rt38,%i8s1", 0xd000, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, + {"bnes38", "%rt38,%i8s1", 0xd800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, + + /* SEG00, get bit10. */ + {"mov55", "=rt5,%ra5", 0x8000, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"movi55", "=rt5,%i5s", 0x8400, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG01 bit10~bit9. */ + {"add45", "=rt4,%ra5", 0x8800, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"sub45", "=rt4,%ra5", 0x8a00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"addi45", "=rt4,%i5u", 0x8c00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"subi45", "=rt4,%i5u", 0x8e00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG02 bit10~bit9. */ + {"srai45", "=rt4,%i5u", 0x9000, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"srli45", "=rt4,%i5u", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"slli333", "=rt3,%ra3,%i3u", 0x9400, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG03 bit10~bit9. */ + {"add333", "=rt3,%ra3,%rb3", 0x9800, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"sub333", "=rt3,%ra3,%rb3", 0x9a00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"addi333", "=rt3,%ra3,%i3u", 0x9c00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"subi333", "=rt3,%ra3,%i3u", 0x9e00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG04 bit10~bit9. */ {"lwi333", "=rt3,[%ra3{+%i3u2}]", 0xa000, 2, ATTR_ALL, 0, NULL, 0, NULL}, {"lwi333.bi", "=rt3,[%ra3],%i3u2", 0xa200, 2, ATTR_ALL, 0, NULL, 0, NULL}, {"lhi333", "=rt3,[%ra3{+%i3u1}]", 0xa400, 2, ATTR_ALL, 0, NULL, 0, NULL}, {"lbi333", "=rt3,[%ra3{+%i3u}]", 0xa600, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG05 bit10~bit9. */ {"swi333", "%rt3,[%ra3{+%i3u2}]", 0xa800, 2, ATTR_ALL, 0, NULL, 0, NULL}, {"swi333.bi", "%rt3,[%ra3],%i3u2", 0xaa00, 2, ATTR_ALL, 0, NULL, 0, NULL}, {"shi333", "%rt3,[%ra3{+%i3u1}]", 0xac00, 2, ATTR_ALL, 0, NULL, 0, NULL}, {"sbi333", "%rt3,[%ra3{+%i3u}]", 0xae00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"addri36.sp", "%rt3,%i6u2", 0xb000, 2, ATTR_V3MUP, USE_REG (31), NULL, 0, NULL}, - {"lwi45.fe", "=rt4,%fe5", 0xb200, 2, ATTR_V3MUP, USE_REG (8), NULL, 0, NULL}, - {"lwi450", "=rt4,[%ra5]", 0xb400, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"swi450", "%rt4,[%ra5]", 0xb600, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG06 bit10~bit9. */ + {"addri36.sp", "%rt3,%i6u2", 0xb000, 2, ATTR_V3MUP, USE_REG (31), NULL, 0, NULL}, + {"lwi45.fe", "=rt4,%fe5", 0xb200, 2, ATTR_V3MUP, USE_REG (8), NULL, 0, NULL}, + {"lwi450", "=rt4,[%ra5]", 0xb400, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"swi450", "%rt4,[%ra5]", 0xb600, 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG07 bit7. */ {"lwi37", "=rt38,[$fp{+%i7u2}]", 0xb800, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL}, {"swi37", "%rt38,[$fp{+%i7u2}]", 0xb880, 2, ATTR_ALL, USE_REG (28), NULL, 0, NULL}, - {"beqz38", "%rt38,%i8s1", 0xc000, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bnez38", "%rt38,%i8s1", 0xc800, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"beqs38", "%rt38,%i8s1", 0xd000, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, - {"j8", "%i8s1", 0xd500, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, - {"bnes38", "%rt38,%i8s1", 0xd800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, - {"jr5", "%ra5", 0xdd00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"ex9.it", "%i5u", 0xdd40, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL}, - {"ret5", "%ra5", 0xdd80, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"ret5", "", 0xdd80 | RA5 (30), 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"jral5", "%ra5", 0xdd20, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"add5.pc", "%ra5", 0xdda0, 2, ATTR_V3, 0, NULL, 0, NULL}, - {"slts45", "%rt4,%ra5", 0xe000, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, - {"slt45", "%rt4,%ra5", 0xe200, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, - {"sltsi45", "%rt4,%i5u", 0xe400, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, - {"slti45", "%rt4,%i5u", 0xe600, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, - {"beqzs8", "%i8s1", 0xe800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, - {"bnezs8", "%i8s1", 0xe900, 2, ATTR_PCREL | ATTR_ALL, USE_REG (5), NULL, 0, NULL}, - {"ex9.it", "%i9u", 0xea00, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL}, - {"break16", "%i9u", 0xea00, 2, ATTR_ALL, 0, NULL, 0, NULL}, - {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, + /* SEG10_1 if Rt3=5. */ + {"j8", "%i8s1", 0xd500, 2, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG11_2 bit7~bit5. */ + {"jr5", "%ra5", 0xdd00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"jral5", "%ra5", 0xdd20, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"ex9.it", "%i5u", 0xdd40, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL}, + {"ret5", "%ra5", 0xdd80, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"add5.pc", "%ra5", 0xdda0, 2, ATTR_V3, 0, NULL, 0, NULL}, + /* SEG11_3 if Ra5=30. */ + {"ret5", "", 0xdd80 | RA5 (30), 2, ATTR_ALL, 0, NULL, 0, NULL}, + /* SEG12 bit10~bit9. */ + {"slts45", "%rt4,%ra5", 0xe000, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, + {"slt45", "%rt4,%ra5", 0xe200, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, + {"sltsi45", "%rt4,%i5u", 0xe400, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, + {"slti45", "%rt4,%i5u", 0xe600, 2, ATTR_ALL, DEF_REG (15), NULL, 0, NULL}, + /* SEG13 bit10~bit9. */ + {"break16", "%i5u", 0xea00, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, + {"addi10.sp", "%i10s", 0xec00, 2, ATTR_V2UP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, + /* SEG13_1 bit8. */ + {"beqzs8", "%i8s1", 0xe800, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL}, + {"bnezs8", "%i8s1", 0xe900, 2, ATTR_PCREL | ATTR_ALL, USE_REG (15), NULL, 0, NULL}, + /* SEG13_2 bit8~bit5. */ + {"ex9.it", "%i9u", 0xea00, 2, ATTR (EX9_EXT), 0, NULL, 0, NULL}, + /* SEG14 bit7. */ {"lwi37.sp", "=rt38,[+%i7u2]", 0xf000, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL}, {"swi37.sp", "%rt38,[+%i7u2]", 0xf080, 2, ATTR_V2UP, USE_REG (31), NULL, 0, NULL}, - {"ifcall9", "%i9u1", 0xf800, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL}, - {"movpi45", "=rt4,%pi5", 0xfa00, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"push25", "%re2,%i5u3", 0xfc00, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, - {"pop25", "%re2,%i5u3", 0xfc80, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, - {"movd44", "=rt5e,%ra5e", 0xfd00, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"neg33", "=rt3,%ra3", 0xfe02, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"not33", "=rt3,%ra3", 0xfe03, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"mul33", "=rt3,%ra3", 0xfe04, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"xor33", "=rt3,%ra3", 0xfe05, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"and33", "=rt3,%ra3", 0xfe06, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - {"or33", "=rt3,%ra3", 0xfe07, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, - - /* Alias instructions. */ - {"neg", "=rt,%ra", OP6 (SUBRI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"zeb", "=rt,%ra", OP6 (ANDI) | 0xff, 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"nop", "", ALU1 (SRLI), 4, ATTR_ALL, 0, NULL, 0, NULL}, - {"nop16", "", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL}, - - /* TODO: For some instruction, an operand may refer to a pair of - register, e.g., mulsr64 or movd44. - - Some instruction need special constrain, e.g., movpi45, - break16, ex9.it. */ + /* SEG15 bit10~bit9. */ + {"ifcall9", "%i9u1", 0xf800, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL}, + {"movpi45", "=rt4,%pi5", 0xfa00, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + /* SEG15_1 bit8. */ + {"movd44", "=rt5e,%ra5e", 0xfd00, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + + /* SEG-BFMI333 bit2~bit0. */ + {"zeb33", "=rt3,%ra3", 0x9600, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"zeh33", "=rt3,%ra3", 0x9601, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"seb33", "=rt3,%ra3", 0x9602, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"seh33", "=rt3,%ra3", 0x9603, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"xlsb33", "=rt3,%ra3", 0x9604, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"x11b33", "=rt3,%ra3", 0x9605, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"bmski33", "=rt3,%ia3u", 0x9606, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + {"fexti33", "=rt3,%ia3u", 0x9607, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + /* SEG-PUSHPOP25 bit8~bit7. */ + {"push25", "%re2,%i5u3", 0xfc00, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, + {"pop25", "%re2,%i5u3", 0xfc80, 2, ATTR_V3MUP, USE_REG (31) | DEF_REG (31), NULL, 0, NULL}, + /* SEG-MISC33 bit2~bit0. */ + {"neg33", "=rt3,%ra3", 0xfe02, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + {"not33", "=rt3,%ra3", 0xfe03, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + {"mul33", "=rt3,%ra3", 0xfe04, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + {"xor33", "=rt3,%ra3", 0xfe05, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + {"and33", "=rt3,%ra3", 0xfe06, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + {"or33", "=rt3,%ra3", 0xfe07, 2, ATTR_V3MUP, 0, NULL, 0, NULL}, + /* SEG-Alias instructions. */ + {"nop16", "", 0x9200, 2, ATTR_ALL, 0, NULL, 0, NULL}, + {"ifret16", "", 0x83ff, 2, ATTR (IFC_EXT), 0, NULL, 0, NULL}, + + /* Saturation ext ISA. */ + {"kaddw", "=rt,%ra,%rb", ALU2 (KADD), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"ksubw", "=rt,%ra,%rb", ALU2 (KSUB), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"kdmbb", "=rt,%ra,%rb", ALU2 (KMxy), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"kslraw", "=rt,%ra,%rb", ALU2 (KSLRA), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"rdov", "=rt", ALU2 (MFUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + {"clrov", "", ALU2 (MTUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL}, + + /* Audio ext. instructions. */ + + {"amtari", "%aridxi,%imm16", AUDIO (AMTARI), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMADD */ + {"alr2", "=a_rt,=a_ru,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x1 << 6), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADD) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADD) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADD) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADD) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"alr", "=a_rt,[%im5_i],%im5_m", AUDIO (AMADD) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amadd", "=a_dx,%ra,%rb", AUDIO (AMADD), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabbs", "=a_dx,%ra,%rb", AUDIO (AMADD) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMSUB */ + {"amsubl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUB) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"asr", "%ra,[%im5_i],%im5_m", AUDIO (AMSUB) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsub", "=a_dx,%ra,%rb", AUDIO (AMSUB), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabts", "=a_dx,%ra,%rb", AUDIO (AMSUB) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMULT */ + {"amultl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULT) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULT) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULT) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultsa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULT) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ala", "=dxh,[%im5_i],%im5_m", AUDIO (AMULT) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amult", "=a_dx,%ra,%rb", AUDIO (AMULT), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amatbs", "=a_dx,%ra,%rb", AUDIO (AMULT) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"asats48", "=a_dx", AUDIO (AMULT) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"awext", "%ra,%a_dx,%i5u", AUDIO (AMULT) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMFAR */ + {"amatts", "=a_dx,%ra,%rb", AUDIO (AMFAR) | 0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"asa", "=dxh,[%im5_i],%im5_m", AUDIO (AMFAR) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtar", "%ra,%aridx", AUDIO (AMFAR) | (0x02 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtar2", "%ra,%aridx2", AUDIO (AMFAR) | (0x12 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amfar", "=ra,%aridx", AUDIO (AMFAR) | (0x03 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amfar2", "=ra,%aridx2", AUDIO (AMFAR) | (0x13 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMADDS */ + {"amaddsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMADDS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amaddssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMADDS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"aupi", "%im5_i,%im5_m", AUDIO (AMADDS) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amadds", "=a_dx,%ra,%rb", AUDIO (AMADDS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawbs", "=a_dx,%ra,%rb", AUDIO (AMADDS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMSUBS */ + {"amsubsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMSUBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMSUBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amsubs", "=a_dx,%ra,%rb", AUDIO (AMSUBS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawts", "=a_dx,%ra,%rb", AUDIO (AMSUBS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMULTS */ + {"amultsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMULTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amultssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMULTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amults", "=a_dx,%ra,%rb", AUDIO (AMULTS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwbs", "=a_dx,%ra,%rb", AUDIO (AMULTS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMNEGS */ + {"amnegsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amnegsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amnegsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amnegsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMNEGS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amnegssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMNEGS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amnegs", "=a_dx,%ra,%rb", AUDIO (AMNEGS), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x01, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwts", "=a_dx,%ra,%rb", AUDIO (AMNEGS) |0x02, 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AADDL */ + {"aaddl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"asubl", "=a_rte69,%ra,%rb,%a_rte69_1,[%im5_i],%im5_m", AUDIO (AADDL) | (0x01 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMAWBS */ + {"amawbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMAWTS */ + {"amawtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMAWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amawtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMAWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMWBS */ + {"amwbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMWTS */ + {"amwtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMWTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amwtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMWTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMABBS */ + {"amabbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMABTS */ + {"amabtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMABTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amabtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMABTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMATBS */ + {"amatbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amatbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amatbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amatbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amatbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMATTS */ + {"amattsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amattsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amattsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amattsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMATTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amattssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMATTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMBBS */ + {"ambbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMBTS */ + {"ambtsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambtsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambtsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambtsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMBTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"ambtssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMBTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMTBS */ + {"amtbsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtbsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtbsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtbsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTBS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amtbssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTBS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + /* N32_AEXT_AMTTS */ + {"amttsl.s", "=a_dx,%ra,%rb,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x04 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amttsl.l", "=a_dx,%a_a30,%a_b20,%a_rt21,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x06 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amttsl2.s", "=a_dx,%ra,%rb,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x08 << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amttsl2.l", "=a_dx,%a_a30,%a_b20,%a_rte,%a_rte1,[%im6_ip],[%im6_iq],%im6_mr,%im6_ms", AUDIO (AMTTS) | (0x0A << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {"amttssa", "=a_dx,%ra,%rb,%dhy,[%im5_i],%im5_m", AUDIO (AMTTS) | (0x0C << 5), 4, ATTR (AUDIO_ISAEXT), 0, NULL, 0, NULL}, + {NULL, NULL, 0, 0, 0, 0, NULL, 0, NULL}, }; -static const keyword_t keyword_gpr[] = +const keyword_t keyword_gpr[] = { + /* Standard names. */ {"r0", 0, ATTR (RDREG)}, {"r1", 1, ATTR (RDREG)}, {"r2", 2, ATTR (RDREG)}, {"r3", 3, ATTR (RDREG)}, {"r4", 4, ATTR (RDREG)}, {"r5", 5, ATTR (RDREG)}, {"r6", 6, ATTR (RDREG)}, {"r7", 7, ATTR (RDREG)}, {"r8", 8, ATTR (RDREG)}, - {"r9", 9, ATTR (RDREG)}, {"r10", 10, ATTR (RDREG)}, - {"r11", 11, 0}, {"r12", 12, 0}, {"r13", 13, 0}, {"r14", 14, 0}, - {"r15", 15, ATTR (RDREG)}, - {"r16", 16, 0}, {"r17", 17, 0}, {"r18", 18, 0}, {"r19", 19, 0}, {"r20", 20, 0}, - {"r21", 21, 0}, {"r22", 22, 0}, {"r23", 23, 0}, {"r24", 24, 0}, {"r25", 25, 0}, + {"r9", 9, ATTR (RDREG)}, {"r10", 10, ATTR (RDREG)}, {"r11", 11, 0}, + {"r12", 12, 0}, {"r13", 13, 0}, {"r14", 14, 0}, {"r15", 15, ATTR (RDREG)}, + {"r16", 16, 0}, {"r17", 17, 0}, {"r18", 18, 0}, {"r19", 19, 0}, + {"r20", 20, 0}, {"r21", 21, 0}, {"r22", 22, 0}, {"r23", 23, 0}, + {"r24", 24, 0}, {"r25", 25, 0}, + {"p0", 26, 0}, {"p1", 27, 0}, + {"fp", 28, ATTR (RDREG)}, {"gp", 29, ATTR (RDREG)}, + {"lp", 30, ATTR (RDREG)}, {"sp", 31, ATTR (RDREG)}, {"r26", 26, 0}, {"r27", 27, 0}, {"r28", 28, ATTR (RDREG)}, {"r29", 29, ATTR (RDREG)}, {"r30", 30, ATTR (RDREG)}, {"r31", 31, ATTR (RDREG)}, - - {"ta", 15, ATTR (RDREG)}, {"p0", 26, 0}, {"p1", 27, 0}, - {"fp", 28, ATTR (RDREG)}, {"gp", 29, ATTR (RDREG)}, - {"lp", 30, ATTR (RDREG)}, {"sp", 31, ATTR (RDREG)}, - + /* Names for parameter passing. */ + {"a0", 0, ATTR (RDREG)}, {"a1", 1, ATTR (RDREG)}, + {"a2", 2, ATTR (RDREG)}, {"a3", 3, ATTR (RDREG)}, + {"a4", 4, ATTR (RDREG)}, {"a5", 5, ATTR (RDREG)}, + /* Names reserved for 5-bit addressing only. */ + {"s0", 6, ATTR (RDREG)}, {"s1", 7, ATTR (RDREG)}, + {"s2", 8, ATTR (RDREG)}, {"s3", 9, ATTR (RDREG)}, + {"s4", 10, ATTR (RDREG)}, {"s5", 11, 0}, {"s6", 12, 0}, {"s7", 13, 0}, + {"s8", 14, 0}, {"s9", 28, ATTR (RDREG)}, + {"ta", 15, ATTR (RDREG)}, + {"t0", 16, 0}, {"t1", 17, 0}, {"t2", 18, 0}, {"t3", 19, 0}, + {"t4", 20, 0}, {"t5", 21, 0}, {"t6", 22, 0}, {"t7", 23, 0}, + {"t8", 24, 0}, {"t9", 25, 0}, + /* Names reserved for 4-bit addressing only. */ + {"h0", 0, ATTR (RDREG)}, {"h1", 1, ATTR (RDREG)}, + {"h2", 2, ATTR (RDREG)}, {"h3", 3, ATTR (RDREG)}, + {"h4", 4, ATTR (RDREG)}, {"h5", 5, ATTR (RDREG)}, + {"h6", 6, ATTR (RDREG)}, {"h7", 7, ATTR (RDREG)}, + {"h8", 8, ATTR (RDREG)}, {"h9", 9, ATTR (RDREG)}, + {"h10", 10, ATTR (RDREG)}, {"h11", 11, 0}, + {"h12", 16, 0}, {"h13", 17, 0}, {"h14", 18, 0}, {"h15", 19, 0}, + /* Names reserved for 3-bit addressing only. */ + {"o0", 0, ATTR (RDREG)}, {"o1", 1, ATTR (RDREG)}, + {"o2", 2, ATTR (RDREG)}, {"o3", 3, ATTR (RDREG)}, + {"o4", 4, ATTR (RDREG)}, {"o5", 5, ATTR (RDREG)}, + {"o6", 6, ATTR (RDREG)}, {"o7", 7, ATTR (RDREG)}, {NULL, 0, 0} }; -static const keyword_t keyword_usr[] = +const keyword_t keyword_usr[] = { {"d0.lo", USRIDX (0, 0), 0}, {"d0.hi", USRIDX (0, 1), 0}, @@ -770,163 +1012,164 @@ static const keyword_t keyword_usr[] = {NULL, 0, 0} }; -static const keyword_t keyword_dxr[] = +const keyword_t keyword_dxr[] = { {"d0", 0, 0}, {"d1", 1, 0}, {NULL, 0, 0} }; -static const keyword_t keyword_sr[] = +const keyword_t keyword_sr[] = { - {"cr0", SRIDX (0, 0, 0), 0}, {"cpu_ver", SRIDX (0, 0, 0), 0}, - {"cr1", SRIDX (0, 1, 0), 0}, {"icm_cfg", SRIDX (0, 1, 0), 0}, - {"cr2", SRIDX (0, 2, 0), 0}, {"dcm_cfg", SRIDX (0, 2, 0), 0}, - {"cr3", SRIDX (0, 3, 0), 0}, {"mmu_cfg", SRIDX (0, 3, 0), 0}, - {"cr4", SRIDX (0, 4, 0), 0}, {"msc_cfg", SRIDX (0, 4, 0), 0}, - {"cr5", SRIDX (0, 0, 1), 0}, {"core_id", SRIDX (0, 0, 1), 0}, - {"cr6", SRIDX (0, 5, 0), 0}, {"fucop_exist", SRIDX (0, 5, 0), 0}, - - {"ir0", SRIDX (1, 0, 0), 0}, {"psw", SRIDX (1, 0, 0), 0}, - {"ir1", SRIDX (1, 0, 1), 0}, {"ipsw", SRIDX (1, 0, 1), 0}, - {"ir2", SRIDX (1, 0, 2), 0}, {"p_ipsw", SRIDX (1, 0, 2), 0}, - {"ir3", SRIDX (1, 1, 1), 0}, {"ivb", SRIDX (1, 1, 1), 0}, - {"ir4", SRIDX (1, 2, 1), 0}, {"p_eva", SRIDX (1, 2, 2), 0}, - {"ir5", SRIDX (1, 2, 2), 0}, {"eva", SRIDX (1, 2, 1), 0}, - {"ir6", SRIDX (1, 3, 1), 0}, {"itype", SRIDX (1, 3, 1), 0}, - {"ir7", SRIDX (1, 3, 2), 0}, {"p_itype", SRIDX (1, 3, 2), 0}, - {"ir8", SRIDX (1, 4, 1), 0}, {"merr", SRIDX (1, 4, 1), 0}, - {"ir9", SRIDX (1, 5, 1), 0}, {"ipc", SRIDX (1, 5, 1), 0}, - {"ir10", SRIDX (1, 5, 2), 0}, {"p_ipc", SRIDX (1, 5, 2), 0}, - {"ir11", SRIDX (1, 5, 3), 0}, {"oipc", SRIDX (1, 5, 3), 0}, - {"ir12", SRIDX (1, 6, 2), 0}, {"p_p0", SRIDX (1, 6, 2), 0}, - {"ir13", SRIDX (1, 7, 2), 0}, {"p_p1", SRIDX (1, 7, 2), 0}, - {"ir14", SRIDX (1, 8, 0), 0}, {"int_mask", SRIDX (1, 8, 0), 0}, - {"ir15", SRIDX (1, 9, 0), 0}, {"int_pend", SRIDX (1, 9, 0), 0}, - {"ir16", SRIDX (1, 10, 0), 0}, {"sp_usr", SRIDX (1, 10, 0), 0}, - {"ir17", SRIDX (1, 10, 1), 0}, {"sp_priv", SRIDX (1, 10, 1), 0}, - {"ir18", SRIDX (1, 11, 0), 0}, {"int_pri", SRIDX (1, 11, 0), 0}, - {"ir19", SRIDX (1, 1, 2), 0}, {"int_ctrl", SRIDX (1, 1, 2), 0}, - {"ir20", SRIDX (1, 10, 2), 0}, {"sp_usr1", SRIDX (1, 10, 2), 0}, - {"ir21", SRIDX (1, 10, 3), 0}, {"sp_priv1", SRIDX (1, 10, 3), 0}, - {"ir22", SRIDX (1, 10, 4), 0}, {"sp_usr2", SRIDX (1, 10, 4), 0}, - {"ir23", SRIDX (1, 10, 5), 0}, {"sp_priv2", SRIDX (1, 10, 5), 0}, - {"ir24", SRIDX (1, 10, 6), 0}, {"sp_usr3", SRIDX (1, 10, 6), 0}, - {"ir25", SRIDX (1, 10, 7), 0}, {"sp_priv3", SRIDX (1, 10, 7), 0}, - {"ir26", SRIDX (1, 8, 1), 0}, {"int_mask2", SRIDX (1, 8, 1), 0}, - {"ir27", SRIDX (1, 9, 1), 0}, {"int_pend2", SRIDX (1, 9, 1), 0}, - {"ir28", SRIDX (1, 11, 1), 0}, {"int_pri2", SRIDX (1, 11, 1), 0}, - {"ir29", SRIDX (1, 9, 4), 0}, {"int_trigger", SRIDX (1, 9, 4), 0}, - {"ir30", SRIDX (1, 1, 3), 0}, - - {"mr0", SRIDX (2, 0, 0), 0}, {"mmu_ctl", SRIDX (2, 0, 0), 0}, - {"mr1", SRIDX (2, 1, 0), 0}, {"l1_pptb", SRIDX (2, 1, 0), 0}, - {"mr2", SRIDX (2, 2, 0), 0}, {"tlb_vpn", SRIDX (2, 2, 0), 0}, - {"mr3", SRIDX (2, 3, 0), 0}, {"tlb_data", SRIDX (2, 3, 0), 0}, - {"mr4", SRIDX (2, 4, 0), 0}, {"tlb_misc", SRIDX (2, 4, 0), 0}, - {"mr5", SRIDX (2, 5, 0), 0}, {"vlpt_idx", SRIDX (2, 5, 0), 0}, - {"mr6", SRIDX (2, 6, 0), 0}, {"ilmb", SRIDX (2, 6, 0), 0}, - {"mr7", SRIDX (2, 7, 0), 0}, {"dlmb", SRIDX (2, 7, 0), 0}, - {"mr8", SRIDX (2, 8, 0), 0}, {"cache_ctl", SRIDX (2, 8, 0), 0}, - {"mr9", SRIDX (2, 9, 0), 0}, {"hsmp_saddr", SRIDX (2, 9, 0), 0}, - {"mr10", SRIDX (2, 9, 1), 0}, {"hsmp_eaddr", SRIDX (2, 9, 1), 0}, - {"mr11", SRIDX (2, 0, 1), 0}, {"bg_region", SRIDX (2, 0, 1), 0}, - - {"pfr0", SRIDX (4, 0, 0), 0}, {"pfmc0", SRIDX (4, 0, 0), 0}, - {"pfr1", SRIDX (4, 0, 1), 0}, {"pfmc1", SRIDX (4, 0, 1), 0}, - {"pfr2", SRIDX (4, 0, 2), 0}, {"pfmc2", SRIDX (4, 0, 2), 0}, - {"pfr3", SRIDX (4, 1, 0), 0}, {"pfm_ctl", SRIDX (4, 1, 0), 0}, - - {"dmar0", SRIDX (5, 0, 0), 0}, {"dma_cfg", SRIDX (5, 0, 0), 0}, - {"dmar1", SRIDX (5, 1, 0), 0}, {"dma_gcsw", SRIDX (5, 1, 0), 0}, - {"dmar2", SRIDX (5, 2, 0), 0}, {"dma_chnsel", SRIDX (5, 2, 0), 0}, - {"dmar3", SRIDX (5, 3, 0), 0}, {"dma_act", SRIDX (5, 3, 0), 0}, - {"dmar4", SRIDX (5, 4, 0), 0}, {"dma_setup", SRIDX (5, 4, 0), 0}, - {"dmar5", SRIDX (5, 5, 0), 0}, {"dma_isaddr", SRIDX (5, 5, 0), 0}, - {"dmar6", SRIDX (5, 6, 0), 0}, {"dma_esaddr", SRIDX (5, 6, 0), 0}, - {"dmar7", SRIDX (5, 7, 0), 0}, {"dma_tcnt", SRIDX (5, 7, 0), 0}, - {"dmar8", SRIDX (5, 8, 0), 0}, {"dma_status", SRIDX (5, 8, 0), 0}, - {"dmar9", SRIDX (5, 9, 0), 0}, {"dma_2dset", SRIDX (5, 9, 0), 0}, - {"dmar10", SRIDX (5, 9, 1), 0}, {"dma_2dsctl", SRIDX (5, 9, 1), 0}, - {"dmar11", SRIDX (5, 7, 1), 0}, {"dma_rcnt", SRIDX (5, 7, 1), 0}, - {"dmar12", SRIDX (5, 8, 1), 0}, {"dma_hstatus", SRIDX (5, 8, 1), 0}, - - {"idr0", SRIDX (2, 15, 0), 0}, {"sdz_ctl", SRIDX (2, 15, 0), 0}, - {"idr1", SRIDX (2, 15, 1), 0}, {"n12misc_ctl", SRIDX (2, 15, 1), 0}, - {"misc_ctl", SRIDX (2, 15, 1), 0}, - - {"secur0", SRIDX (6, 0, 0), 0}, {"sfcr", SRIDX (6, 0, 0), 0}, + {"cpu_ver", SRIDX (0, 0, 0), 0}, {"cr0", SRIDX (0, 0, 0), 0}, + {"icm_cfg", SRIDX (0, 1, 0), 0}, {"cr1", SRIDX (0, 1, 0), 0}, + {"dcm_cfg", SRIDX (0, 2, 0), 0}, {"cr2", SRIDX (0, 2, 0), 0}, + {"mmu_cfg", SRIDX (0, 3, 0), 0}, {"cr3", SRIDX (0, 3, 0), 0}, + {"msc_cfg", SRIDX (0, 4, 0), 0}, {"cr4", SRIDX (0, 4, 0), 0}, + {"core_id", SRIDX (0, 0, 1), 0}, {"cr5", SRIDX (0, 0, 1), 0}, + {"fucop_exist", SRIDX (0, 5, 0), 0}, {"cr6", SRIDX (0, 5, 0), 0}, + + {"psw", SRIDX (1, 0, 0), 0}, {"ir0", SRIDX (1, 0, 0), 0}, + {"ipsw", SRIDX (1, 0, 1), 0}, {"ir1", SRIDX (1, 0, 1), 0}, + {"p_ipsw", SRIDX (1, 0, 2), 0}, {"ir2", SRIDX (1, 0, 2), 0}, + {"ivb", SRIDX (1, 1, 1), 0}, {"ir3", SRIDX (1, 1, 1), 0}, + {"eva", SRIDX (1, 2, 1), 0}, {"ir4", SRIDX (1, 2, 1), 0}, + {"p_eva", SRIDX (1, 2, 2), 0}, {"ir5", SRIDX (1, 2, 2), 0}, + {"itype", SRIDX (1, 3, 1), 0}, {"ir6", SRIDX (1, 3, 1), 0}, + {"p_itype", SRIDX (1, 3, 2), 0}, {"ir7", SRIDX (1, 3, 2), 0}, + {"merr", SRIDX (1, 4, 1), 0}, {"ir8", SRIDX (1, 4, 1), 0}, + {"ipc", SRIDX (1, 5, 1), 0}, {"ir9", SRIDX (1, 5, 1), 0}, + {"p_ipc", SRIDX (1, 5, 2), 0}, {"ir10", SRIDX (1, 5, 2), 0}, + {"oipc", SRIDX (1, 5, 3), 0}, {"ir11", SRIDX (1, 5, 3), 0}, + {"p_p0", SRIDX (1, 6, 2), 0}, {"ir12", SRIDX (1, 6, 2), 0}, + {"p_p1", SRIDX (1, 7, 2), 0}, {"ir13", SRIDX (1, 7, 2), 0}, + {"int_mask", SRIDX (1, 8, 0), 0}, {"ir14", SRIDX (1, 8, 0), 0}, + {"int_pend", SRIDX (1, 9, 0), 0}, {"ir15", SRIDX (1, 9, 0), 0}, + {"sp_usr", SRIDX (1, 10, 0), 0}, {"ir16", SRIDX (1, 10, 0), 0}, + {"sp_priv", SRIDX (1, 10, 1), 0}, {"ir17", SRIDX (1, 10, 1), 0}, + {"int_pri", SRIDX (1, 11, 0), 0}, {"ir18", SRIDX (1, 11, 0), 0}, + {"int_ctrl", SRIDX (1, 1, 2), 0}, {"ir19", SRIDX (1, 1, 2), 0}, + {"sp_usr1", SRIDX (1, 10, 2), 0}, {"ir20", SRIDX (1, 10, 2), 0}, + {"sp_priv1", SRIDX (1, 10, 3), 0}, {"ir21", SRIDX (1, 10, 3), 0}, + {"sp_usr2", SRIDX (1, 10, 4), 0}, {"ir22", SRIDX (1, 10, 4), 0}, + {"sp_priv2", SRIDX (1, 10, 5), 0}, {"ir23", SRIDX (1, 10, 5), 0}, + {"sp_usr3", SRIDX (1, 10, 6), 0}, {"ir24", SRIDX (1, 10, 6), 0}, + {"sp_priv3", SRIDX (1, 10, 7), 0}, {"ir25", SRIDX (1, 10, 7), 0}, + {"int_mask2", SRIDX (1, 8, 1), 0}, {"ir26", SRIDX (1, 8, 1), 0}, + {"int_pend2", SRIDX (1, 9, 1), 0}, {"ir27", SRIDX (1, 9, 1), 0}, + {"int_pri2", SRIDX (1, 11, 1), 0}, {"ir28", SRIDX (1, 11, 1), 0}, + {"int_trigger", SRIDX (1, 9, 4), 0}, {"ir29", SRIDX (1, 9, 4), 0}, + {"int_gpr_push_dis", SRIDX(1, 1, 3), 0}, {"ir30", SRIDX (1, 1, 3), 0}, + + {"mmu_ctl", SRIDX (2, 0, 0), 0}, {"mr0", SRIDX (2, 0, 0), 0}, + {"l1_pptb", SRIDX (2, 1, 0), 0}, {"mr1", SRIDX (2, 1, 0), 0}, + {"tlb_vpn", SRIDX (2, 2, 0), 0}, {"mr2", SRIDX (2, 2, 0), 0}, + {"tlb_data", SRIDX (2, 3, 0), 0}, {"mr3", SRIDX (2, 3, 0), 0}, + {"tlb_misc", SRIDX (2, 4, 0), 0}, {"mr4", SRIDX (2, 4, 0), 0}, + {"vlpt_idx", SRIDX (2, 5, 0), 0}, {"mr5", SRIDX (2, 5, 0), 0}, + {"ilmb", SRIDX (2, 6, 0), 0}, {"mr6", SRIDX (2, 6, 0), 0}, + {"dlmb", SRIDX (2, 7, 0), 0}, {"mr7", SRIDX (2, 7, 0), 0}, + {"cache_ctl", SRIDX (2, 8, 0), 0}, {"mr8", SRIDX (2, 8, 0), 0}, + {"hsmp_saddr", SRIDX (2, 9, 0), 0}, {"mr9", SRIDX (2, 9, 0), 0}, + {"hsmp_eaddr", SRIDX (2, 9, 1), 0}, {"mr10", SRIDX (2, 9, 1), 0}, + {"bg_region", SRIDX (2, 0, 1), 0}, {"mr11", SRIDX (2, 0, 1), 0}, + + {"pfmc0", SRIDX (4, 0, 0), 0}, {"pfr0", SRIDX (4, 0, 0), 0}, + {"pfmc1", SRIDX (4, 0, 1), 0}, {"pfr1", SRIDX (4, 0, 1), 0}, + {"pfmc2", SRIDX (4, 0, 2), 0}, {"pfr2", SRIDX (4, 0, 2), 0}, + {"pfm_ctl", SRIDX (4, 1, 0), 0}, {"pfr3", SRIDX (4, 1, 0), 0}, + + {"dma_cfg", SRIDX (5, 0, 0), 0}, {"dmar0", SRIDX (5, 0, 0), 0}, + {"dma_gcsw", SRIDX (5, 1, 0), 0}, {"dmar1", SRIDX (5, 1, 0), 0}, + {"dma_chnsel", SRIDX (5, 2, 0), 0}, {"dmar2", SRIDX (5, 2, 0), 0}, + {"dma_act", SRIDX (5, 3, 0), 0}, {"dmar3", SRIDX (5, 3, 0), 0}, + {"dma_setup", SRIDX (5, 4, 0), 0}, {"dmar4", SRIDX (5, 4, 0), 0}, + {"dma_isaddr", SRIDX (5, 5, 0), 0}, {"dmar5", SRIDX (5, 5, 0), 0}, + {"dma_esaddr", SRIDX (5, 6, 0), 0}, {"dmar6", SRIDX (5, 6, 0), 0}, + {"dma_tcnt", SRIDX (5, 7, 0), 0}, {"dmar7", SRIDX (5, 7, 0), 0}, + {"dma_status", SRIDX (5, 8, 0), 0}, {"dmar8", SRIDX (5, 8, 0), 0}, + {"dma_2dset", SRIDX (5, 9, 0), 0}, {"dmar9", SRIDX (5, 9, 0), 0}, + {"dma_2dsctl", SRIDX (5, 9, 1), 0}, {"dmar10", SRIDX (5, 9, 1), 0}, + {"dma_rcnt", SRIDX (5, 7, 1), 0}, {"dmar11", SRIDX (5, 7, 1), 0}, + {"dma_hstatus", SRIDX (5, 8, 1), 0}, {"dmar12", SRIDX (5, 8, 1), 0}, + + {"sdz_ctl", SRIDX (2, 15, 0), 0}, {"idr0", SRIDX (2, 15, 0), 0}, + {"misc_ctl", SRIDX (2, 15, 1), 0}, {"n12misc_ctl", SRIDX (2, 15, 1), 0}, + {"idr1", SRIDX (2, 15, 1), 0}, + + {"secur0", SRIDX (6, 0, 0), 0}, {"sfcr", SRIDX (6, 0, 0), 0}, {"prusr_acc_ctl", SRIDX (4, 4, 0), 0}, - {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0}, - - {"dr0", SRIDX (3, 0, 0), 0}, {"bpc0", SRIDX (3, 0, 0), 0}, - {"dr1", SRIDX (3, 0, 1), 0}, {"bpc1", SRIDX (3, 0, 1), 0}, - {"dr2", SRIDX (3, 0, 2), 0}, {"bpc2", SRIDX (3, 0, 2), 0}, - {"dr3", SRIDX (3, 0, 3), 0}, {"bpc3", SRIDX (3, 0, 3), 0}, - {"dr4", SRIDX (3, 0, 4), 0}, {"bpc4", SRIDX (3, 0, 4), 0}, - {"dr5", SRIDX (3, 0, 5), 0}, {"bpc5", SRIDX (3, 0, 5), 0}, - {"dr6", SRIDX (3, 0, 6), 0}, {"bpc6", SRIDX (3, 0, 6), 0}, - {"dr7", SRIDX (3, 0, 7), 0}, {"bpc7", SRIDX (3, 0, 7), 0}, - {"dr8", SRIDX (3, 1, 0), 0}, {"bpa0", SRIDX (3, 1, 0), 0}, - {"dr9", SRIDX (3, 1, 1), 0}, {"bpa1", SRIDX (3, 1, 1), 0}, - {"dr10", SRIDX (3, 1, 2), 0}, {"bpa2", SRIDX (3, 1, 2), 0}, - {"dr11", SRIDX (3, 1, 3), 0}, {"bpa3", SRIDX (3, 1, 3), 0}, - {"dr12", SRIDX (3, 1, 4), 0}, {"bpa4", SRIDX (3, 1, 4), 0}, - {"dr13", SRIDX (3, 1, 5), 0}, {"bpa5", SRIDX (3, 1, 5), 0}, - {"dr14", SRIDX (3, 1, 6), 0}, {"bpa6", SRIDX (3, 1, 6), 0}, - {"dr15", SRIDX (3, 1, 7), 0}, {"bpa7", SRIDX (3, 1, 7), 0}, - {"dr16", SRIDX (3, 2, 0), 0}, {"bpam0", SRIDX (3, 2, 0), 0}, - {"dr17", SRIDX (3, 2, 1), 0}, {"bpam1", SRIDX (3, 2, 1), 0}, - {"dr18", SRIDX (3, 2, 2), 0}, {"bpam2", SRIDX (3, 2, 2), 0}, - {"dr19", SRIDX (3, 2, 3), 0}, {"bpam3", SRIDX (3, 2, 3), 0}, - {"dr20", SRIDX (3, 2, 4), 0}, {"bpam4", SRIDX (3, 2, 4), 0}, - {"dr21", SRIDX (3, 2, 5), 0}, {"bpam5", SRIDX (3, 2, 5), 0}, - {"dr22", SRIDX (3, 2, 6), 0}, {"bpam6", SRIDX (3, 2, 6), 0}, - {"dr23", SRIDX (3, 2, 7), 0}, {"bpam7", SRIDX (3, 2, 7), 0}, - {"dr24", SRIDX (3, 3, 0), 0}, {"bpv0", SRIDX (3, 3, 0), 0}, - {"dr25", SRIDX (3, 3, 1), 0}, {"bpv1", SRIDX (3, 3, 1), 0}, - {"dr26", SRIDX (3, 3, 2), 0}, {"bpv2", SRIDX (3, 3, 2), 0}, - {"dr27", SRIDX (3, 3, 3), 0}, {"bpv3", SRIDX (3, 3, 3), 0}, - {"dr28", SRIDX (3, 3, 4), 0}, {"bpv4", SRIDX (3, 3, 4), 0}, - {"dr29", SRIDX (3, 3, 5), 0}, {"bpv5", SRIDX (3, 3, 5), 0}, - {"dr30", SRIDX (3, 3, 6), 0}, {"bpv6", SRIDX (3, 3, 6), 0}, - {"dr31", SRIDX (3, 3, 7), 0}, {"bpv7", SRIDX (3, 3, 7), 0}, - {"dr32", SRIDX (3, 4, 0), 0}, {"bpcid0", SRIDX (3, 4, 0), 0}, - {"dr33", SRIDX (3, 4, 1), 0}, {"bpcid1", SRIDX (3, 4, 1), 0}, - {"dr34", SRIDX (3, 4, 2), 0}, {"bpcid2", SRIDX (3, 4, 2), 0}, - {"dr35", SRIDX (3, 4, 3), 0}, {"bpcid3", SRIDX (3, 4, 3), 0}, - {"dr36", SRIDX (3, 4, 4), 0}, {"bpcid4", SRIDX (3, 4, 4), 0}, - {"dr37", SRIDX (3, 4, 5), 0}, {"bpcid5", SRIDX (3, 4, 5), 0}, - {"dr38", SRIDX (3, 4, 6), 0}, {"bpcid6", SRIDX (3, 4, 6), 0}, - {"dr39", SRIDX (3, 4, 7), 0}, {"bpcid7", SRIDX (3, 4, 7), 0}, - {"dr40", SRIDX (3, 5, 0), 0}, {"edm_cfg", SRIDX (3, 5, 0), 0}, - {"dr41", SRIDX (3, 6, 0), 0}, {"edmsw", SRIDX (3, 6, 0), 0}, - {"dr42", SRIDX (3, 7, 0), 0}, {"edm_ctl", SRIDX (3, 7, 0), 0}, - {"dr43", SRIDX (3, 8, 0), 0}, {"edm_dtr", SRIDX (3, 8, 0), 0}, - {"dr44", SRIDX (3, 9, 0), 0}, {"bpmtc", SRIDX (3, 9, 0), 0}, - {"dr45", SRIDX (3, 10, 0), 0}, {"dimbr", SRIDX (3, 10, 0), 0}, - {"dr46", SRIDX (3, 14, 0), 0}, {"tecr0", SRIDX (3, 14, 0), 0}, - {"dr47", SRIDX (3, 14, 1), 0}, {"tecr1", SRIDX (3, 14, 1), 0}, + {"fucpr", SRIDX (4, 5, 0), 0}, {"fucop_ctl", SRIDX (4, 5, 0), 0}, + + {"bpc0", SRIDX (3, 0, 0), 0}, {"dr0", SRIDX (3, 0, 0), 0}, + {"bpc1", SRIDX (3, 0, 1), 0}, {"dr1", SRIDX (3, 0, 1), 0}, + {"bpc2", SRIDX (3, 0, 2), 0}, {"dr2", SRIDX (3, 0, 2), 0}, + {"bpc3", SRIDX (3, 0, 3), 0}, {"dr3", SRIDX (3, 0, 3), 0}, + {"bpc4", SRIDX (3, 0, 4), 0}, {"dr4", SRIDX (3, 0, 4), 0}, + {"bpc5", SRIDX (3, 0, 5), 0}, {"dr5", SRIDX (3, 0, 5), 0}, + {"bpc6", SRIDX (3, 0, 6), 0}, {"dr6", SRIDX (3, 0, 6), 0}, + {"bpc7", SRIDX (3, 0, 7), 0}, {"dr7", SRIDX (3, 0, 7), 0}, + {"bpa0", SRIDX (3, 1, 0), 0}, {"dr8", SRIDX (3, 1, 0), 0}, + {"bpa1", SRIDX (3, 1, 1), 0}, {"dr9", SRIDX (3, 1, 1), 0}, + {"bpa2", SRIDX (3, 1, 2), 0}, {"dr10", SRIDX (3, 1, 2), 0}, + {"bpa3", SRIDX (3, 1, 3), 0}, {"dr11", SRIDX (3, 1, 3), 0}, + {"bpa4", SRIDX (3, 1, 4), 0}, {"dr12", SRIDX (3, 1, 4), 0}, + {"bpa5", SRIDX (3, 1, 5), 0}, {"dr13", SRIDX (3, 1, 5), 0}, + {"bpa6", SRIDX (3, 1, 6), 0}, {"dr14", SRIDX (3, 1, 6), 0}, + {"bpa7", SRIDX (3, 1, 7), 0}, {"dr15", SRIDX (3, 1, 7), 0}, + {"bpam0", SRIDX (3, 2, 0), 0}, {"dr16", SRIDX (3, 2, 0), 0}, + {"bpam1", SRIDX (3, 2, 1), 0}, {"dr17", SRIDX (3, 2, 1), 0}, + {"bpam2", SRIDX (3, 2, 2), 0}, {"dr18", SRIDX (3, 2, 2), 0}, + {"bpam3", SRIDX (3, 2, 3), 0}, {"dr19", SRIDX (3, 2, 3), 0}, + {"bpam4", SRIDX (3, 2, 4), 0}, {"dr20", SRIDX (3, 2, 4), 0}, + {"bpam5", SRIDX (3, 2, 5), 0}, {"dr21", SRIDX (3, 2, 5), 0}, + {"bpam6", SRIDX (3, 2, 6), 0}, {"dr22", SRIDX (3, 2, 6), 0}, + {"bpam7", SRIDX (3, 2, 7), 0}, {"dr23", SRIDX (3, 2, 7), 0}, + {"bpv0", SRIDX (3, 3, 0), 0}, {"dr24", SRIDX (3, 3, 0), 0}, + {"bpv1", SRIDX (3, 3, 1), 0}, {"dr25", SRIDX (3, 3, 1), 0}, + {"bpv2", SRIDX (3, 3, 2), 0}, {"dr26", SRIDX (3, 3, 2), 0}, + {"bpv3", SRIDX (3, 3, 3), 0}, {"dr27", SRIDX (3, 3, 3), 0}, + {"bpv4", SRIDX (3, 3, 4), 0}, {"dr28", SRIDX (3, 3, 4), 0}, + {"bpv5", SRIDX (3, 3, 5), 0}, {"dr29", SRIDX (3, 3, 5), 0}, + {"bpv6", SRIDX (3, 3, 6), 0}, {"dr30", SRIDX (3, 3, 6), 0}, + {"bpv7", SRIDX (3, 3, 7), 0}, {"dr31", SRIDX (3, 3, 7), 0}, + {"bpcid0", SRIDX (3, 4, 0), 0}, {"dr32", SRIDX (3, 4, 0), 0}, + {"bpcid1", SRIDX (3, 4, 1), 0}, {"dr33", SRIDX (3, 4, 1), 0}, + {"bpcid2", SRIDX (3, 4, 2), 0}, {"dr34", SRIDX (3, 4, 2), 0}, + {"bpcid3", SRIDX (3, 4, 3), 0}, {"dr35", SRIDX (3, 4, 3), 0}, + {"bpcid4", SRIDX (3, 4, 4), 0}, {"dr36", SRIDX (3, 4, 4), 0}, + {"bpcid5", SRIDX (3, 4, 5), 0}, {"dr37", SRIDX (3, 4, 5), 0}, + {"bpcid6", SRIDX (3, 4, 6), 0}, {"dr38", SRIDX (3, 4, 6), 0}, + {"bpcid7", SRIDX (3, 4, 7), 0}, {"dr39", SRIDX (3, 4, 7), 0}, + {"edm_cfg", SRIDX (3, 5, 0), 0}, {"dr40", SRIDX (3, 5, 0), 0}, + {"edmsw", SRIDX (3, 6, 0), 0}, {"dr41", SRIDX (3, 6, 0), 0}, + {"edm_ctl", SRIDX (3, 7, 0), 0}, {"dr42", SRIDX (3, 7, 0), 0}, + {"edm_dtr", SRIDX (3, 8, 0), 0}, {"dr43", SRIDX (3, 8, 0), 0}, + {"bpmtc", SRIDX (3, 9, 0), 0}, {"dr44", SRIDX (3, 9, 0), 0}, + {"dimbr", SRIDX (3, 10, 0), 0}, {"dr45", SRIDX (3, 10, 0), 0}, + {"tecr0", SRIDX (3, 14, 0), 0}, {"dr46", SRIDX (3, 14, 0), 0}, + {"tecr1", SRIDX (3, 14, 1), 0}, {"dr47", SRIDX (3, 14, 1), 0}, {NULL,0 ,0} }; -static const keyword_t keyword_cp[] = +const keyword_t keyword_cp[] = { {"cp0", 0, 0}, {"cp1", 1, 0}, {"cp2", 2, 0}, {"cp3", 3, 0}, {NULL, 0, 0} }; -static const keyword_t keyword_cpr[] = +const keyword_t keyword_cpr[] = { - {"cpr0", 0, 0}, {"cpr1", 1, 0}, {"cpr2", 2, 0}, {"cpr3", 3, 0}, {"cpr4", 4, 0}, - {"cpr5", 5, 0}, {"cpr6", 6, 0}, {"cpr7", 7, 0}, {"cpr8", 8, 0}, {"cpr9", 9, 0}, - {"cpr10", 10, 0}, {"cpr11", 11, 0}, {"cpr12", 12, 0}, {"cpr13", 13, 0}, - {"cpr14", 14, 0}, {"cpr15", 15, 0}, {"cpr16", 16, 0}, {"cpr17", 17, 0}, - {"cpr18", 18, 0}, {"cpr19", 19, 0}, {"cpr20", 20, 0}, {"cpr21", 21, 0}, - {"cpr22", 22, 0}, {"cpr23", 23, 0}, {"cpr24", 24, 0}, {"cpr25", 25, 0}, - {"cpr26", 26, 0}, {"cpr27", 27, 0}, {"cpr28", 28, 0}, {"cpr29", 29, 0}, - {"cpr30", 30, 0}, {"cpr31", 31, 0}, {NULL, 0, 0} + {"cpr0", 0, 0}, {"cpr1", 1, 0}, {"cpr2", 2, 0}, {"cpr3", 3, 0}, + {"cpr4", 4, 0}, {"cpr5", 5, 0}, {"cpr6", 6, 0}, {"cpr7", 7, 0}, + {"cpr8", 8, 0}, {"cpr9", 9, 0}, {"cpr10", 10, 0}, {"cpr11", 11, 0}, + {"cpr12", 12, 0}, {"cpr13", 13, 0}, {"cpr14", 14, 0}, {"cpr15", 15, 0}, + {"cpr16", 16, 0}, {"cpr17", 17, 0}, {"cpr18", 18, 0}, {"cpr19", 19, 0}, + {"cpr20", 20, 0}, {"cpr21", 21, 0}, {"cpr22", 22, 0}, {"cpr23", 23, 0}, + {"cpr24", 24, 0}, {"cpr25", 25, 0}, {"cpr26", 26, 0}, {"cpr27", 27, 0}, + {"cpr28", 28, 0}, {"cpr29", 29, 0}, {"cpr30", 30, 0}, {"cpr31", 31, 0}, + {NULL, 0, 0} }; -static const keyword_t keyword_fsr[] = +const keyword_t keyword_fsr[] = { {"fs0", 0, 0}, {"fs1", 1, 0}, {"fs2", 2, 0}, {"fs3", 3, 0}, {"fs4", 4, 0}, {"fs5", 5, 0}, {"fs6", 6, 0}, {"fs7", 7, 0}, {"fs8", 8, 0}, {"fs9", 9, 0}, @@ -938,7 +1181,7 @@ static const keyword_t keyword_fsr[] = {"fs30", 30, 0}, {"fs31", 31, 0}, {NULL, 0 ,0} }; -static const keyword_t keyword_fdr[] = +const keyword_t keyword_fdr[] = { {"fd0", 0, 0}, {"fd1", 1, 0}, {"fd2", 2, 0}, {"fd3", 3, 0}, {"fd4", 4, 0}, {"fd5", 5, 0}, {"fd6", 6, 0}, {"fd7", 7, 0}, {"fd8", 8, 0}, {"fd9", 9, 0}, @@ -950,16 +1193,18 @@ static const keyword_t keyword_fdr[] = {"fd30", 30, 0}, {"fd31", 31, 0}, {NULL, 0, 0} }; -static const keyword_t keyword_abdim[] = +const keyword_t keyword_abdim[] = { {"bi", 0, 0}, {"bim", 1, 0}, {"bd", 2, 0}, {"bdm", 3, 0}, {"ai", 4, 0}, {"aim", 5, 0}, {"ad", 6, 0}, {"adm", 7, 0}, {NULL, 0, 0} }; -static const keyword_t keyword_abm[] = +const keyword_t keyword_abm[] = { - {"b", 0, 0}, {"bm", 1, 0}, {"a", 4, 0}, {"am", 5, 0}, {NULL, 0, 0} + {"b", 0, 0}, {"bm", 1, 0}, {"bx", 2, 0}, {"bmx", 3, 0}, + {"a", 4, 0}, {"am", 5, 0}, {"ax", 6, 0}, {"amx", 7, 0}, + {NULL, 0, 0} }; static const keyword_t keyword_dtiton[] = @@ -972,13 +1217,13 @@ static const keyword_t keyword_dtitoff[] = {"itoff", 1, 0}, {"toff", 3, 0}, {NULL, 0, 0} }; -static const keyword_t keyword_dpref_st[] = +const keyword_t keyword_dpref_st[] = { {"srd", 0, 0}, {"mrd", 1, 0}, {"swr", 2, 0}, {"mwr", 3, 0}, {"pte", 4, 0}, {"clwr", 5, 0}, {NULL, 0, 0} }; -/* CCTL Ra, SubType */ +/* CCTL Ra, SubType. */ static const keyword_t keyword_cctl_st0[] = { {"l1d_ix_inval", 0X0, 0}, {"l1d_ix_wb", 0X1, 0}, {"l1d_ix_wbinval", 0X2, 0}, @@ -987,7 +1232,7 @@ static const keyword_t keyword_cctl_st0[] = {NULL, 0, 0} }; -/* CCTL Ra, SubType, level */ +/* CCTL Ra, SubType, level. */ static const keyword_t keyword_cctl_st1[] = { {"l1d_va_inval", 0X8, 0}, {"l1d_va_wb", 0X9, 0}, @@ -995,7 +1240,7 @@ static const keyword_t keyword_cctl_st1[] = {NULL, 0, 0} }; -/* CCTL Rt, Ra, SubType */ +/* CCTL Rt, Ra, SubType. */ static const keyword_t keyword_cctl_st2[] = { {"l1d_ix_rtag", 0X3, 0}, {"l1d_ix_rwd", 0X4, 0}, @@ -1003,7 +1248,7 @@ static const keyword_t keyword_cctl_st2[] = {NULL, 0, 0} }; -/* CCTL Rb, Ra, SubType */ +/* CCTL Rb, Ra, SubType. */ static const keyword_t keyword_cctl_st3[] = { {"l1d_ix_wtag", 0X5, 0}, {"l1d_ix_wwd", 0X6, 0}, @@ -1011,19 +1256,19 @@ static const keyword_t keyword_cctl_st3[] = {NULL, 0, 0} }; -/* CCTL L1D_INVALALL */ +/* CCTL L1D_INVALALL. */ static const keyword_t keyword_cctl_st4[] = { {"l1d_invalall", 0x7, 0}, {NULL, 0, 0} }; -/* CCTL L1D_WBALL, level */ +/* CCTL L1D_WBALL, level. */ static const keyword_t keyword_cctl_st5[] = { {"l1d_wball", 0xf, 0}, {NULL, 0, 0} }; -static const keyword_t keyword_cctl_lv[] = +const keyword_t keyword_cctl_lv[] = { {"1level", 0, 0}, {"alevel", 1, 0}, {"0", 0, 0}, {"1", 1, 0}, {NULL, 0, 0}, @@ -1031,19 +1276,16 @@ static const keyword_t keyword_cctl_lv[] = static const keyword_t keyword_tlbop_st[] = { - {"trd", 0, 0}, {"targetread", 0, 0}, - {"twr", 1, 0}, {"targetwrite", 1, 0}, - {"rwr", 2, 0}, {"rwrite", 2, 0}, - {"rwlk", 3, 0}, {"rwritelock", 3, 0}, - {"unlk", 4, 0}, {"unlock", 4, 0}, - {"inv", 6, 0}, {"invalidate", 6, 0}, + {"targetread", 0, 0}, {"trd", 0, 0}, + {"targetwrite", 1, 0}, {"twr", 1, 0}, + {"rwrite", 2, 0}, {"rwr", 2, 0}, + {"rwritelock", 3, 0}, {"rwlk", 3, 0}, + {"unlock", 4, 0}, {"unlk", 4, 0}, + {"invalidate", 6, 0}, {"inv", 6, 0}, {NULL, 0, 0}, - /* "pb" requries two operand and "flua" requires none. */ - /* {"pb", 5, 0}, {"probe", 5, 0}, - {"flua", 7, 0}, {"flushall", 0}, */ }; -static const keyword_t keyword_standby_st[] = +const keyword_t keyword_standby_st[] = { {"no_wake_grant", 0, 0}, {"wake_grant", 1, 0}, @@ -1055,12 +1297,73 @@ static const keyword_t keyword_standby_st[] = {NULL, 0, 0}, }; -static const keyword_t keyword_msync_st[] = +const keyword_t keyword_msync_st[] = { {"all", 0, 0}, {"store", 1, 0}, {NULL, 0, 0} }; +const keyword_t keyword_im5_i[] = +{ + {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0}, + {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0}, + {NULL, 0, 0} +}; + +const keyword_t keyword_im5_m[] = +{ + {"m0", 0, 0}, {"m1", 1, 0}, {"m2", 2, 0}, {"m3", 3, 0}, + {"m4", 4, 0}, {"m5", 5, 0}, {"m6", 6, 0}, {"m7", 7, 0}, + {NULL, 0, 0} +}; + +const keyword_t keyword_accumulator[] = +{ + {"d0.lo", 0, 0}, {"d0.hi", 1, 0}, {"d1.lo", 2, 0}, {"d1.hi", 3, 0}, + {NULL, 0, 0} +}; + +const keyword_t keyword_aridx[] = +{ + {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0}, + {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0}, + {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0}, + {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0}, + {"d0.l24", 16, 0}, {"d1.l24", 17, 0}, + {"shft_ctl0", 18, 0}, {"shft_ctl1", 19, 0}, + {"lb", 24, 0}, {"le", 25, 0}, {"lc", 26, 0}, {"adm_vbase", 27, 0}, + {NULL, 0, 0} +}; + +const keyword_t keyword_aridx2[] = +{ + {"cbb0", 0, 0}, {"cbb1", 1, 0}, {"cbb2", 2, 0}, {"cbb3", 3, 0}, + {"cbe0", 4, 0}, {"cbe1", 5, 0}, {"cbe2", 6, 0}, {"cbe3", 7, 0}, + {"cb_ctl", 31, 0}, + {NULL, 0, 0} +}; + +const keyword_t keyword_aridxi[] = +{ + {"i0", 0, 0}, {"i1", 1, 0}, {"i2", 2, 0}, {"i3", 3, 0}, + {"i4", 4, 0}, {"i5", 5, 0}, {"i6", 6, 0}, {"i7", 7, 0}, + {"mod", 8, 0}, {"m1", 9, 0}, {"m2", 10, 0}, {"m3",11, 0}, + {"m5",13, 0}, {"m6",14, 0}, {"m7",15, 0}, + {NULL, 0, 0} +}; + +const keyword_t *keywords[_HW_LAST] = +{ + keyword_gpr, keyword_usr, keyword_dxr, keyword_sr, keyword_fsr, + keyword_fdr, keyword_cp, keyword_cpr, keyword_abdim, keyword_abm, + keyword_dtiton, keyword_dtitoff, keyword_dpref_st, + keyword_cctl_st0, keyword_cctl_st1, keyword_cctl_st2, + keyword_cctl_st3, keyword_cctl_st4, keyword_cctl_st5, + keyword_cctl_lv, keyword_tlbop_st, keyword_standby_st, + keyword_msync_st, + keyword_im5_i, keyword_im5_m, + keyword_accumulator, keyword_aridx, keyword_aridx2, keyword_aridxi +}; /* Hash table for syntax lex. */ static htab_t field_htab; @@ -1085,7 +1388,6 @@ htab_hash_eq (const void *p, const void *q) return strcmp (name, h->name) == 0; } - /* Build a hash table for array BASE. Each element is in size of SIZE, and it's first element is a pointer to the key of string. @@ -1157,9 +1459,15 @@ build_opcode_syntax (struct nds32_opcode *opc) switch (*str) { - case '%': *plex = SYN_INPUT; break; - case '=': *plex = SYN_OUTPUT; break; - case '&': *plex = SYN_INPUT | SYN_OUTPUT; break; + case '%': + *plex = SYN_INPUT; + break; + case '=': + *plex = SYN_OUTPUT; + break; + case '&': + *plex = SYN_INPUT | SYN_OUTPUT; + break; case '{': *plex++ = SYN_LOPT; opt++; @@ -1201,9 +1509,6 @@ build_opcode_syntax (struct nds32_opcode *opc) *plex = 0; opc->variant = opt; return; - - fprintf (stderr, "Unknown lex in assembly syntax, %s.\n", str); - abort (); } /* Initialize the assembler. It must be called before assembling. */ @@ -1213,16 +1518,6 @@ nds32_asm_init (nds32_asm_desc_t *pdesc, int flags) { int i; hashval_t hash; - const keyword_t *keywords[_HW_LAST] = - { - keyword_gpr, keyword_usr, keyword_dxr, keyword_sr, keyword_fsr, - keyword_fdr, keyword_cp, keyword_cpr, keyword_abdim, keyword_abm, - keyword_dtiton, keyword_dtitoff, keyword_dpref_st, - keyword_cctl_st0, keyword_cctl_st1, keyword_cctl_st2, - keyword_cctl_st3, keyword_cctl_st4, keyword_cctl_st5, - keyword_cctl_lv, keyword_tlbop_st, keyword_standby_st, - keyword_msync_st, - }; pdesc->flags = flags; pdesc->mach = flags & NASM_OPEN_ARCH_MASK; @@ -1244,30 +1539,32 @@ nds32_asm_init (nds32_asm_desc_t *pdesc, int flags) struct nds32_opcode *opc; opc = &nds32_opcodes[i]; - - hash = htab_hash_string (opc->opcode); - slot = (struct nds32_opcode **) - htab_find_slot_with_hash (opcode_htab, opc->opcode, hash, INSERT); + if ((opc->opcode != NULL) && (opc->instruction != NULL)) + { + hash = htab_hash_string (opc->opcode); + slot = (struct nds32_opcode **) + htab_find_slot_with_hash (opcode_htab, opc->opcode, hash, INSERT); #define NDS32_PREINIT_SYNTAX #if defined (NDS32_PREINIT_SYNTAX) - /* Initial SYNTAX when build opcode table, so bug in syntax can be - found when initialized rather than used. */ - build_opcode_syntax (opc); + /* Initial SYNTAX when build opcode table, so bug in syntax can be + found when initialized rather than used. */ + build_opcode_syntax (opc); #endif - if (*slot == NULL) - { - /* This is the new one. */ - *slot = opc; - } - else - { - /* Already exists. Append to the list. */ - opc = *slot; - while (opc->next) - opc = opc->next; - opc->next = &nds32_opcodes[i]; + if (*slot == NULL) + { + /* This is the new one. */ + *slot = opc; + } + else + { + /* Already exists. Append to the list. */ + opc = *slot; + while (opc->next) + opc = opc->next; + opc->next = &nds32_opcodes[i]; + } } } } @@ -1288,6 +1585,35 @@ parse_to_delimiter (char *str, char odstr[MAX_KEYWORD_LEN]) return str; } +/* Parse the operand of lmw/smw/lmwa/smwa. */ + +static int +parse_re (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn, char **pstr, int64_t *value) +{ + char *end = *pstr; + char odstr[MAX_KEYWORD_LEN]; + keyword_t *k; + hashval_t hash; + + if (*end == '$') + end++; + end = parse_to_delimiter (end, odstr); + + hash = htab_hash_string (odstr); + k = htab_find_with_hash (hw_ktabs[HW_GPR], odstr, hash); + + if (k == NULL) + return NASM_ERR_OPERAND; + + if (__GF (pinsn->insn, 20, 5) > (unsigned int) k->value) + return NASM_ERR_OPERAND; + + *value = k->value; + *pstr = end; + return NASM_R_CONST; +} + /* Parse the operand of push25/pop25. */ static int @@ -1335,7 +1661,7 @@ parse_fe5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn, r = pdesc->parse_operand (pdesc, pinsn, pstr, value); if (r != NASM_R_CONST) - return r; + return NASM_ERR_OPERAND; /* 128 == 32 << 2. Leave the shift to parse_opreand, so it can check whether it is a multiple of 4. */ @@ -1353,12 +1679,262 @@ parse_pi5 (struct nds32_asm_desc *pdesc, struct nds32_asm_insn *pinsn, r = pdesc->parse_operand (pdesc, pinsn, pstr, value); if (r != NASM_R_CONST) - return r; + return NASM_ERR_OPERAND; *value -= 16; return r; } +static int aext_a30b20 = 0; +static int aext_rte = 0; +static int aext_im5_ip = 0; +static int aext_im6_ip = 0; +/* Parse the operand of audio ext. */ +static int +parse_aext_reg (char **pstr, int *value, int hw_res) +{ + char *end = *pstr; + char odstr[MAX_KEYWORD_LEN]; + keyword_t *k; + hashval_t hash; + + if (*end == '$') + end++; + end = parse_to_delimiter (end, odstr); + + hash = htab_hash_string (odstr); + k = htab_find_with_hash (hw_ktabs[hw_res], odstr, hash); + + if (k == NULL) + return NASM_ERR_OPERAND; + + *value = k->value; + *pstr = end; + return NASM_R_CONST; +} + +static int +parse_a30b20 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_GPR); + + if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)) + return NASM_ERR_OPERAND; + + *value = rt_value; + aext_a30b20 = rt_value; + return NASM_R_CONST; +} + +static int +parse_rt21 (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret, tmp_value, tmp1, tmp2; + + ret = parse_aext_reg (pstr, &rt_value, HW_GPR); + + if ((ret == NASM_ERR_OPERAND) || (rt_value > 15)) + return NASM_ERR_OPERAND; + tmp1 = (aext_a30b20 & 0x08); + tmp2 = (rt_value & 0x08); + if (tmp1 != tmp2) + return NASM_ERR_OPERAND; + + /* Rt=CONCAT(c, t21, t0), t21:bit11-10, t0:bit5. */ + tmp_value = (rt_value & 0x06) << 4; + tmp_value |= (rt_value & 0x01); + *value = tmp_value; + return NASM_R_CONST; +} + +static int +parse_rte_start (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret, tmp1, tmp2; + + ret = parse_aext_reg (pstr, &rt_value, HW_GPR); + + if ((ret == NASM_ERR_OPERAND) || (rt_value > 15) + || (rt_value & 0x01)) + return NASM_ERR_OPERAND; + tmp1 = (aext_a30b20 & 0x08); + tmp2 = (rt_value & 0x08); + if (tmp1 != tmp2) + return NASM_ERR_OPERAND; + + aext_rte = rt_value; + /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */ + rt_value = (rt_value & 0x06) << 4; + *value = rt_value; + return NASM_R_CONST; +} + +static int +parse_rte_end (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret, tmp1, tmp2; + + ret = parse_aext_reg (pstr, &rt_value, HW_GPR); + if ((ret == NASM_ERR_OPERAND) || (rt_value > 15) + || ((rt_value & 0x01) == 0) + || (rt_value != (aext_rte + 1))) + return NASM_ERR_OPERAND; + tmp1 = (aext_a30b20 & 0x08); + tmp2 = (rt_value & 0x08); + if (tmp1 != tmp2) + return NASM_ERR_OPERAND; + /* Rt=CONCAT(c, t21, 0), t21:bit11-10. */ + rt_value = (rt_value & 0x06) << 4; + *value = rt_value; + return NASM_R_CONST; +} + +static int +parse_rte69_start (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_GPR); + if ((ret == NASM_ERR_OPERAND) + || (rt_value & 0x01)) + return NASM_ERR_OPERAND; + aext_rte = rt_value; + rt_value = (rt_value >> 1); + *value = rt_value; + return NASM_R_CONST; +} + +static int +parse_rte69_end (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_GPR); + if ((ret == NASM_ERR_OPERAND) + || ((rt_value & 0x01) == 0) + || (rt_value != (aext_rte + 1))) + return NASM_ERR_OPERAND; + aext_rte = rt_value; + rt_value = (rt_value >> 1); + *value = rt_value; + return NASM_R_CONST; +} + +static int +parse_im5_ip (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret, new_value; + + ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I); + if (ret == NASM_ERR_OPERAND) + return NASM_ERR_OPERAND; + /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */ + new_value = (rt_value & 0x04) << 2; + new_value |= (rt_value & 0x03); + *value = new_value; + aext_im5_ip = new_value; + return NASM_R_CONST; +} + +static int +parse_im5_mr (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret, new_value, tmp1, tmp2; + + ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M); + if (ret == NASM_ERR_OPERAND) + return NASM_ERR_OPERAND; + /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */ + new_value = (rt_value & 0x07) << 2; + tmp1 = (aext_im5_ip & 0x10); + tmp2 = (new_value & 0x10); + if (tmp1 != tmp2) + return NASM_ERR_OPERAND; + *value = new_value; + return NASM_R_CONST; +} + +static int +parse_im6_ip (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I); + if ((ret == NASM_ERR_OPERAND) || (rt_value > 3)) + return NASM_ERR_OPERAND; + /* p = 0.bit[1:0]. */ + aext_im6_ip = rt_value; + *value = aext_im6_ip; + return NASM_R_CONST; +} + +static int +parse_im6_iq (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_I); + if ((ret == NASM_ERR_OPERAND) || (rt_value < 4)) + return NASM_ERR_OPERAND; + /* q = 1.bit[1:0]. */ + if ((rt_value & 0x03) != aext_im6_ip) + return NASM_ERR_OPERAND; + *value = aext_im6_ip; + return NASM_R_CONST; +} + +static int +parse_im6_mr (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M); + if ((ret == NASM_ERR_OPERAND) || (rt_value > 3)) + return NASM_ERR_OPERAND; + /* r = 0.bit[3:2]. */ + *value = (rt_value & 0x03); + return NASM_R_CONST; +} + +static int +parse_im6_ms (struct nds32_asm_desc *pdesc ATTRIBUTE_UNUSED, + struct nds32_asm_insn *pinsn ATTRIBUTE_UNUSED, + char **pstr, int64_t *value) +{ + int rt_value, ret; + + ret = parse_aext_reg (pstr, &rt_value, HW_AEXT_IM_M); + if ((ret == NASM_ERR_OPERAND) || (rt_value < 4)) + return NASM_ERR_OPERAND; + /* s = 1.bit[5:4]. */ + *value = (rt_value & 0x03); + return NASM_R_CONST; +} + /* Generic operand parse base on the information provided by the field. */ static int @@ -1379,6 +1955,11 @@ parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, if (fld->parse) { r = fld->parse (pdesc, pinsn, &end, &value); + if (r == NASM_ERR_OPERAND) + { + pdesc->result = NASM_ERR_OPERAND; + return 0; + } goto done; } @@ -1437,7 +2018,7 @@ parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, } else if (strncasecmp (end, "lo20(", 5) == 0) { - /* e.g., movi */ + /* e.g., movi. */ modifier |= NASM_ATTR_LO20; end += 5; } @@ -1469,7 +2050,7 @@ parse_operand (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, break; default: fprintf (stderr, "Internal error: Don't know how to handle " - "parsing results.\n"); + "parsing results.\n"); abort (); } } @@ -1488,7 +2069,7 @@ done: } /* Check the range of signed or unsigned result. */ - if (fld->hw_res != HW_INT && (value >> (fld->bitsize + fld->shift))) + if (fld->hw_res != HW_INT && ((int32_t) value >> (fld->bitsize + fld->shift))) { pdesc->result = NASM_ERR_OUT_OF_RANGE; return 0; @@ -1509,7 +2090,8 @@ done: } } - pinsn->insn |= (((value >> fld->shift) & __MASK (fld->bitsize)) << fld->bitpos); + pinsn->insn |= + (((value >> fld->shift) & __MASK (fld->bitsize)) << fld->bitpos); *str = end; return 1; } @@ -1530,15 +2112,15 @@ parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, For example, there are 2 optional operands in this syntax, - "a{,b}{,c}" + "a{,b}{,c}" we can try it 4 times (i.e., 1 << 2) - 0 (b00): "a,b,c" - 1 (b01): "a,c" - 2 (b10): "a,b" - 3 (b11): "a" - */ + 0 (b00): "a,b,c" + 1 (b01): "a,c" + 2 (b10): "a,b" + 3 (b11): "a" + */ /* The outer do-while loop is used to try each possible optional operand combination, and VARIANT is the bit mask. The inner loop @@ -1562,8 +2144,18 @@ parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, if (IS_LEX_CHAR (*plex)) { /* If it's a plain char, just compare it. */ - if (LEX_CHAR (*plex) != *p) + if (LEX_CHAR (*plex) != TOLOWER (*p)) { + if (LEX_CHAR (*plex) == '+' && TOLOWER (*p) == '-') + { + /* We don't define minus format for some signed + immediate case, so ignoring '+' here to parse + negative value eazily. Besides, the minus format + can not support for instruction with relocation. + Ex: lwi $r0, [$r0 + imm] */ + plex++; + continue; + } pdesc->result = NASM_ERR_SYNTAX; goto reject; } @@ -1581,7 +2173,7 @@ parse_insn (nds32_asm_desc_t *pdesc, nds32_asm_insn_t *pinsn, } else if (*plex & SYN_ROPT) { - /* ignore */ + /* ignore. */ } else { diff --git a/opcodes/nds32-asm.h b/opcodes/nds32-asm.h index 4f4cf1b..4b6828d 100644 --- a/opcodes/nds32-asm.h +++ b/opcodes/nds32-asm.h @@ -17,7 +17,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA.*/ + 02110-1301, USA. */ #ifndef NDS32_ASM_H @@ -70,7 +70,7 @@ enum NASM_ATTR_FPU_FMA = 0x0080000, NASM_ATTR_DXREG = 0x0100000, NASM_ATTR_BRANCH = 0x0200000, - NASM_ATTR_RELAXABLE = 0x0400000, + NASM_ATTR_SATURATION_EXT = 0x0400000, NASM_ATTR_PCREL = 0x0800000, NASM_ATTR_GPREL = 0x1000000, @@ -83,6 +83,81 @@ enum NASM_ATTR_RDREG = 0x000100 }; +enum +{ + /* This is a field (operand) of just a separator char. */ + SYN_FIELD = 0x100, + + /* This operand is used for input or output. (define or use) */ + SYN_INPUT = 0x1000, + SYN_OUTPUT = 0x2000, + SYN_LOPT = 0x4000, + SYN_ROPT = 0x8000, + + /* Hardware resources. */ + HW_GPR = 0, + HW_USR, + HW_DXR, + HW_SR, + HW_FSR, + HW_FDR, + HW_CP, /* Co-processor ID. */ + HW_CPR, /* Co-processor registers. */ + HW_ABDIM, /* [ab][di]m? flag for LSMWA?. */ + HW_ABM, /* [ab]m? flag for LSMWZB. */ + HW_DTITON, + HW_DTITOFF, + HW_DPREF_ST, + HW_CCTL_ST0, + HW_CCTL_ST1, + HW_CCTL_ST2, + HW_CCTL_ST3, + HW_CCTL_ST4, + HW_CCTL_ST5, + HW_CCTL_LV, + HW_TLBOP_ST, + HW_STANDBY_ST, + HW_MSYNC_ST, + HW_AEXT_IM_I, + HW_AEXT_IM_M, + HW_AEXT_ACC, + HW_AEXT_ARIDX, + HW_AEXT_ARIDX2, + HW_AEXT_ARIDXI, + _HW_LAST, + /* TODO: Maybe we should add a new type to distinguish address and + const int. Only the former allows symbols and relocations. */ + HW_INT, + HW_UINT +}; + +/* for audio-extension. */ +enum +{ + N32_AEXT_AMADD = 0, + N32_AEXT_AMSUB, + N32_AEXT_AMULT, + N32_AEXT_AMFAR, + N32_AEXT_AMADDS, + N32_AEXT_AMSUBS, + N32_AEXT_AMULTS, + N32_AEXT_AMNEGS, + N32_AEXT_AADDL, + N32_AEXT_AMTARI, + N32_AEXT_AMAWBS = 0x0c, + N32_AEXT_AMAWTS, + N32_AEXT_AMWBS, + N32_AEXT_AMWTS, + N32_AEXT_AMABBS, + N32_AEXT_AMABTS, + N32_AEXT_AMATBS, + N32_AEXT_AMATTS, + N32_AEXT_AMBBS, + N32_AEXT_AMBTS, + N32_AEXT_AMTBS, + N32_AEXT_AMTTS +}; + /* Macro for instruction attribute. */ #define ATTR(attr) NASM_ATTR_ ## attr #define ATTR_NONE 0 @@ -131,6 +206,7 @@ typedef struct nds32_opcode int variant; /* Next form of the same mnemonic. */ struct nds32_opcode *next; + /* TODO: Extra constrains and verification. For example, `mov55 $sp, $sp' is not allowed in v3. */ } opcode_t; @@ -187,4 +263,35 @@ typedef struct nds32_field extern void nds32_assemble (nds32_asm_desc_t *, nds32_asm_insn_t *, char *); extern void nds32_asm_init (nds32_asm_desc_t *, int); +#define OP6(op6) (N32_OP6_ ## op6 << 25) + +#define LSMW(sub) (OP6 (LSMW) | N32_LSMW_ ## sub) +#define JREG(sub) (OP6 (JREG) | N32_JREG_ ## sub) +#define JREG_RET (1 << 5) +#define JREG_IFC (1 << 6) +#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16)) +#define SIMD(sub) (OP6 (SIMD) | N32_SIMD_ ## sub) +#define ALU1(sub) (OP6 (ALU1) | N32_ALU1_ ## sub) +#define ALU2(sub) (OP6 (ALU2) | N32_ALU2_ ## sub) +#define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub) +#define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub) +#define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12)) +#define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6)) +#define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \ + | (N32_FPU_FS1_F2OP_ ## sub << 10)) +#define FS2(sub) (OP6 (COP) | N32_FPU_FS2 | (N32_FPU_FS2_ ## sub << 6)) +#define FD1(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_ ## sub << 6)) +#define FD1_F2OP(sub) (OP6 (COP) | N32_FPU_FD1 | (N32_FPU_FD1_F2OP << 6) \ + | (N32_FPU_FD1_F2OP_ ## sub << 10)) +#define FD2(sub) (OP6 (COP) | N32_FPU_FD2 | (N32_FPU_FD2_ ## sub << 6)) +#define MFCP(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_ ## sub << 6)) +#define MFCP_XR(sub) (OP6 (COP) | N32_FPU_MFCP | (N32_FPU_MFCP_XR << 6) \ + | (N32_FPU_MFCP_XR_ ## sub << 10)) +#define MTCP(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_ ## sub << 6)) +#define MTCP_XR(sub) (OP6 (COP) | N32_FPU_MTCP | (N32_FPU_MTCP_XR << 6) \ + | (N32_FPU_MTCP_XR_ ## sub << 10)) +#define FPU_MEM(sub) (OP6 (COP) | N32_FPU_ ## sub) +#define FPU_MEMBI(sub) (OP6 (COP) | N32_FPU_ ## sub | 0x1 << 7) +#define AUDIO(sub) (OP6 (AEXT) | (N32_AEXT_ ## sub << 20)) + #endif diff --git a/opcodes/nds32-dis.c b/opcodes/nds32-dis.c index e8308d5..7274d19 100644 --- a/opcodes/nds32-dis.c +++ b/opcodes/nds32-dis.c @@ -17,8 +17,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA.*/ - + 02110-1301, USA. */ #include "sysdep.h" #include <stdio.h> @@ -29,1227 +28,947 @@ #include "libiberty.h" #include "opintl.h" #include "bfd_stdint.h" +#include "hashtab.h" +#include "nds32-asm.h" +#include "opcode/nds32.h" -#define __MF(v, off, bs) ((v & ((1 << (bs)) - 1)) << (off)) -#define __GF(v, off, bs) ((v >> (off)) & ((1 << (bs)) - 1)) -#define __PF(v, off, bs, val) do { v = __put_field (v, off, bs, val); } while (0) -/* #define __SEXT(v, bs) ((v ^ (1 << (bs - 1))) - (1 << (bs - 1))) */ -#define __SEXT(v, bs) (((v & ((1 << bs) - 1)) ^ (1 << (bs - 1))) - (1 << (bs - 1))) -#define __BIT(n) (1 << n) - -/* Get fields */ -#define OP6(insn) ((insn >> 25) & 0x3F) -#define RT5(insn) ((insn >> 20) & 0x1F) -#define RA5(insn) ((insn >> 15) & 0x1F) -#define RB5(insn) ((insn >> 10) & 0x1F) -#define RD5(insn) ((insn >> 5) & 0x1F) -#define SUB5(insn) ((insn >> 0) & 0x1F) -#define SUB10(insn) ((insn >> 0) & 0x3FF) -#define IMMU(insn, bs) (insn & ((1 << bs) - 1)) -#define IMMS(insn, bs) __SEXT ((insn & ((1 << bs) - 1)), bs) -#define IMM1U(insn) IMMU ((insn >> 10), 5) -#define IMM1S(insn) IMMS ((insn >> 10), 5) -#define IMM2U(insn) IMMU ((insn >> 5), 5) -#define IMM2S(insn) IMMS ((insn >> 5), 5) +/* Get fields macro define. */ +#define MASK_OP(insn, mask) ((insn) & (0x3f << 25 | (mask))) /* Default text to print if an instruction isn't recognized. */ #define UNKNOWN_INSN_MSG _("*unknown*") - -static const char *mnemonic_op6[] = -{ - "lbi", "lhi", "lwi", "ldi", "lbi.bi", "lhi.bi", "lwi.bi", "ldi.bi", - "sbi", "shi", "swi", "sdi", "sbi.bi", "shi.bi", "swi.bi", "sdi.bi", - "lbsi", "lhsi", "lwsi", "dprefi", "lbsi.bi", "lhsi.bi", "lwsi.bi", "lbgp", - "lwc", "swc", "ldc", "sdc", "mem", "lsmw", "hwgp", "sbgp", - "alu1", "alu2", "movi", "sethi", "ji", "jreg", "br1", "br2", - "addi", "subri", "andi", "xori", "ori", "br3", "slti", "sltsi", - "aext", "cext", "misc", "bitci", "op_64", "cop" -}; - -static const char *mnemonic_mem[] = -{ - "lb", "lh", "lw", "ld", "lb.bi", "lh.bi", "lw.bi", "ld.bi", - "sb", "sh", "sw", "sd", "sb.bi", "sh.bi", "sw.bi", "sd.bi", - "lbs", "lhs", "lws", "dpref", "lbs.bi", "lhs.bi", "lws.bi", "27", - "llw", "scw", "32", "33", "34", "35", "36", "37", - "lbup", "41", "lwup", "43", "44", "45", "46", "47", - "sbup", "51", "swup" -}; - -static const char *mnemonic_alu1[] = -{ - "add", "sub", "and", "xor", "or", "nor", "slt", "slts", - "slli", "srli", "srai", "rotri", "sll", "srl", "sra", "rotr", - "seb", "seh", "bitc", "zeh", "wsbh", "or_srli", "divsr", "divr", - "sva", "svs", "cmovz", "cmovn", "add_srli", "sub_srli", "and_srli", "xor_srli" -}; - - -static const char *mnemonic_alu20[] = -{ - "max", "min", "ave", "abs", "clips", "clip", "clo", "clz", - "bset", "bclr", "btgl", "btst", "bse", "bsp", "ffb", "ffmism", - "add.sc", "sub.sc", "add.wc", "sub.wc", "24", "25", "26", "ffzmism", - "qadd", "qsub", "32", "33", "34", "35", "36", "37", - "mfusr", "mtusr", "42", "43", "mul", "45", "46", "47", - "mults64", "mult64", "madds64", "madd64", "msubs64", "msub64", "divs", "div", - "60", "mult32", "62", "madd32", "64", "msub32", "65", "66", - "dmadd", "dmaddc", "dmsub", "dmsubc", "rmfhi", "qmflo" -}; - -static const char *mnemonic_alu21[] = +#define NDS32_PARSE_INSN16 0x01 +#define NDS32_PARSE_INSN32 0x02 +#define NDS32_PARSE_EX9IT 0x04 +#define NDS32_PARSE_EX9TAB 0x08 + +extern struct nds32_opcode nds32_opcodes[]; +extern const field_t operand_fields[]; +extern const keyword_t *keywords[]; +extern const keyword_t keyword_gpr[]; +static void print_insn16 (bfd_vma pc, disassemble_info *info, + uint32_t insn, uint32_t parse_mode); +static void print_insn32 (bfd_vma pc, disassemble_info *info, uint32_t insn, + uint32_t parse_mode); +static uint32_t nds32_mask_opcode (uint32_t); +static void nds32_special_opcode (uint32_t, struct nds32_opcode **); + +/* define in objdump.c. */ +struct objdump_disasm_info { - "00", "01", "02", "03", "04", "05", "06", "07", - "10", "11", "12", "13", "14", "15", "ffbi", "flmism", - "20", "21", "22", "23", "24", "25", "26", "27", - "30", "31", "32", "33", "34", "35", "36", "37", - "40", "41", "42", "43", "44", "45", "46", "47", - "mulsr64", "mulr64", "52", "53", "54", "55", "56", "57", - "60", "61", "62", "maddr32", "64", "msubr32", "66", "67", - "70", "71", "72", "73", "74", "75", "76", "77" + bfd * abfd; + asection * sec; + bfd_boolean require_sec; + arelent ** dynrelbuf; + long dynrelcount; + disassembler_ftype disassemble_fn; + arelent * reloc; }; -static const char *mnemonic_br2[] = -{ - "ifcall", "01", "beqz", "bnez", "bgez", "bltz", "bgtz", "blez", - "10", "11", "12", "13", "bgezal", "bltzal" -}; - -static const char *mnemonic_misc[] = -{ - "standby", "cctl", "mfsr", "mtsr", "iret", "trap", "teqz", "tnez", - "dsb", "isb", "break", "syscall", "msync", "isync", "tlbop" -}; - -static const char *mnemonic_hwgp[] = -{ - "lhi.gp", "lhi.gp", "lhsi.gp", "lhsi.gp", - "shi.gp", "shi.gp", "lwi.gp", "swi.gp" -}; +/* file_ptr ex9_filepos=NULL;. */ +bfd_byte *ex9_data = NULL; +int ex9_ready = 0, ex9_base_offset = 0; -static const char *keyword_dpref[] = -{ - "SRD", "MRD", "SWR", "MWR", "PTE", "CLWR", "6", "7", - "8", "9", "10", "11", "12", "13", "14", "15" -}; +/* Hash function for disassemble. */ -static const char *mnemonic_alu[] = -{ - "fadds", "fsubs", "fcpynss", "fcpyss", "fmadds", - "fmsubs", "fcmovns", "fcmovzs", "fnmadds", "fnmsubs", - "10", "11", "fmuls", "fdivs", "faddd", - "fsubd", "fcpynsd", "fcpysd", "fmaddd", "fmsubd", - "fcmovnd", "fcmovzd", "fnmaddd", "fnmsubd", "24", - "25", "fmuld", "fdivd" -}; +static htab_t opcode_htab; -static const char *mnemonic_fpu_2op[] = +static void +nds32_ex9_info (bfd_vma pc ATTRIBUTE_UNUSED, + disassemble_info *info, uint32_t ex9_index) { - "fs2d", "fsqrts", "2", "3", "4", "fabss", "6", "7", - "fui2s", "9", "10", "11", "fsi2s", "13", "14", "15", - "fs2ui", "17", "18", "19", "fs2ui.z", "21", "22", "23", - "fs2si", "25", "26", "27", "fs2si.z", "fd2s", "fsqrtd", "31", - "32", "33", "fabsd", "35", "36", "fui2d", "38", "39", - "40", "fsi2d", "42", "43", "44", "fd2ui", "46", "47", - "48", "fd2ui.z", "50", "51", "52", "fd2si", "54", "55", - "56", "fd2si.z" -}; + uint32_t insn; + static asymbol *itb = NULL; + bfd_byte buffer[4]; + long unsigned int isec_vma; -static const char *mnemonic_fs2_cmp[] = -{ - "fcmpeqs", "fcmpeqs.e", "fcmplts", "fcmplts.e", - "fcmples", "fcmples.e", "fcmpuns", "fcmpuns.e" -}; + /* Lookup itb symbol. */ + if (!itb) + { + int i; -static const char *mnemonic_fd2_cmp[] = -{ - "fcmpeqd", "fcmpeqd.e", "fcmpltd", "fcmpltd.e", - "fcmpled", "fcmpled.e", "fcmpund", "fcmpund.e" -}; + for (i = 0; i < info->symtab_size; i++) + if (bfd_asymbol_name (info->symtab[i]) + && (strcmp (bfd_asymbol_name (info->symtab[i]), "$_ITB_BASE_") == 0 + || strcmp (bfd_asymbol_name (info->symtab[i]), + "_ITB_BASE_") == 0)) + { + itb = info->symtab[i]; + break; + } -/* Register name table. */ -/* General purpose register. */ + /* Lookup it only once, in case _ITB_BASE_ doesn't exist at all. */ + if (itb == NULL) + itb = (void *) -1; + } -static const char *gpr_map[] = -{ - "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", - "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$r15", - "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", - "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp" -}; + if (itb == (void *) -1) + return; + + isec_vma = itb->section->vma; + isec_vma = itb->section->vma - bfd_asymbol_value (itb); + if (!itb->section || !itb->section->owner) + return; + bfd_get_section_contents (itb->section->owner, itb->section, buffer, + ex9_index * 4 - isec_vma, 4); + insn = bfd_getb32 (buffer); + /* 16-bit instructions in ex9 table. */ + if (insn & 0x80000000) + print_insn16 (pc, info, (insn & 0x0000FFFF), + NDS32_PARSE_INSN16 | NDS32_PARSE_EX9IT); + /* 32-bit instructions in ex9 table. */ + else + print_insn32 (pc, info, insn, NDS32_PARSE_INSN32 | NDS32_PARSE_EX9IT); +} -/* User special register. */ +/* Find the value map register name. */ -static const char *usr_map[][32] = +static keyword_t * +nds32_find_reg_keyword (keyword_t *reg, int value) { - { - "d0.lo", "d0.hi", "d1.lo", "d1.hi", "4", "5", "6", "7", - "8", "9", "10", "11", "12", "13", "14", "15", - "16", "17", "18", "19", "20", "21", "22", "23", - "24", "25", "26", "27", "28", "29", "30", "pc" - }, - { - "DMA_CFG", "DMA_GCSW", "DMA_CHNSEL", "DMA_ACT", "DMA_SETUP", - "DMA_ISADDR", "DMA_ESADDR", "DMA_TCNT", "DMA_STATUS", "DMA_2DSET", - "10", "11", "12", "13", "14", - "15", "16", "17", "18", "19", - "20", "21", "22", "23", "24", - "DMA_2DSCTL" - }, - { - "PFMC0", "PFMC1", "PFMC2", "3", "PFM_CTL" - } -}; + if (!reg) + return NULL; -/* System register. */ -/* Major Minor Extension. */ -static const char *sr_map[8][16][8] = -{ - { - {"CPU_VER", "CORE_ID"}, - {"ICM_CFG"}, - {"DCM_CFG"}, - {"MMU_CFG"}, - {"MSC_CFG"} - }, - { - {"PSW", "IPSW", "P_IPSW"}, - {"0", "IVB", "INT_CTRL"}, - {"0", "EVA", "P_EVA"}, - {"0", "ITYPE", "P_ITYPE"}, - {"0", "MERR"}, - {"0", "IPC", "P_IPC", "OIPC"}, - {"0", "1", "P_P0"}, - {"0", "1", "P_P1"}, - {"INT_MASK", "INT_MASK2"}, - {"INT_PEND", "INT_PEND2", "2", "3", "INT_TRIGGER"}, - {"SP_USR", "SP_PRIV"}, - {"INT_PRI", "INT_PRI2"} - }, - { - {"MMU_CTL"}, - {"L1_PPTB"}, - {"TLB_VPN"}, - {"TLB_DATA"}, - {"TLB_MISC"}, - {"VLPT_IDX"}, - {"ILMB"}, - {"DLMB"}, - {"CACHE_CTL"}, - {"HSMP_SADDR", "HSMP_EADDR"}, - {"0"}, - {"0"}, - {"0"}, - {"0"}, - {"0"}, - {"SDZ_CTL", "MISC_CTL"} - }, - { - {"BPC0", "BPC1", "BPC2", "BPC3", "BPC4", "BPC5", "BPC6", "BPC7"}, - {"BPA0", "BPA1", "BPA2", "BPA3", "BPA4", "BPA5", "BPA6", "BPA7"}, - {"BPAM0", "BPAM1", "BPAM2", "BPAM3", "BPAM4", "BPAM5", "BPAM6", "BPAM7"}, - {"BPV0", "BPV1", "BPV2", "BPV3", "BPV4", "BPV5", "BPV6", "BPV7"}, - {"BPCID0", "BPCID1", "BPCID2", "BPCID3", "BPCID4", "BPCID5", "BPCID6", "BPCID7"}, - {"EDM_CFG"}, - {"EDMSW"}, - {"EDM_CTL"}, - {"EDM_DTR"}, - {"BPMTC"}, - {"DIMBR"}, - {"EDM_PROBE"}, - {"0"}, - {"0"}, - {"TECR0", "TECR1"} - }, - { - {"PFMC0", "PFMC1", "PFMC2"}, - {"PFM_CTL"}, - {"0"}, - {"0"}, - {"PRUSR_ACC_CTL"}, - {"FUCOP_CTL"} - }, - { - {"DMA_CFG"}, - {"DMA_GCSW"}, - {"DMA_CHNSEL"}, - {"DMA_ACT"}, - {"DMA_SETUP"}, - {"DMA_ISADDR"}, - {"DMA_ESADDR"}, - {"DMA_TCNT"}, - {"DMA_STATUS"}, - {"DMA_2DSET", "DMA_2DSCTL"} - } -}; + while (reg->name != NULL && reg->value != value) + { + reg++; + } + if (reg->name == NULL) + return NULL; + return reg; +} static void -print_insn16 (bfd_vma pc, disassemble_info *info, uint32_t insn) +nds32_parse_audio_ext (const field_t *pfd, + disassemble_info *info, uint32_t insn) { - static char r4map[] = - { - 0, 1, 2, 3, 4, 5, 6, 7, - 8, 9, 10, 11, 16, 17, 18, 19 - }; - const int rt5 = __GF (insn, 5, 5); - const int ra5 = __GF (insn, 0, 5); - const int rt4 = r4map[__GF (insn, 5, 4)]; - const int imm5u = IMMU (insn, 5); - const int imm9u = IMMU (insn, 9); - const int rt3 = __GF (insn, 6, 3); - const int ra3 = __GF (insn, 3, 3); - const int rb3 = __GF (insn, 0, 3); - const int rt38 = __GF (insn, 8, 3); - const int imm3u = rb3; fprintf_ftype func = info->fprintf_func; void *stream = info->stream; + keyword_t *psys_reg; + int int_value, new_value; - static const char *mnemonic_96[] = - { - "0x1", "0x1", "0x2", "0x3", - "add45", "sub45", "addi45", "subi45", - "srai45", "srli45", "slli333", "0xb", - "add333", "sub333", "addi333", "subi333", - "lwi333", "lwi333.bi", "lhi333", "lbi333", - "swi333", "swi333.bi", "shi333", "sbi333", - "addri36.sp", "lwi45.fe", "lwi450", "swi450", - "0x1c", "0x1d", "0x1e", "0x1f", - "0x20", "0x21", "0x22", "0x23", - "0x24", "0x25", "0x26", "0x27", - "0x28", "0x29", "0x2a", "0x2b", - "0x2c", "0x2d", "0x2e", "0x2f", - "slts45", "slt45", "sltsi45", "slti45", - "0x34", "0x35", "0x36", "0x37", - "0x38", "0x39", "0x3a", "0x3b", - "ifcall9", "movpi45" - }; - - static const char *mnemonic_misc33[] = - { - "misc33_0", "misc33_1", "neg33", "not33", "mul33", "xor33", "and33", "or33", - }; - - static const char *mnemonic_0xb[] = - { - "zeb33", "zeh33", "seb33", "seh33", "xlsb33", "x11b33", "bmski33", "fexti33" - }; - - static const char *mnemonic_bnes38[] = - { - "jr5", "jral5", "ex9.it", "?", "ret5", "add5.pc" - }; - - switch (__GF (insn, 7, 8)) + if (pfd->hw_res == HW_INT || pfd->hw_res == HW_UINT) { - case 0xf8: /* push25 */ - case 0xf9: /* pop25 */ - { - uint32_t res[] = { 6, 8, 10, 14 }; - uint32_t re = res[__GF (insn, 5, 2)]; + if (pfd->hw_res == HW_INT) + int_value = + N32_IMMS ((insn >> pfd->bitpos), pfd->bitsize) << pfd->shift; + else + int_value = __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; - func (stream, "%s\t%s, %d", (insn & __BIT (7)) ? "pop25" : "push25", - gpr_map[re], imm5u << 3); - } + if (int_value < 0) + func (stream, "#%d", int_value); + else + func (stream, "#0x%x", int_value); return; } + int_value = + __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; + new_value = int_value; + psys_reg = (keyword_t*) keywords[pfd->hw_res]; - if (__GF (insn, 8, 7) == 0x7d) /* movd44 */ + /* p = bit[4].bit[1:0], r = bit[4].bit[3:2]. */ + if (strcmp (pfd->name, "im5_i") == 0) { - int rt5e = __GF (insn, 4, 4) << 1; - int ra5e = IMMU (insn, 4) << 1; - - func (stream, "movd44\t%s, %d", gpr_map[rt5e], ra5e); - return; + new_value = int_value & 0x03; + new_value |= ((int_value & 0x10) >> 2); } - - switch (__GF (insn, 9, 6)) + else if (strcmp (pfd->name, "im5_m") == 0) { - case 0x4: /* add45 */ - case 0x5: /* sub45 */ - case 0x30: /* slts45 */ - case 0x31: /* slt45 */ - func (stream, "%s\t%s, %s", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt4], gpr_map[ra5]); - return; - case 0x6: /* addi45 */ - case 0x7: /* subi45 */ - case 0x8: /* srai45 */ - case 0x9: /* srli45 */ - case 0x32: /* sltsi45 */ - case 0x33: /* slti45 */ - func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt4], ra5); - return; - case 0xc: /* add333 */ - case 0xd: /* sub333 */ - func (stream, "%s\t%s, %s, %s", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], gpr_map[ra3], gpr_map[rb3]); - return; - case 0xa: /* slli333 */ - case 0xe: /* addi333 */ - case 0xf: /* subi333 */ - func (stream, "%s\t%s, %s, %d", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], gpr_map[ra3], imm3u); - return; - case 0x10: /* lwi333 */ - case 0x14: /* swi333 */ - func (stream, "%s\t%s, [%s + %d]", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], gpr_map[ra3], imm3u << 2); - return; - case 0x12: /* lhi333 */ - case 0x16: /* shi333 */ - func (stream, "%s\t%s, [%s + %d]", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], gpr_map[ra3], imm3u << 1); - return; - case 0x13: /* lbi333 */ - case 0x17: /* sbi333 */ - func (stream, "%s\t%s, [%s + %d]", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], gpr_map[ra3], imm3u); - return; - case 0x11: /* lwi333.bi */ - case 0x15: /* swi333.bi */ - func (stream, "%s\t%s, [%s], %d", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], gpr_map[ra3], imm3u << 2); - return; - case 0x18: /* addri36.sp */ - func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt3], IMMU (insn, 6) << 2); - return; - case 0x19: /* lwi45.fe */ - func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt4], -((32 - imm5u) << 2)); - return; - case 0x1a: /* lwi450 */ - case 0x1b: /* swi450 */ - func (stream, "%s\t%s, [%s]", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt4], gpr_map[ra5]); - return; - case 0x34: /* beqzs8, bnezs8 */ - func (stream, "%s\t", ((insn & __BIT (8)) ? "bnezs8" : "beqzs8")); - info->print_address_func ((IMMS (insn, 8) << 1) + pc, info); - return; - case 0x35: /* break16, ex9.it */ - /* FIXME: Check bfd_mach. */ - if (imm9u < 32) /* break16 */ - func (stream, "break16\t%d", imm9u); - else - func (stream, "ex9.it\t%d", imm9u); - return; - case 0x3c: /* ifcall9 */ - func (stream, "%s\t", mnemonic_96[__GF (insn, 9, 6)]); - info->print_address_func ((IMMU (insn, 9) << 1) + pc, info); - return; - case 0x3d: /* movpi45 */ - func (stream, "%s\t%s, %d", mnemonic_96[__GF (insn, 9, 6)], - gpr_map[rt4], ra5 + 16); - return; - case 0x3f: /* MISC33 */ - func (stream, "%s\t%s, %s", mnemonic_misc33[rb3], - gpr_map[rt3], gpr_map[ra3]); - return; - case 0xb: /* ... */ - func (stream, "%s\t%s, %s", mnemonic_0xb[rb3], - gpr_map[rt3], gpr_map[ra3]); - return; + new_value = ((int_value & 0x1C) >> 2); } - - switch (__GF (insn, 10, 5)) + /* p = 0.bit[1:0], r = 0.bit[3:2]. */ + /* q = 1.bit[1:0], s = 1.bit[5:4]. */ + else if (strcmp (pfd->name, "im6_iq") == 0) { - case 0x0: /* mov55 or ifret16 */ - /* FIXME: Check bfd_mach. */ - if (rt5 == ra5 && rt5 == 31) - func (stream, "ifret16"); - else - func (stream, "mov55\t%s, %s", gpr_map[rt5], gpr_map[ra5]); - return; - case 0x1: /* movi55 */ - func (stream, "movi55\t%s, %d", gpr_map[rt5], IMMS (insn, 5)); - return; - case 0x1b: /* addi10s (V2) */ - func (stream, "addi10s\t%d", IMMS (insn, 10)); - return; + new_value |= 0x04; } - - switch (__GF (insn, 11, 4)) + else if (strcmp (pfd->name, "im6_ms") == 0) { - case 0x7: /* lwi37.fp/swi37.fp */ - func (stream, "%s\t%s, [$fp + 0x%x]", - ((insn & __BIT (7)) ? "swi37" : "lwi37"), - gpr_map[rt38], IMMU (insn, 7) << 2); - return; - case 0x8: /* beqz38 */ - case 0x9: /* bnez38 */ - func (stream, "%s\t%s, ", - ((__GF (insn, 11, 4) & 1) ? "bnez38" : "beqz38"), gpr_map[rt38]); - info->print_address_func ((IMMS (insn, 8) << 1) + pc, info); - return; - case 0xa: /* beqs38/j8, implied r5 */ - if (rt38 == 5) - { - func (stream, "j8\t"); - info->print_address_func ((IMMS (insn, 8) << 1) + pc, info); - } - else - { - func (stream, "beqs38\t%s, ", gpr_map[rt38]); - info->print_address_func ((IMMS (insn, 8) << 1) + pc, info); - } - return; - case 0xb: /* bnes38 and others */ - if (rt38 == 5) - { - switch (__GF (insn, 5, 3)) - { - case 0: /* jr5 */ - case 1: /* jral5 */ - case 4: /* ret5 */ - func (stream, "%s\t%s", mnemonic_bnes38[__GF (insn, 5, 3)], - gpr_map[ra5]); - return; - case 2: /* ex9.it imm5 */ - case 5: /* add5.pc */ - func (stream, "%s\t%d", mnemonic_bnes38[__GF (insn, 5, 3)], ra5); - return; - default: - func (stream, UNKNOWN_INSN_MSG); - return; - } - } - else - { - func (stream, "bnes38\t%s", gpr_map[rt3]); - info->print_address_func ((IMMS (insn, 8) << 1) + pc, info); - } - return; - case 0xe: /* lwi37/swi37 */ - func (stream, "%s\t%s, [+ 0x%x]", - ((insn & __BIT (7)) ? "swi37.sp" : "lwi37.sp"), - gpr_map[rt38], IMMU (insn, 7) << 2); - return; + new_value |= 0x04; + } + /* Rt CONCAT(c, t21, t0). */ + else if (strcmp (pfd->name, "a_rt21") == 0) + { + new_value = (insn & 0x00000020) >> 5; + new_value |= (insn & 0x00000C00) >> 9; + new_value |= (insn & 0x00008000) >> 12; + } + else if (strcmp (pfd->name, "a_rte") == 0) + { + new_value = (insn & 0x00000C00) >> 9; + new_value |= (insn & 0x00008000) >> 12; + } + else if (strcmp (pfd->name, "a_rte1") == 0) + { + new_value = (insn & 0x00000C00) >> 9; + new_value |= (insn & 0x00008000) >> 12; + new_value |= 0x01; } + else if (strcmp (pfd->name, "a_rte69") == 0) + { + new_value = int_value << 1; + } + else if (strcmp (pfd->name, "a_rte69_1") == 0) + { + new_value = int_value << 1; + new_value |= 0x01; + } + + psys_reg = nds32_find_reg_keyword (psys_reg, new_value); + if (!psys_reg) + func (stream, "???"); + else + func (stream, "$%s", psys_reg->name); } +/* Dump instruction. If the opcode is unknown, return FALSE. */ static void -print_insn32_mem (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, - uint32_t insn) +nds32_parse_opcode (struct nds32_opcode *opc, bfd_vma pc ATTRIBUTE_UNUSED, + disassemble_info *info, uint32_t insn, + uint32_t parse_mode) { - const int rt = RT5 (insn); - const int ra = RA5 (insn); - const int rb = RB5 (insn); - const int sv = __GF (insn, 8, 2); - const int op = insn & 0xFF; + int op = 0; fprintf_ftype func = info->fprintf_func; void *stream = info->stream; - - switch (op) + const char *pstr_src; + char *pstr_tmp; + char tmp_string[16]; + unsigned int push25gpr = 0, lsmwRb, lsmwRe, lsmwEnb4, checkbit, i; + int int_value, ifthe1st = 1; + const field_t *pfd; + keyword_t *psys_reg; + + if (opc == NULL) { - case 0x0: /* lb */ - case 0x1: /* lh */ - case 0x2: /* lw */ - case 0x3: /* ld */ - case 0x8: /* sb */ - case 0x9: /* sh */ - case 0xa: /* sw */ - case 0xb: /* sd */ - case 0x10: /* lbs */ - case 0x11: /* lhs */ - case 0x12: /* lws */ - case 0x18: /* llw */ - case 0x19: /* scw */ - case 0x20: /* lbup */ - case 0x22: /* lwup */ - case 0x28: /* sbup */ - case 0x2a: /* swup */ - func (stream, "%s\t%s, [%s + (%s << %d)]", - mnemonic_mem[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], sv); - break; - case 0x4: /* lb.bi */ - case 0x5: /* lh.bi */ - case 0x6: /* lw.bi */ - case 0x7: /* ld.bi */ - case 0xc: /* sb.bi */ - case 0xd: /* sh.bi */ - case 0xe: /* sw.bi */ - case 0xf: /* sd.bi */ - case 0x14: /* lbs.bi */ - case 0x15: /* lhs.bi */ - case 0x16: /* lws.bi */ - func (stream, "%s\t%s, [%s], (%s << %d)", - mnemonic_mem[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], sv); - break; - case 0x13: /* dpref */ - { - const char *subtype = "???"; - - if ((rt & 0xf) < ARRAY_SIZE (keyword_dpref)) - subtype = keyword_dpref[rt & 0xf]; - - func (stream, "%s\t%s, [%s + (%s << %d)]", - "dpref", subtype, gpr_map[ra], gpr_map[rb], sv); - } - break; - default: func (stream, UNKNOWN_INSN_MSG); return; } -} -static void -print_insn32_alu1 (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, uint32_t insn) -{ - int op = insn & 0x1f; - const int rt = RT5 (insn); - const int ra = RA5 (insn); - const int rb = RB5 (insn); - const int rd = RD5 (insn); - fprintf_ftype func = info->fprintf_func; - void *stream = info->stream; + if (parse_mode & NDS32_PARSE_EX9IT) + func (stream, " !"); - switch (op) + pstr_src = opc->instruction; + if (*pstr_src == 0) { - case 0x0: /* add, add_slli */ - case 0x1: /* sub, sub_slli */ - case 0x2: /* and, add_slli */ - case 0x3: /* xor, xor_slli */ - case 0x4: /* or, or_slli */ - if (rd != 0) - { - func (stream, "%s_slli\t%s, %s, %s, #%d", - mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], rd); - } - else - { - func (stream, "%s\t%s, %s, %s", - mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb]); - } - return; - case 0x1c: /* add_srli */ - case 0x1d: /* sub_srli */ - case 0x1e: /* and_srli */ - case 0x1f: /* xor_srli */ - case 0x15: /* or_srli */ - func (stream, "%s\t%s, %s, %s, #%d", - mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb], rd); - return; - case 0x5: /* nor */ - case 0x6: /* slt */ - case 0x7: /* slts */ - case 0xc: /* sll */ - case 0xd: /* srl */ - case 0xe: /* sra */ - case 0xf: /* rotr */ - case 0x12: /* bitc */ - case 0x18: /* sva */ - case 0x19: /* svs */ - case 0x1a: /* cmovz */ - case 0x1b: /* cmovn */ - func (stream, "%s\t%s, %s, %s", - mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], gpr_map[rb]); - return; - case 0x9: /* srli */ - if (ra ==0 && rb == 0 && rb==0) - { - func (stream, "nop"); - return; - } - case 0x8: /* slli */ - case 0xa: /* srai */ - case 0xb: /* rotri */ - func (stream, "%s\t%s, %s, #%d", - mnemonic_alu1[op], gpr_map[rt], gpr_map[ra], rb); - return; - case 0x10: /* seb */ - case 0x11: /* seh */ - case 0x13: /* zeh */ - case 0x14: /* wsbh */ - func (stream, "%s\t%s, %s", - mnemonic_alu1[op], gpr_map[rt], gpr_map[ra]); - return; - case 0x16: /* divsr */ - case 0x17: /* divr */ - func (stream, "%s\t%s, %s, %s, %s", - mnemonic_alu1[op], gpr_map[rt], gpr_map[rd], gpr_map[ra], gpr_map[rb]); - return; - default: - func (stream, UNKNOWN_INSN_MSG); + func (stream, "%s", opc->opcode); return; } + /* NDS32_PARSE_INSN16. */ + if (parse_mode & NDS32_PARSE_INSN16) + { + func (stream, "%s ", opc->opcode); + } - return; -} - -static void -print_insn32_alu2 (bfd_vma pc ATTRIBUTE_UNUSED, - disassemble_info *info, - uint32_t insn) -{ - int op = insn & 0x3ff; - const int rt = RT5 (insn); - const int ra = RA5 (insn); - const int rb = RB5 (insn); - fprintf_ftype func = info->fprintf_func; - void *stream = info->stream; - - if ((insn & 0x7f) == 0x4e) /* ffbi */ + /* NDS32_PARSE_INSN32. */ + else { - func (stream, "ffbi\t%s, %s, #0x%x", - gpr_map[rt], gpr_map[ra], __GF (insn, 7, 8)); - return; + op = N32_OP6 (insn); + if (op == N32_OP6_LSMW) + func (stream, "%s.", opc->opcode); + else if (strstr (opc->instruction, "tito")) + func (stream, "%s", opc->opcode); + else + func (stream, "%s ", opc->opcode); } - switch (op) + while (*pstr_src) { - case 0x0: /* max */ - case 0x1: /* min */ - case 0x2: /* ave */ - case 0xc: /* bse */ - case 0xd: /* bsp */ - case 0xe: /* ffb */ - case 0xf: /* ffmism */ - case 0x17: /* ffzmism */ - case 0x24: /* mul */ - func (stream, "%s\t%s, %s, %s", mnemonic_alu20[op], - gpr_map[rt], gpr_map[ra], gpr_map[rb]); - return; + switch (*pstr_src) + { + case '%': + case '=': + case '&': + pstr_src++; + /* compare with operand_fields[].name. */ + pstr_tmp = &tmp_string[0]; + while (*pstr_src) + { + if ((*pstr_src == ',') || (*pstr_src == ' ') + || (*pstr_src == '{') || (*pstr_src == '}') + || (*pstr_src == '[') || (*pstr_src == ']') + || (*pstr_src == '(') || (*pstr_src == ')') + || (*pstr_src == '+') || (*pstr_src == '<')) + break; + *pstr_tmp++ = *pstr_src++; + } + *pstr_tmp = 0; - case 0x3: /* abs */ - case 0x6: /* clo */ - case 0x7: /* clz */ - func (stream, "%s\t%s, %s", mnemonic_alu20[op], gpr_map[rt], gpr_map[ra]); - return; + pfd = (const field_t *) &operand_fields[0]; + while (1) + { + if (pfd->name == NULL) + return; + else if (strcmp (&tmp_string[0], pfd->name) == 0) + break; + pfd++; + } - case 0x4: /* clips */ - case 0x5: /* clip */ - case 0x8: /* bset */ - case 0x9: /* bclr */ - case 0xa: /* btgl */ - case 0xb: /* btst */ - func (stream, "%s\t%s, %s, #%d", mnemonic_alu20[op], - gpr_map[rt], gpr_map[ra], IMM1U (insn)); - return; + /* for insn-16. */ + if (parse_mode & NDS32_PARSE_INSN16) + { + if (pfd->hw_res == HW_GPR) + { + int_value = + __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; + /* push25/pop25. */ + if ((opc->value == 0xfc00) || (opc->value == 0xfc80)) + { + if (int_value == 0) + int_value = 6; + else + int_value = (6 + (0x01 << int_value)); + push25gpr = int_value; + } + else if (strcmp (pfd->name, "rt4") == 0) + { + int_value = nds32_r45map[int_value]; + } + func (stream, "$%s", keyword_gpr[int_value].name); + } + else if ((pfd->hw_res == HW_INT) || (pfd->hw_res == HW_UINT)) + { + if (pfd->hw_res == HW_INT) + int_value = + N32_IMMS ((insn >> pfd->bitpos), + pfd->bitsize) << pfd->shift; + else + int_value = + __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; + + /* movpi45. */ + if (opc->value == 0xfa00) + { + int_value += 16; + func (stream, "#0x%x", int_value); + } + /* lwi45.fe. */ + else if (opc->value == 0xb200) + { + int_value = 0 - (128 - int_value); + func (stream, "#%d", int_value); + } + /* beqz38/bnez38/beqs38/bnes38/j8/beqzs8/bnezs8/ifcall9. */ + else if ((opc->value == 0xc000) || (opc->value == 0xc800) + || (opc->value == 0xd000) || (opc->value == 0xd800) + || (opc->value == 0xd500) || (opc->value == 0xe800) + || (opc->value == 0xe900) + || (opc->value == 0xf800)) + { + info->print_address_func (int_value + pc, info); + } + /* push25/pop25. */ + else if ((opc->value == 0xfc00) || (opc->value == 0xfc80)) + { + func (stream, "#%d ! {$r6", int_value); + if (push25gpr != 6) + func (stream, "~$%s", keyword_gpr[push25gpr].name); + func (stream, ", $fp, $gp, $lp}"); + } + /* ex9.it. */ + else if ((opc->value == 0xdd40) || (opc->value == 0xea00)) + { + func (stream, "#%d", int_value); + nds32_ex9_info (pc, info, int_value); + } + else if (pfd->hw_res == HW_INT) + { + if (int_value < 0) + func (stream, "#%d", int_value); + else + func (stream, "#0x%x", int_value); + } + else /* if(pfd->hw_res == HW_UINT). */ + func (stream, "#0x%x", int_value); + } - case 0x20: /* mfusr */ - case 0x21: /* mtusr */ - func (stream, "%s\t%s, $%s", mnemonic_alu20[op], - gpr_map[rt], usr_map[__GF (insn, 10, 5)][__GF (insn, 15, 5)]); - return; - case 0x28: /* mults64 */ - case 0x29: /* mult64 */ - case 0x2a: /* madds64 */ - case 0x2b: /* madd64 */ - case 0x2c: /* msubs64 */ - case 0x2d: /* msub64 */ - case 0x2e: /* divs */ - case 0x2f: /* div */ - case 0x31: /* mult32 */ - case 0x33: /* madd32 */ - case 0x35: /* msub32 */ - func (stream, "%s\t$d%d, %s, %s", mnemonic_alu20[op], - rt >> 1, gpr_map[ra], gpr_map[rb]); - return; + } + /* for audio-ext. */ + else if (op == N32_OP6_AEXT) + { + nds32_parse_audio_ext (pfd, info, insn); + } + /* for insn-32. */ + else if (pfd->hw_res < _HW_LAST) + { + int_value = + __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; + + psys_reg = (keyword_t*) keywords[pfd->hw_res]; + + psys_reg = nds32_find_reg_keyword (psys_reg, int_value); + /* For HW_SR, dump the index when it can't + map the register name. */ + if (!psys_reg && pfd->hw_res == HW_SR) + func (stream, "%d", int_value); + else if (!psys_reg) + func (stream, "???"); + else + { + if (pfd->hw_res == HW_GPR || pfd->hw_res == HW_CPR + || pfd->hw_res == HW_FDR || pfd->hw_res == HW_FSR + || pfd->hw_res == HW_DXR || pfd->hw_res == HW_SR + || pfd->hw_res == HW_USR) + func (stream, "$%s", psys_reg->name); + else if (pfd->hw_res == HW_DTITON + || pfd->hw_res == HW_DTITOFF) + func (stream, ".%s", psys_reg->name); + else + func (stream, "%s", psys_reg->name); + } + } + else if ((pfd->hw_res == HW_INT) || (pfd->hw_res == HW_UINT)) + { + if (pfd->hw_res == HW_INT) + int_value = + N32_IMMS ((insn >> pfd->bitpos), pfd->bitsize) << pfd->shift; + else + int_value = + __GF (insn, pfd->bitpos, pfd->bitsize) << pfd->shift; + + if ((op == N32_OP6_BR1) || (op == N32_OP6_BR2)) + { + info->print_address_func (int_value + pc, info); + } + else if ((op == N32_OP6_BR3) && (pfd->bitpos == 0)) + { + info->print_address_func (int_value + pc, info); + } + else if (op == N32_OP6_JI) + { + /* FIXME: Handle relocation. */ + if (info->flags & INSN_HAS_RELOC) + pc = 0; + /* Check if insn32 in ex9 table. */ + if (parse_mode & NDS32_PARSE_EX9IT) + info->print_address_func ((pc & 0xFE000000) | int_value, + info); + /* Check if decode ex9 table, PC(31,25)|Inst(23,0)<<1. */ + else if (parse_mode & NDS32_PARSE_EX9TAB) + func (stream, "PC(31,25)|#0x%x", int_value); + else + info->print_address_func (int_value + pc, info); + } + else if (op == N32_OP6_LSMW) + { + /* lmw.adm/smw.adm. */ + func (stream, "#0x%x ! {", int_value); + lsmwEnb4 = int_value; + lsmwRb = ((insn >> 20) & 0x1F); + lsmwRe = ((insn >> 10) & 0x1F); + + /* If [Rb, Re] specifies at least one register, + Rb(4,0) <= Re(4,0) and 0 <= Rb(4,0), Re(4,0) < 28. + Disassembling does not consider this currently because of + the convience comparing with bsp320. */ + if (lsmwRb != 31 || lsmwRe != 31) + { + func (stream, "$%s", keyword_gpr[lsmwRb].name); + if (lsmwRb != lsmwRe) + func (stream, "~$%s", keyword_gpr[lsmwRe].name); + ifthe1st = 0; + } + if (lsmwEnb4 != 0) + { + /* $fp, $gp, $lp, $sp. */ + checkbit = 0x08; + for (i = 0; i < 4; i++) + { + if (lsmwEnb4 & checkbit) + { + if (ifthe1st == 1) + { + ifthe1st = 0; + func (stream, "$%s", keyword_gpr[28 + i].name); + } + else + func (stream, ", $%s", keyword_gpr[28 + i].name); + } + checkbit >>= 1; + } + } + func (stream, "}"); + } + else if (pfd->hw_res == HW_INT) + { + if (int_value < 0) + func (stream, "#%d", int_value); + else + func (stream, "#0x%x", int_value); + } + else /* if(pfd->hw_res == HW_UINT). */ + { + func (stream, "#0x%x", int_value); + } + } + break; - case 0x4f: /* flmism */ - case 0x68: /* mulsr64 */ - case 0x69: /* mulr64 */ - case 0x73: /* maddr32 */ - case 0x75: /* msubr32 */ - op = insn & 0x3f; - func (stream, "%s\t%s, %s, %s", mnemonic_alu21[op], - gpr_map[rt], gpr_map[ra], gpr_map[rb]); - return; - default: - func (stream, UNKNOWN_INSN_MSG); - return; - } + case '{': + case '}': + pstr_src++; + break; + + default: + func (stream, "%c", *pstr_src++); + break; + } /* switch (*pstr_src). */ + + } /* while (*pstr_src). */ + return; } +/* Filter instructions with some bits must be fixed. */ + static void -print_insn32_jreg (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, uint32_t insn) +nds32_filter_unknown_insn (uint32_t insn, struct nds32_opcode **opc) { - int op = insn & 0xff; - const int rt = RT5 (insn); - const int rb = RB5 (insn); - const char *dtit_on[] = { "", ".iton", ".dton", ".ton" }; - const char *dtit_off[] = { "", ".itoff", ".dtoff", ".toff" }; - const char *mnemonic_jreg[] = { "jr", "jral", "jrnez", "jralnez" }; - const char *mnemonic_ret[] = { "jr", "ret", NULL, "ifret" }; - const int dtit = __GF (insn, 8, 2); - fprintf_ftype func = info->fprintf_func; - void *stream = info->stream; + if (!(*opc)) + return; - switch (op) + switch ((*opc)->value) { - case 0: /* jr */ - func (stream, "%s%s\t%s", mnemonic_ret[op >> 5], - dtit_on[dtit], gpr_map[rb]); - return; - - case 0x20: /* ret */ - func (stream, "%s%s\t%s", mnemonic_ret[op >> 5], - dtit_off[dtit], gpr_map[rb]); - return; - case 0x60: /* ifret */ + case JREG (JR): + case JREG (JRNEZ): + /* jr jr.xtoff */ + if (__GF (insn, 6, 2) != 0 || __GF (insn, 15, 10) != 0) + *opc = NULL; break; - case 1: /* jral */ - case 2: /* jrnez */ - case 3: /* jralnez */ - func (stream, "%s%s\t%s, %s", mnemonic_jreg[op], - dtit_on[dtit], gpr_map[rt], gpr_map[rb]); - return; - default: /* unknown */ - func (stream, UNKNOWN_INSN_MSG); + case MISC (STANDBY): + if (__GF (insn, 7, 18) != 0) + *opc = NULL; + break; + case SIMD (PBSAD): + case SIMD (PBSADA): + if (__GF (insn, 5, 5) != 0) + *opc = NULL; + break; + case BR2 (IFCALL): + if (__GF (insn, 20, 5) != 0) + *opc = NULL; + break; + case JREG (JRAL): + if (__GF (insn, 5, 3) != 0 || __GF (insn, 15, 5) != 0) + *opc = NULL; + break; + case ALU1 (NOR): + case ALU1 (SLT): + case ALU1 (SLTS): + case ALU1 (SLLI): + case ALU1 (SRLI): + case ALU1 (SRAI): + case ALU1 (ROTRI): + case ALU1 (SLL): + case ALU1 (SRL): + case ALU1 (SRA): + case ALU1 (ROTR): + case ALU1 (SEB): + case ALU1 (SEH): + case ALU1 (ZEH): + case ALU1 (WSBH): + case ALU1 (SVA): + case ALU1 (SVS): + case ALU1 (CMOVZ): + case ALU1 (CMOVN): + if (__GF (insn, 5, 5) != 0) + *opc = NULL; + break; + case MISC (IRET): + case MISC (ISB): + case MISC (DSB): + if (__GF (insn, 5, 20) != 0) + *opc = NULL; break; } } static void -print_insn32_misc (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, - uint32_t insn) +print_insn32 (bfd_vma pc, disassemble_info *info, uint32_t insn, + uint32_t parse_mode) { - int op = insn & 0x1f; - int rt = RT5 (insn); - unsigned int id; - fprintf_ftype func = info->fprintf_func; - void *stream = info->stream; - - static const char *keyword_standby[] = - { - "no_wake_grant", "wake_grant", "wait_done", - }; - static const char *keyword_tlbop[] = - { - "TRD", "TWR", "RWR", "RWLK", "UNLK", "PB", "INV", "FLUA" - }; - - switch (op) - { - case 0x0: /* standby */ - id = __GF (insn, 5, 20); - if (id < ARRAY_SIZE (keyword_standby)) - func (stream, "standby\t%s", keyword_standby[id]); - else - func (stream, "standby\t%d", id); - return; - case 0x1: /* cctl */ - func (stream, "cctl\t!FIXME"); - return; - case 0x8: /* dsb */ - case 0x9: /* isb */ - case 0xd: /* isync */ - case 0xc: /* msync */ - case 0x4: /* iret */ - func (stream, "%s", mnemonic_misc[op]); - return; - case 0x5: /* trap */ - case 0xa: /* break */ - case 0xb: /* syscall */ - id = __GF (insn, 5, 15); - func (stream, "%s\t%d", mnemonic_misc[op], id); - return; - case 0x2: /* mfsr */ - case 0x3: /* mtsr */ - /* FIXME: setend, setgie. */ - func (stream, "%s\t%s, $%s", mnemonic_misc[op], gpr_map[rt], - sr_map[__GF(insn, 17, 3)][__GF(insn, 13, 4)][__GF(insn, 10, 3)]); - return; - case 0x6: /* teqz */ - case 0x7: /* tnez */ - id = __GF (insn, 5, 15); - func (stream, "%s\t%s, %d", mnemonic_misc[op], gpr_map[rt], id); - return; - case 0xe: /* tlbop */ - id = __GF (insn, 5, 5); - if (id < ARRAY_SIZE (keyword_tlbop)) - func (stream, "tlbop\t%s", keyword_tlbop[id]); - else - func (stream, "tlbop\t%d", id); - return; - } + /* Get the final correct opcode and parse. */ + struct nds32_opcode *opc; + uint32_t opcode = nds32_mask_opcode (insn); + opc = (struct nds32_opcode *) htab_find (opcode_htab, &opcode); + + nds32_special_opcode (insn, &opc); + nds32_filter_unknown_insn (insn, &opc); + nds32_parse_opcode (opc, pc, info, insn, parse_mode); } static void -print_insn32_fpu (bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info, - uint32_t insn) +print_insn16 (bfd_vma pc, disassemble_info *info, + uint32_t insn, uint32_t parse_mode) { - int op = insn & 0xf; - int mask_sub_op = (insn & 0x3c0) >> 6; - int mask_bi = (insn & 0x80) >> 7; - int mask_cfg = (insn & 0x7c00) >> 10; - int mask_f2op = (insn & 0x7c00) >> 10; - int dp = 0; - int dp_insn = 0; - char wd = 's'; - const int rt = RT5 (insn); - const int ra = RA5 (insn); - const int rb = RB5 (insn); - const int sv = __GF (insn, 8, 2); - fprintf_ftype func = info->fprintf_func; - void *stream = info->stream; + struct nds32_opcode *opc; + uint32_t opcode; + + /* Get highest 7 bit in default. */ + unsigned int mask = 0xfe00; - switch (op) + /* Classify 16-bit instruction to 4 sets by bit 13 and 14. */ + switch (__GF (insn, 13, 2)) { - case 0x0: /* fs1 */ - case 0x8: /* fd1 */ - dp = (op & 0x8) ? 1 : 0; - if (dp) + case 0x0: + /* mov55 movi55 */ + if (__GF (insn, 11, 2) == 0) { - wd = 'd'; - dp_insn = 14; + mask = 0xfc00; + /* ifret16 = mov55 $sp, $sp*/ + if (__GF (insn, 0, 11) == 0x3ff) + mask = 0xffff; } - else + else if (__GF (insn, 9, 4) == 0xb) + mask = 0xfe07; + break; + case 0x1: + /* lwi37 swi37 */ + if (__GF (insn, 11, 2) == 0x3) + mask = 0xf880; + break; + case 0x2: + mask = 0xf800; + /* Exclude beqz38, bnez38, beqs38, and bnes38. */ + if (__GF (insn, 12, 1) == 0x1 + && __GF (insn, 8, 3) == 0x5) { - wd = 's'; - dp_insn = 0; + if (__GF (insn, 11, 1) == 0x0) + mask = 0xff00; + else + mask = 0xffe0; } - switch (mask_sub_op) + break; + case 0x3: + switch (__GF (insn, 11, 2)) { - case 0x0: case 0x1: + /* beqzs8 bnezs8 */ + if (__GF (insn, 9, 2) == 0x0) + mask = 0xff00; + /* addi10s */ + else if (__GF(insn, 10, 1) == 0x1) + mask = 0xfc00; + break; case 0x2: + /* lwi37.sp swi37.sp */ + mask = 0xf880; + break; case 0x3: - case 0x4: - case 0x5: - case 0x8: - case 0x9: - case 0xc: - case 0xd: - func (stream, "%s\t$f%c%d, $f%c%d, $f%c%d", - mnemonic_alu[mask_sub_op + dp_insn], - wd, rt, wd, ra, wd, rb); - return; - case 0x6: - case 0x7: - func (stream, "%s\t$f%c%d, $f%c%d, $fs%d", - mnemonic_alu[mask_sub_op + dp_insn], - wd, rt, wd, ra, rb); - return; - case 0xf: - if (dp) - { - wd = 'd'; - dp_insn = 0x1d; - } - else - { - wd = 's'; - dp_insn = 0; - } + if (__GF (insn, 8, 3) == 0x5) + mask = 0xff00; + else if (__GF (insn, 8, 3) == 0x4) + mask = 0xff80; + else if (__GF (insn, 9 , 2) == 0x3) + mask = 0xfe07; + break; + } + break; + } + opcode = insn & mask; + opc = (struct nds32_opcode *) htab_find (opcode_htab, &opcode); + + nds32_special_opcode (insn, &opc); + /* Get the final correct opcode and parse it. */ + nds32_parse_opcode (opc, pc, info, insn, parse_mode); +} + +static hashval_t +htab_hash_hash (const void *p) +{ + return (*(unsigned int *) p) % 49; +} + +static int +htab_hash_eq (const void *p, const void *q) +{ + uint32_t pinsn = ((struct nds32_opcode *) p)->value; + uint32_t qinsn = *((uint32_t *) q); + + return (pinsn == qinsn); +} + +/* Get the format of instruction. */ - switch (mask_f2op) +static uint32_t +nds32_mask_opcode (uint32_t insn) +{ + uint32_t opcode = N32_OP6 (insn); + switch (opcode) + { + case N32_OP6_LBI: + case N32_OP6_LHI: + case N32_OP6_LWI: + case N32_OP6_LDI: + case N32_OP6_LBI_BI: + case N32_OP6_LHI_BI: + case N32_OP6_LWI_BI: + case N32_OP6_LDI_BI: + case N32_OP6_SBI: + case N32_OP6_SHI: + case N32_OP6_SWI: + case N32_OP6_SDI: + case N32_OP6_SBI_BI: + case N32_OP6_SHI_BI: + case N32_OP6_SWI_BI: + case N32_OP6_SDI_BI: + case N32_OP6_LBSI: + case N32_OP6_LHSI: + case N32_OP6_LWSI: + case N32_OP6_LBSI_BI: + case N32_OP6_LHSI_BI: + case N32_OP6_LWSI_BI: + case N32_OP6_MOVI: + case N32_OP6_SETHI: + case N32_OP6_ADDI: + case N32_OP6_SUBRI: + case N32_OP6_ANDI: + case N32_OP6_XORI: + case N32_OP6_ORI: + case N32_OP6_SLTI: + case N32_OP6_SLTSI: + case N32_OP6_CEXT: + case N32_OP6_BITCI: + return MASK_OP (insn, 0); + case N32_OP6_ALU2: + /* FFBI */ + if (__GF (insn, 0, 7) == (N32_ALU2_FFBI | __BIT (6))) + return MASK_OP (insn, 0x7f); + else if (__GF (insn, 0, 7) == (N32_ALU2_MFUSR | __BIT (6)) + || __GF (insn, 0, 7) == (N32_ALU2_MTUSR | __BIT (6))) + /* RDOV CLROV */ + return MASK_OP (insn, 0xf81ff); + return MASK_OP (insn, 0x1ff); + case N32_OP6_ALU1: + case N32_OP6_SIMD: + return MASK_OP (insn, 0x1f); + case N32_OP6_MEM: + return MASK_OP (insn, 0xff); + case N32_OP6_JREG: + return MASK_OP (insn, 0x7f); + case N32_OP6_LSMW: + return MASK_OP (insn, 0x23); + case N32_OP6_SBGP: + case N32_OP6_LBGP: + return MASK_OP (insn, 0x1 << 19); + case N32_OP6_HWGP: + if (__GF (insn, 18, 2) == 0x3) + return MASK_OP (insn, 0x7 << 17); + return MASK_OP (insn, 0x3 << 18); + case N32_OP6_DPREFI: + return MASK_OP (insn, 0x1 << 24); + case N32_OP6_LWC: + case N32_OP6_SWC: + case N32_OP6_LDC: + case N32_OP6_SDC: + return MASK_OP (insn, 0x1 << 12); + case N32_OP6_JI: + return MASK_OP (insn, 0x1 << 24); + case N32_OP6_BR1: + return MASK_OP (insn, 0x1 << 14); + case N32_OP6_BR2: + return MASK_OP (insn, 0xf << 16); + case N32_OP6_BR3: + return MASK_OP (insn, 0x1 << 19); + case N32_OP6_MISC: + switch (__GF (insn, 0, 5)) + { + case N32_MISC_MTSR: + /* SETGIE and SETEND */ + if (__GF (insn, 5, 5) == 0x1 || __GF (insn, 5, 5) == 0x2) + return MASK_OP (insn, 0x1fffff); + return MASK_OP (insn, 0x1f); + case N32_MISC_TLBOP: + if (__GF (insn, 5, 5) == 5 || __GF (insn, 5, 5) == 7) + /* PB FLUA */ + return MASK_OP (insn, 0x3ff); + return MASK_OP (insn, 0x1f); + default: + return MASK_OP (insn, 0x1f); + } + case N32_OP6_COP: + if (__GF (insn, 4, 2) == 0) + { + /* FPU */ + switch (__GF (insn, 0, 4)) { case 0x0: - if (dp) - func (stream, "%s\t$fs%d, $fd%d", - mnemonic_fpu_2op[mask_f2op + dp_insn], rt, ra); - else - func (stream, "%s\t$fd%d, $fs%d", - mnemonic_fpu_2op[mask_f2op + dp_insn], rt, ra); - return; - case 0x1: - case 0x5: - func (stream, "%s\t$f%c%d, $f%c%d", - mnemonic_fpu_2op[mask_f2op + dp_insn], wd, rt, wd, ra); - return; case 0x8: + /* FS1/F2OP FD1/F2OP */ + if (__GF (insn, 6, 4) == 0xf) + return MASK_OP (insn, 0x7fff); + /* FS1 FD1 */ + return MASK_OP (insn, 0x3ff); + case 0x4: case 0xc: - func (stream, "%s\t$f%c%d, $fs%d", - mnemonic_fpu_2op[mask_f2op + dp_insn], wd, rt, ra); - return; - case 0x10: - case 0x14: - case 0x18: - case 0x1c: - func (stream, "%s\t$fs%d, $f%c%d", - mnemonic_fpu_2op[mask_f2op + dp_insn], rt, wd, ra); - return; + /* FS2 */ + return MASK_OP (insn, 0x3ff); + case 0x1: + case 0x9: + /* XR */ + if (__GF (insn, 6, 4) == 0xc) + return MASK_OP (insn, 0x7fff); + /* MFCP MTCP */ + return MASK_OP (insn, 0x3ff); + default: + return MASK_OP (insn, 0xff); } } - case 0x1: /* mfcp */ - switch (mask_sub_op) + else if (__GF (insn, 0, 2) == 0) + return MASK_OP (insn, 0xf); + return MASK_OP (insn, 0xcf); + case N32_OP6_AEXT: + /* AUDIO */ + switch (__GF (insn, 23, 2)) { case 0x0: - func (stream, "fmfsr\t%s, $fs%d", gpr_map[rt], ra); - return; - case 0x1: - func (stream, "fmfdr\t%s, $fd%d", gpr_map[rt], ra); - return; - case 0xc: - if (mask_cfg) - func (stream, "fmfcsr\t%s", gpr_map[rt]); + if (__GF (insn, 5, 4) == 0) + /* AMxxx AMAyyS AMyyS AMAWzS AMWzS */ + return MASK_OP (insn, (0x1f << 20) | 0x1ff); + else if (__GF (insn, 5, 4) == 1) + /* ALR ASR ALA ASA AUPI */ + return MASK_OP (insn, (0x1f << 20) | (0xf << 5)); + else if (__GF (insn, 20, 3) == 0 && __GF (insn, 6, 3) == 1) + /* ALR2 */ + return MASK_OP (insn, (0x1f << 20) | (0x7 << 6)); + else if (__GF (insn, 20 ,3) == 2 && __GF (insn, 6, 3) == 1) + /* AWEXT ASATS48 */ + return MASK_OP (insn, (0x1f << 20) | (0xf << 5)); + else if (__GF (insn, 20 ,3) == 3 && __GF (insn, 6, 3) == 1) + /* AMTAR AMTAR2 AMFAR AMFAR2 */ + return MASK_OP (insn, (0x1f << 20) | (0x1f << 5)); + else if (__GF (insn, 7, 2) == 3) + /* AMxxxSA */ + return MASK_OP (insn, (0x1f << 20) | (0x3 << 7)); + else if (__GF (insn, 6, 3) == 2) + /* AMxxxL.S */ + return MASK_OP (insn, (0x1f << 20) | (0xf << 5)); else - func (stream, "fmfcfg\t%s", gpr_map[rt]); - return; - } - case 0x2: /* fls */ - if (mask_bi) - func (stream, "fls.bi\t$fs%d, [%s], (%s << %d)", - rt, gpr_map[ra], gpr_map[rb], sv); - else - func (stream, "fls\t$fs%d, [%s + (%s << %d)]", - rt, gpr_map[ra], gpr_map[rb], sv); - return; - case 0x3: /* fld */ - if (mask_bi) - func (stream, "fld.bi\t$fd%d, [%s], (%s << %d)", - rt, gpr_map[ra], gpr_map[rb], sv); - else - func (stream, "fld\t$fd%d, [%s + (%s << %d)]", - rt, gpr_map[ra], gpr_map[rb], sv); - return; - case 0x4: /* fs2 */ - func (stream, "%s\t$fs%d, $fs%d, $fs%d", - mnemonic_fs2_cmp[mask_sub_op], rt, ra, rb); - return; - case 0x9: /* mtcp */ - switch (mask_sub_op) - { - case 0x0: - func (stream, "fmtsr\t%s, $fs%d", gpr_map[rt], ra); - return; + /* AmxxxL.l AmxxxL2.S AMxxxL2.L */ + return MASK_OP (insn, (0x1f << 20) | (0x7 << 6)); case 0x1: - func (stream, "fmtdr\t%s, $fd%d", gpr_map[rt], ra); - return; - case 0xc: - func (stream, "fmtcsr\t%s", gpr_map[rt]); - return; + if (__GF (insn, 20, 3) == 0) + /* AADDL ASUBL */ + return MASK_OP (insn, (0x1f << 20) | (0x1 << 5)); + else if (__GF (insn, 20, 3) == 1) + /* AMTARI Ix AMTARI Mx */ + return MASK_OP (insn, (0x1f << 20)); + else if (__GF (insn, 6, 3) == 2) + /* AMAWzSl.S AMWzSl.S */ + return MASK_OP (insn, (0x1f << 20) | (0xf << 5)); + else if (__GF (insn, 7, 2) == 3) + /* AMAWzSSA AMWzSSA */ + return MASK_OP (insn, (0x1f << 20) | (0x3 << 7)); + else + /* AMAWzSL.L AMAWzSL2.S AMAWzSL2.L AMWzSL.L AMWzSL.L AMWzSL2.S */ + return MASK_OP (insn, (0x1f << 20) | (0x7 << 6)); + case 0x2: + if (__GF (insn, 6, 3) == 2) + /* AMAyySl.S AMWyySl.S */ + return MASK_OP (insn, (0x1f << 20) | (0xf << 5)); + else if (__GF (insn, 7, 2) == 3) + /* AMAWyySSA AMWyySSA */ + return MASK_OP (insn, (0x1f << 20) | (0x3 << 7)); + else + /* AMAWyySL.L AMAWyySL2.S AMAWyySL2.L AMWyySL.L AMWyySL.L AMWyySL2.S */ + return MASK_OP (insn, (0x1f << 20) | (0x7 << 6)); } - case 0xa: /* fss */ - if (mask_bi) - func (stream, "fss.bi\t$fs%d, [%s], (%s << %d)", - rt, gpr_map[ra], gpr_map[rb], sv); - else - func (stream, "fss\t$fs%d, [%s + (%s << %d)]", - rt, gpr_map[ra], gpr_map[rb], sv); - return; - case 0xb: /* fsd */ - if (mask_bi) - func (stream, "fsd.bi\t$fd%d, [%s], (%s << %d)", - rt, gpr_map[ra], gpr_map[rb], sv); - else - func (stream, "fsd\t$fd%d, [%s + (%s << %d)]", - rt, gpr_map[ra], gpr_map[rb], sv); - return; - case 0xc: /* fd2 */ - func (stream, "%s\t$fs%d, $fd%d, $fd%d", - mnemonic_fd2_cmp[mask_sub_op], rt, ra, rb); - return; + return MASK_OP (insn, 0x1f << 20); + default: + return (1 << 31); } } -static void -print_insn32 (bfd_vma pc, disassemble_info *info, uint32_t insn) +/* Define cctl subtype. */ +static char *cctl_subtype [] = { - int op = OP6 (insn); - const int rt = RT5 (insn); - const int ra = RA5 (insn); - const int rb = RB5 (insn); - const int imm15s = IMMS (insn, 15); - const int imm15u = IMMU (insn, 15); - uint32_t shift; - fprintf_ftype func = info->fprintf_func; - void *stream = info->stream; - - switch (op) - { - case 0x0: /* lbi */ - case 0x1: /* lhi */ - case 0x2: /* lwi */ - case 0x3: /* ldi */ - case 0x8: /* sbi */ - case 0x9: /* shi */ - case 0xa: /* swi */ - case 0xb: /* sdi */ - case 0x10: /* lbsi */ - case 0x11: /* lhsi */ - case 0x12: /* lwsi */ - shift = op & 0x3; - func (stream, "%s\t%s, [%s + #%d]", - mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15s << shift); - return; - case 0x4: /* lbi.bi */ - case 0x5: /* lhi.bi */ - case 0x6: /* lwi.bi */ - case 0x7: /* ldi.bi */ - case 0xc: /* sbi.bi */ - case 0xd: /* shi.bi */ - case 0xe: /* swi.bi */ - case 0xf: /* sdi.bi */ - case 0x14: /* lbsi.bi */ - case 0x15: /* lhsi.bi */ - case 0x16: /* lwsi.bi */ - shift = op & 0x3; - func (stream, "%s\t%s, [%s], #%d", - mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15s << shift); - return; - case 0x13: /* dprefi */ - { - const char *subtype = "???"; - char wd = 'w'; + /* 0x0 */ + "st0", "st0", "st0", "st2", "st2", "st3", "st3", "st4", + "st1", "st1", "st1", "st0", "st0", NULL, NULL, "st5", + /* 0x10 */ + "st0", NULL, NULL, "st2", "st2", "st3", "st3", NULL, + "st1", NULL, NULL, "st0", "st0", NULL, NULL, NULL +}; - shift = 2; +/* Check the subset of opcode. */ - /* d-bit */ - if (rt & 0x10) - { - wd = 'd'; - shift = 3; - } +static void +nds32_special_opcode (uint32_t insn, struct nds32_opcode **opc) +{ + char *string = NULL; + uint32_t op; - if ((rt & 0xf) < ARRAY_SIZE (keyword_dpref)) - subtype = keyword_dpref[rt & 0xf]; + if (!(*opc)) + return; - func (stream, "%s.%c\t%s, [%s + #%d]", - mnemonic_op6[op], wd, subtype, gpr_map[ra], imm15s << shift); - } - return; - case 0x17: /* LBGP */ - func (stream, "%s\t%s, [+ %d]", - ((insn & __BIT (19)) ? "lbsi.gp" : "lbi.gp"), - gpr_map[rt], IMMS (insn, 19)); - return; - case 0x18: /* LWC */ - case 0x19: /* SWC */ - case 0x1a: /* LDC */ - case 0x1b: /* SDC */ + /* Check if special case. */ + switch ((*opc)->value) + { + case OP6 (LWC): + case OP6 (SWC): + case OP6 (LDC): + case OP6 (SDC): + case FPU_RA_IMMBI (LWC): + case FPU_RA_IMMBI (SWC): + case FPU_RA_IMMBI (LDC): + case FPU_RA_IMMBI (SDC): + /* Check if cp0 => FPU. */ if (__GF (insn, 13, 2) == 0) - { - char ls = (op & 1) ? 's' : 'l'; - char wd = (op & 2) ? 'd' : 's'; - - if (insn & __BIT (12)) - { - func (stream, "f%c%ci.bi\t$f%c%d, [%s], %d", ls, wd, - wd, rt, gpr_map[ra], IMMS (insn, 12) << 2); - } - else - { - func (stream, "f%c%ci\t$f%c%d, [%s + %d]", ls, wd, - wd, rt, gpr_map[ra], IMMS (insn, 12) << 2); - } - } - else - { - char ls = (op & 1) ? 's' : 'l'; - char wd = (op & 2) ? 'd' : 'w'; - int cp = __GF (insn, 13, 2); - - if (insn & __BIT (12)) - { - func (stream, "cp%c%ci\tcp%d, $cpr%d, [%s], %d", ls, wd, - cp, rt, gpr_map[ra], IMMS (insn, 12) << 2); - } - else - { - func (stream, "cp%c%ci\tcp%d, $cpr%d, [%s + %d]", ls, wd, - cp, rt, gpr_map[ra], IMMS (insn, 12) << 2); - } - } - return; - case 0x1c: /* MEM */ - print_insn32_mem (pc, info, insn); - return; - case 0x1d: /* LSMW */ { - int enb4 = __GF (insn, 6, 4); - char ls = (insn & __BIT (5)) ? 's' : 'l'; - char ab = (insn & __BIT (4)) ? 'a' : 'b'; - char *di = (insn & __BIT (3)) ? "d" : "i"; - char *m = (insn & __BIT (2)) ? "m" : ""; - static const char *s[] = {"", "a", "zb", "?"}; - - /* lsmwzb only always increase. */ - if ((insn & 0x3) == 2) - di = ""; - - func (stream, "%cmw%s.%c%s%s\t%s, [%s], %s, 0x%x", - ls, s[insn & 0x3], ab, di, m, gpr_map[rt], - gpr_map[ra], gpr_map[rb], enb4); + while (!((*opc)->attr & ATTR (FPU)) && (*opc)->next) + *opc = (*opc)->next; } - return; - case 0x1e: /* HWGP */ - op = __GF (insn, 17, 3); - switch (op) - { - case 0: case 1: /* lhi.gp */ - case 2: case 3: /* lhsi.gp */ - case 4: case 5: /* shi.gp */ - func (stream, "%s\t%s, [+ %d]", - mnemonic_hwgp[op], gpr_map[rt], IMMS (insn, 18) << 1); - return; - case 6: /* lwi.gp */ - case 7: /* swi.gp */ - func (stream, "%s\t%s, [+ %d]", - mnemonic_hwgp[op], gpr_map[rt], IMMS (insn, 17) << 2); - return; - } - return; - case 0x1f: /* SBGP */ - if (insn & __BIT (19)) - func (stream, "addi.gp\t%s, %d", - gpr_map[rt], IMMS (insn, 19)); - else - func (stream, "sbi.gp\t%s, [+ %d]", - gpr_map[rt], IMMS (insn, 19)); - return; - case 0x20: /* ALU_1 */ - print_insn32_alu1 (pc, info, insn); - return; - case 0x21: /* ALU_2 */ - print_insn32_alu2 (pc, info, insn); - return; - case 0x22: /* movi */ - func (stream, "movi\t%s, %d", gpr_map[rt], IMMS (insn, 20)); - return; - case 0x23: /* sethi */ - func (stream, "sethi\t%s, 0x%x", gpr_map[rt], IMMU (insn, 20)); - return; - case 0x24: /* ji, jal */ - /* FIXME: Handle relocation. */ - if (info->flags & INSN_HAS_RELOC) - pc = 0; - func (stream, "%s\t", ((insn & __BIT (24)) ? "jal" : "j")); - info->print_address_func ((IMMS (insn, 24) << 1) + pc, info); - return; - case 0x25: /* jreg */ - print_insn32_jreg (pc, info, insn); - return; - case 0x26: /* br1 */ - func (stream, "%s\t%s, %s, ", ((insn & __BIT (14)) ? "bne" : "beq"), - gpr_map[rt], gpr_map[ra]); - info->print_address_func ((IMMS (insn, 14) << 1) + pc, info); - return; - case 0x27: /* br2 */ - func (stream, "%s\t%s, ", mnemonic_br2[__GF (insn, 16, 4)], - gpr_map[rt]); - info->print_address_func ((IMMS (insn, 16) << 1) + pc, info); - return; - case 0x28: /* addi */ - case 0x2e: /* slti */ - case 0x2f: /* sltsi */ - case 0x29: /* subri */ - func (stream, "%s\t%s, %s, %d", - mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15s); - return; - case 0x2a: /* andi */ - case 0x2b: /* xori */ - case 0x2c: /* ori */ - case 0x33: /* bitci */ - func (stream, "%s\t%s, %s, %d", - mnemonic_op6[op], gpr_map[rt], gpr_map[ra], imm15u); - return; - case 0x2d: /* br3, beqc, bnec */ - func (stream, "%s\t%s, %d, ", ((insn & __BIT (19)) ? "bnec" : "beqc"), - gpr_map[rt], __SEXT (__GF (insn, 8, 11), 11)); - info->print_address_func ((IMMS (insn, 8) << 1) + pc, info); - return; - case 0x32: /* misc */ - print_insn32_misc (pc, info, insn); - return; - case 0x35: /* FPU */ - print_insn32_fpu (pc, info, insn); + break; + case ALU1 (ADD): + case ALU1 (SUB): + case ALU1 (AND): + case ALU1 (XOR): + case ALU1 (OR): + /* Check if (add/add_slli) (sub/sub_slli) (and/and_slli). */ + if (N32_SH5(insn) != 0) + string = "sh"; + break; + case ALU1 (SRLI): + /* Check if nop. */ + if (__GF (insn, 10, 15) == 0) + string = "nop"; + break; + case MISC (CCTL): + string = cctl_subtype [__GF (insn, 5, 5)]; + break; + case JREG (JR): + case JREG (JRAL): + case JREG (JR) | JREG_RET: + if (__GF (insn, 8, 2) != 0) + string = "tit"; + break; + case N32_OP6_COP: + break; + case 0xea00: + /* break16 ex9 */ + if (__GF (insn, 5, 4) != 0) + string = "ex9"; + break; + case 0x9200: + /* nop16 */ + if (__GF (insn, 0, 9) == 0) + string = "nop16"; + break; + } + + if (string) + { + while (strstr ((*opc)->opcode, string) == NULL + && strstr ((*opc)->instruction, string) == NULL && (*opc)->next) + *opc = (*opc)->next; return; } + + /* Classify instruction is COP or FPU. */ + op = N32_OP6 (insn); + if (op == N32_OP6_COP && __GF (insn, 4, 2) != 0) + { + while (((*opc)->attr & ATTR (FPU)) != 0 && (*opc)->next) + *opc = (*opc)->next; + } } int @@ -1258,26 +977,75 @@ print_insn_nds32 (bfd_vma pc, disassemble_info *info) int status; bfd_byte buf[4]; uint32_t insn; + static int init = 1; + int i = 0; + struct nds32_opcode *opc; + struct nds32_opcode **slot; + + if (init) + { + /* Build opcode table. */ + opcode_htab = htab_create_alloc (1024, htab_hash_hash, htab_hash_eq, + NULL, xcalloc, free); - status = info->read_memory_func (pc, (bfd_byte *) buf, 2, info); + while (nds32_opcodes[i].opcode != NULL) + { + opc = &nds32_opcodes[i]; + slot = + (struct nds32_opcode **) htab_find_slot (opcode_htab, &opc->value, + INSERT); + if (*slot == NULL) + { + /* This is the new one. */ + *slot = opc; + } + else + { + /* Already exists. Append to the list. */ + opc = *slot; + while (opc->next) + opc = opc->next; + opc->next = &nds32_opcodes[i]; + } + i++; + } + init = 0; + } + + status = info->read_memory_func (pc, (bfd_byte *) buf, 4, info); if (status) - return -1; + { + /* for the last 16-bit instruction. */ + status = info->read_memory_func (pc, (bfd_byte *) buf, 2, info); + if (status) + { + (*info->memory_error_func)(status, pc, info); + return -1; + } + } + insn = bfd_getb32 (buf); /* 16-bit instruction. */ - if (buf[0] & 0x80) + if (insn & 0x80000000) { - insn = bfd_getb16 (buf); - print_insn16 (pc, info, insn); + if (info->section && strstr (info->section->name, ".ex9.itable") != NULL) + { + print_insn16 (pc, info, (insn & 0x0000FFFF), + NDS32_PARSE_INSN16 | NDS32_PARSE_EX9TAB); + return 4; + } + print_insn16 (pc, info, (insn >> 16), NDS32_PARSE_INSN16); return 2; } /* 32-bit instructions. */ - status = info->read_memory_func (pc + 2, (bfd_byte *) buf + 2, 2, info); - if (status) - return -1; - - insn = bfd_getb32 (buf); - print_insn32 (pc, info, insn); - - return 4; + else + { + if (info->section + && strstr (info->section->name, ".ex9.itable") != NULL) + print_insn32 (pc, info, insn, NDS32_PARSE_INSN32 | NDS32_PARSE_EX9TAB); + else + print_insn32 (pc, info, insn, NDS32_PARSE_INSN32); + return 4; + } } |