diff options
| -rw-r--r-- | bfd/elfxx-riscv.c | 33 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/imply.d | 12 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/imply.s | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/march-help.l | 20 |
4 files changed, 78 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 44dd624..b3adbed 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1214,6 +1214,12 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "+f,+zca", check_implicit_always}, {"zcmp", "+zca", check_implicit_always}, + {"shcounterenw", "+h", check_implicit_always}, + {"shgatpa", "+h", check_implicit_always}, + {"shtvala", "+h", check_implicit_always}, + {"shvsatpa", "+h", check_implicit_always}, + {"shvstvala", "+h", check_implicit_always}, + {"shvstvecd", "+h", check_implicit_always}, {"h", "+zicsr", check_implicit_always}, {"zhinx", "+zhinxmin", check_implicit_always}, {"zhinxmin", "+zfinx", check_implicit_always}, @@ -1253,9 +1259,16 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"ssaia", "+zicsr", check_implicit_always}, {"sscsrind", "+zicsr", check_implicit_always}, {"sscofpmf", "+zicsr", check_implicit_always}, + {"sscounterenw", "+zicsr", check_implicit_always}, {"ssstateen", "+zicsr", check_implicit_always}, {"sstc", "+zicsr", check_implicit_always}, + {"sstvala", "+zicsr", check_implicit_always}, + {"sstvecd", "+zicsr", check_implicit_always}, + {"ssu64xl", "+zicsr", check_implicit_always}, + + {"svade", "+zicsr", check_implicit_always}, {"svadu", "+zicsr", check_implicit_always}, + {"svbare", "+zicsr", check_implicit_always}, {NULL, NULL, NULL} }; @@ -1314,6 +1327,11 @@ static struct riscv_supported_ext riscv_supported_std_ext[] = static struct riscv_supported_ext riscv_supported_std_z_ext[] = { + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1327,6 +1345,8 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -1406,17 +1426,30 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = static struct riscv_supported_ext riscv_supported_std_s_ext[] = { + {"shcounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shgatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shtvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvsatpa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"shvstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smcsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssaia", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssccptr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscsrind", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sscofpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sscounterenw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"ssstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"sstc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvala", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"sstvecd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ssu64xl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svade", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svadu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"svbare", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svinval", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svnapot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"svpbmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, diff --git a/gas/testsuite/gas/riscv/imply.d b/gas/testsuite/gas/riscv/imply.d index dee8890..0c726d3 100644 --- a/gas/testsuite/gas/riscv/imply.d +++ b/gas/testsuite/gas/riscv/imply.d @@ -44,6 +44,12 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zca1p0_zcd1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_f2p2_zicsr2p0_zca1p0_zcf1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zca1p0_zcmp1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shcounterenw1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shgatpa1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shtvala1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvsatpa1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvstvala1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0_shvstvecd1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_h1p0_zicsr2p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinx1p0_zhinxmin1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_zfinx1p0_zhinxmin1p0 @@ -76,7 +82,13 @@ SYMBOL TABLE: [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssaia1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscsrind1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscofpmf1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sscounterenw1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssstateen1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstc1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvala1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_sstvecd1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_ssu64xl1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svade1p0 [0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svadu1p0 +[0-9a-f]+ l .text 0+000 \$xrv32i2p1_zicsr2p0_svbare1p0 [0-9a-f]+ l d .riscv.attributes 0+000 .riscv.attributes diff --git a/gas/testsuite/gas/riscv/imply.s b/gas/testsuite/gas/riscv/imply.s index f341283..8eca66f 100644 --- a/gas/testsuite/gas/riscv/imply.s +++ b/gas/testsuite/gas/riscv/imply.s @@ -48,6 +48,12 @@ imply zcd imply zcf imply zcmp +imply shcounterenw +imply shgatpa +imply shtvala +imply shvsatpa +imply shvstvala +imply shvstvecd imply h imply zhinx imply zhinxmin @@ -86,6 +92,13 @@ imply smepmp imply ssaia imply sscsrind imply sscofpmf +imply sscounterenw imply ssstateen imply sstc +imply sstvala +imply sstvecd +imply ssu64xl + +imply svade imply svadu +imply svbare diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l index c33d856..97521c7 100644 --- a/gas/testsuite/gas/riscv/march-help.l +++ b/gas/testsuite/gas/riscv/march-help.l @@ -10,6 +10,11 @@ All available -march extensions for RISC-V: b 1.0 v 1.0 h 1.0 + zic64b 1.0 + ziccamoa 1.0 + ziccif 1.0 + zicclsm 1.0 + ziccrse 1.0 zicbom 1.0 zicbop 1.0 zicboz 1.0 @@ -21,6 +26,8 @@ All available -march extensions for RISC-V: zihintpause 2.0 zihpm 2.0 zmmul 1.0 + za64rs 1.0 + za128rs 1.0 zaamo 1.0 zabha 1.0 zacas 1.0 @@ -95,17 +102,30 @@ All available -march extensions for RISC-V: zcf 1.0 zcd 1.0 zcmp 1.0 + shcounterenw 1.0 + shgatpa 1.0 + shtvala 1.0 + shvsatpa 1.0 + shvstvala 1.0 + shvstvecd 1.0 smaia 1.0 smcsrind 1.0 smcntrpmf 1.0 smepmp 1.0 smstateen 1.0 ssaia 1.0 + ssccptr 1.0 sscsrind 1.0 sscofpmf 1.0 + sscounterenw 1.0 ssstateen 1.0 sstc 1.0 + sstvala 1.0 + sstvecd 1.0 + ssu64xl 1.0 + svade 1.0 svadu 1.0 + svbare 1.0 svinval 1.0 svnapot 1.0 svpbmt 1.0 |