diff options
-rw-r--r-- | sim/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | sim/testsuite/Makefile.in | 1 | ||||
-rw-r--r-- | sim/testsuite/aarch64/ChangeLog (renamed from sim/testsuite/sim/aarch64/ChangeLog) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/adds.s (renamed from sim/testsuite/sim/aarch64/adds.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/addv.s (renamed from sim/testsuite/sim/aarch64/addv.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/allinsn.exp (renamed from sim/testsuite/sim/aarch64/allinsn.exp) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/bit.s (renamed from sim/testsuite/sim/aarch64/bit.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/cmtst.s (renamed from sim/testsuite/sim/aarch64/cmtst.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/cnt.s (renamed from sim/testsuite/sim/aarch64/cnt.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fcmXX.s (renamed from sim/testsuite/sim/aarch64/fcmXX.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fcmp.s (renamed from sim/testsuite/sim/aarch64/fcmp.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fcsel.s (renamed from sim/testsuite/sim/aarch64/fcsel.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fcvtl.s (renamed from sim/testsuite/sim/aarch64/fcvtl.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fcvtz.s (renamed from sim/testsuite/sim/aarch64/fcvtz.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fminnm.s (renamed from sim/testsuite/sim/aarch64/fminnm.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/fstur.s (renamed from sim/testsuite/sim/aarch64/fstur.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/ldn_multiple.s (renamed from sim/testsuite/sim/aarch64/ldn_multiple.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/ldn_single.s (renamed from sim/testsuite/sim/aarch64/ldn_single.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/ldnr.s (renamed from sim/testsuite/sim/aarch64/ldnr.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/mla.s (renamed from sim/testsuite/sim/aarch64/mla.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/mls.s (renamed from sim/testsuite/sim/aarch64/mls.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/mul.s (renamed from sim/testsuite/sim/aarch64/mul.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/pass.s (renamed from sim/testsuite/sim/aarch64/pass.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/stn_multiple.s (renamed from sim/testsuite/sim/aarch64/stn_multiple.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/stn_single.s (renamed from sim/testsuite/sim/aarch64/stn_single.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/sumov.s (renamed from sim/testsuite/sim/aarch64/sumov.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/sumulh.s (renamed from sim/testsuite/sim/aarch64/sumulh.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/tbnz.s (renamed from sim/testsuite/sim/aarch64/tbnz.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/testutils.inc (renamed from sim/testsuite/sim/aarch64/testutils.inc) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/uzp.s (renamed from sim/testsuite/sim/aarch64/uzp.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/xtl.s (renamed from sim/testsuite/sim/aarch64/xtl.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/aarch64/xtn.s (renamed from sim/testsuite/sim/aarch64/xtn.s) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ChangeLog (renamed from sim/testsuite/sim/arm/ChangeLog) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/adc.cgs (renamed from sim/testsuite/sim/arm/adc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/add.cgs (renamed from sim/testsuite/sim/arm/add.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/allinsn.exp (renamed from sim/testsuite/sim/arm/allinsn.exp) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/and.cgs (renamed from sim/testsuite/sim/arm/and.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/b.cgs (renamed from sim/testsuite/sim/arm/b.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/bic.cgs (renamed from sim/testsuite/sim/arm/bic.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/bl.cgs (renamed from sim/testsuite/sim/arm/bl.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/bx.cgs (renamed from sim/testsuite/sim/arm/bx.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/cmn.cgs (renamed from sim/testsuite/sim/arm/cmn.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/cmp.cgs (renamed from sim/testsuite/sim/arm/cmp.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/eor.cgs (renamed from sim/testsuite/sim/arm/eor.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/hello.ms (renamed from sim/testsuite/sim/arm/hello.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/iwmmxt.exp (renamed from sim/testsuite/sim/arm/iwmmxt/iwmmxt.exp) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/tbcst.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/tbcst.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/testutils.inc (renamed from sim/testsuite/sim/arm/iwmmxt/testutils.inc) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/textrm.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/textrm.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/tinsr.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/tinsr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/tmia.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/tmia.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/tmiaph.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/tmiaph.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/tmiaxy.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/tmiaxy.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/tmovmsk.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/tmovmsk.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wacc.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wacc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wadd.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wadd.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/waligni.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/waligni.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/walignr.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/walignr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wand.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wand.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wandn.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wandn.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wavg2.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wavg2.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wcmpeq.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wcmpeq.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wcmpgt.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wcmpgt.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wmac.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wmac.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wmadd.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wmadd.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wmax.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wmax.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wmin.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wmin.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wmov.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wmov.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wmul.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wmul.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wor.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wor.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wpack.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wpack.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wror.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wror.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wsad.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wsad.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wshufh.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wshufh.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wsll.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wsll.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wsra.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wsra.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wsrl.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wsrl.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wsub.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wsub.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wunpckeh.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wunpckeh.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wunpckel.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wunpckel.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wunpckih.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wunpckih.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wunpckil.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wunpckil.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wxor.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wxor.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/iwmmxt/wzero.cgs (renamed from sim/testsuite/sim/arm/iwmmxt/wzero.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ldm.cgs (renamed from sim/testsuite/sim/arm/ldm.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ldr.cgs (renamed from sim/testsuite/sim/arm/ldr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ldrb.cgs (renamed from sim/testsuite/sim/arm/ldrb.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ldrh.cgs (renamed from sim/testsuite/sim/arm/ldrh.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ldrsb.cgs (renamed from sim/testsuite/sim/arm/ldrsb.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/ldrsh.cgs (renamed from sim/testsuite/sim/arm/ldrsh.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/misaligned1.ms (renamed from sim/testsuite/sim/arm/misaligned1.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/misaligned2.ms (renamed from sim/testsuite/sim/arm/misaligned2.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/misaligned3.ms (renamed from sim/testsuite/sim/arm/misaligned3.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/misc.exp (renamed from sim/testsuite/sim/arm/misc.exp) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/mla.cgs (renamed from sim/testsuite/sim/arm/mla.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/mov.cgs (renamed from sim/testsuite/sim/arm/mov.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/movw-movt.ms (renamed from sim/testsuite/sim/arm/movw-movt.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/mrs.cgs (renamed from sim/testsuite/sim/arm/mrs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/msr.cgs (renamed from sim/testsuite/sim/arm/msr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/mul.cgs (renamed from sim/testsuite/sim/arm/mul.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/mvn.cgs (renamed from sim/testsuite/sim/arm/mvn.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/orr.cgs (renamed from sim/testsuite/sim/arm/orr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/rsb.cgs (renamed from sim/testsuite/sim/arm/rsb.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/rsc.cgs (renamed from sim/testsuite/sim/arm/rsc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/sbc.cgs (renamed from sim/testsuite/sim/arm/sbc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/smlal.cgs (renamed from sim/testsuite/sim/arm/smlal.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/smull.cgs (renamed from sim/testsuite/sim/arm/smull.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/stm.cgs (renamed from sim/testsuite/sim/arm/stm.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/str.cgs (renamed from sim/testsuite/sim/arm/str.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/strb.cgs (renamed from sim/testsuite/sim/arm/strb.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/strh.cgs (renamed from sim/testsuite/sim/arm/strh.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/sub.cgs (renamed from sim/testsuite/sim/arm/sub.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/swi.cgs (renamed from sim/testsuite/sim/arm/swi.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/swp.cgs (renamed from sim/testsuite/sim/arm/swp.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/swpb.cgs (renamed from sim/testsuite/sim/arm/swpb.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/teq.cgs (renamed from sim/testsuite/sim/arm/teq.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/testutils.inc (renamed from sim/testsuite/sim/arm/testutils.inc) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/adc.cgs (renamed from sim/testsuite/sim/arm/thumb/adc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/add-hd-hs.cgs (renamed from sim/testsuite/sim/arm/thumb/add-hd-hs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/add-hd-rs.cgs (renamed from sim/testsuite/sim/arm/thumb/add-hd-rs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/add-rd-hs.cgs (renamed from sim/testsuite/sim/arm/thumb/add-rd-hs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/add-sp.cgs (renamed from sim/testsuite/sim/arm/thumb/add-sp.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/add.cgs (renamed from sim/testsuite/sim/arm/thumb/add.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/addi.cgs (renamed from sim/testsuite/sim/arm/thumb/addi.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/addi8.cgs (renamed from sim/testsuite/sim/arm/thumb/addi8.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/allthumb.exp (renamed from sim/testsuite/sim/arm/thumb/allthumb.exp) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/and.cgs (renamed from sim/testsuite/sim/arm/thumb/and.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/asr.cgs (renamed from sim/testsuite/sim/arm/thumb/asr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/b.cgs (renamed from sim/testsuite/sim/arm/thumb/b.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bcc.cgs (renamed from sim/testsuite/sim/arm/thumb/bcc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bcs.cgs (renamed from sim/testsuite/sim/arm/thumb/bcs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/beq.cgs (renamed from sim/testsuite/sim/arm/thumb/beq.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bge.cgs (renamed from sim/testsuite/sim/arm/thumb/bge.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bgt.cgs (renamed from sim/testsuite/sim/arm/thumb/bgt.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bhi.cgs (renamed from sim/testsuite/sim/arm/thumb/bhi.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bic.cgs (renamed from sim/testsuite/sim/arm/thumb/bic.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bl-hi.cgs (renamed from sim/testsuite/sim/arm/thumb/bl-hi.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bl-lo.cgs (renamed from sim/testsuite/sim/arm/thumb/bl-lo.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ble.cgs (renamed from sim/testsuite/sim/arm/thumb/ble.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bls.cgs (renamed from sim/testsuite/sim/arm/thumb/bls.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/blt.cgs (renamed from sim/testsuite/sim/arm/thumb/blt.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bmi.cgs (renamed from sim/testsuite/sim/arm/thumb/bmi.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bne.cgs (renamed from sim/testsuite/sim/arm/thumb/bne.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bpl.cgs (renamed from sim/testsuite/sim/arm/thumb/bpl.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bvc.cgs (renamed from sim/testsuite/sim/arm/thumb/bvc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bvs.cgs (renamed from sim/testsuite/sim/arm/thumb/bvs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bx-hs.cgs (renamed from sim/testsuite/sim/arm/thumb/bx-hs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/bx-rs.cgs (renamed from sim/testsuite/sim/arm/thumb/bx-rs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/cmn.cgs (renamed from sim/testsuite/sim/arm/thumb/cmn.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/cmp-hd-hs.cgs (renamed from sim/testsuite/sim/arm/thumb/cmp-hd-hs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/cmp-hd-rs.cgs (renamed from sim/testsuite/sim/arm/thumb/cmp-hd-rs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/cmp-rd-hs.cgs (renamed from sim/testsuite/sim/arm/thumb/cmp-rd-hs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/cmp.cgs (renamed from sim/testsuite/sim/arm/thumb/cmp.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/eor.cgs (renamed from sim/testsuite/sim/arm/thumb/eor.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/lda-pc.cgs (renamed from sim/testsuite/sim/arm/thumb/lda-pc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/lda-sp.cgs (renamed from sim/testsuite/sim/arm/thumb/lda-sp.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldmia.cgs (renamed from sim/testsuite/sim/arm/thumb/ldmia.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldr-imm.cgs (renamed from sim/testsuite/sim/arm/thumb/ldr-imm.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldr-pc.cgs (renamed from sim/testsuite/sim/arm/thumb/ldr-pc.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldr-sprel.cgs (renamed from sim/testsuite/sim/arm/thumb/ldr-sprel.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldr.cgs (renamed from sim/testsuite/sim/arm/thumb/ldr.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldrb-imm.cgs (renamed from sim/testsuite/sim/arm/thumb/ldrb-imm.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/arm/thumb/ldrb.cgs (renamed from sim/testsuite/sim/arm/thumb/ldrb.cgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/bfin/c_dsp32alu_r_negneg.s (renamed from sim/testsuite/sim/bfin/c_dsp32alu_r_negneg.s) | 0 | ||||
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-rw-r--r-- | sim/testsuite/bfin/c_loopsetup_preg_div2_lc0.s (renamed from sim/testsuite/sim/bfin/c_loopsetup_preg_div2_lc0.s) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/grloop.ms (renamed from sim/testsuite/sim/frv/grloop.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/hello.ms (renamed from sim/testsuite/sim/frv/hello.ms) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/icei.cgs (renamed from sim/testsuite/sim/frv/icei.cgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/interrupts/Ipipe-fr400.cgs (renamed from sim/testsuite/sim/frv/interrupts/Ipipe-fr400.cgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/interrupts/compound.cgs (renamed from sim/testsuite/sim/frv/interrupts/compound.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/data_store_error-fr550.cgs (renamed from sim/testsuite/sim/frv/interrupts/data_store_error-fr550.cgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/interrupts/fp_exception-fr550.cgs (renamed from sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/fp_exception.cgs (renamed from sim/testsuite/sim/frv/interrupts/fp_exception.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/illinsn.cgs (renamed from sim/testsuite/sim/frv/interrupts/illinsn.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/insn_access_error-fr550.cgs (renamed from sim/testsuite/sim/frv/interrupts/insn_access_error-fr550.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/insn_access_error.cgs (renamed from sim/testsuite/sim/frv/interrupts/insn_access_error.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/mp_exception.cgs (renamed from sim/testsuite/sim/frv/interrupts/mp_exception.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/privileged_instruction.cgs (renamed from sim/testsuite/sim/frv/interrupts/privileged_instruction.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/regalign.cgs (renamed from sim/testsuite/sim/frv/interrupts/regalign.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/reset.cgs (renamed from sim/testsuite/sim/frv/interrupts/reset.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/shadow_regs.cgs (renamed from sim/testsuite/sim/frv/interrupts/shadow_regs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/interrupts/timer.cgs (renamed from sim/testsuite/sim/frv/interrupts/timer.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/jmpil.cgs (renamed from sim/testsuite/sim/frv/jmpil.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/jmpl.cgs (renamed from sim/testsuite/sim/frv/jmpl.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/jmpl.pcgs (renamed from sim/testsuite/sim/frv/jmpl.pcgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/mdpackh.cgs (renamed from sim/testsuite/sim/frv/mdpackh.cgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/misc.exp (renamed from sim/testsuite/sim/frv/misc.exp) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mmachs.cgs (renamed from sim/testsuite/sim/frv/mmachs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mmachu.cgs (renamed from sim/testsuite/sim/frv/mmachu.cgs) | 0 | ||||
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-rw-r--r-- | sim/testsuite/frv/mpackh.cgs (renamed from sim/testsuite/sim/frv/mpackh.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqcpxis.cgs (renamed from sim/testsuite/sim/frv/mqcpxis.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqcpxiu.cgs (renamed from sim/testsuite/sim/frv/mqcpxiu.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqcpxrs.cgs (renamed from sim/testsuite/sim/frv/mqcpxrs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqcpxru.cgs (renamed from sim/testsuite/sim/frv/mqcpxru.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqlclrhs.cgs (renamed from sim/testsuite/sim/frv/mqlclrhs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqlmths.cgs (renamed from sim/testsuite/sim/frv/mqlmths.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqmachs.cgs (renamed from sim/testsuite/sim/frv/mqmachs.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqmachu.cgs (renamed from sim/testsuite/sim/frv/mqmachu.cgs) | 0 | ||||
-rw-r--r-- | sim/testsuite/frv/mqmacxhs.cgs (renamed from sim/testsuite/sim/frv/mqmacxhs.cgs) | 0 | ||||
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2860 files changed, 5 insertions, 1 deletions
diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog index fc5806e..4271705 100644 --- a/sim/testsuite/ChangeLog +++ b/sim/testsuite/ChangeLog @@ -1,5 +1,10 @@ 2021-01-15 Mike Frysinger <vapier@gentoo.org> + * Makefile.in (site.exp): Delete tool setting. + * sim/*/: Move subdirs up a directory. + +2021-01-15 Mike Frysinger <vapier@gentoo.org> + * configure, configure.ac: Delete. * Makefile.in (Makefile, config.status): Switch to ../config.status. diff --git a/sim/testsuite/Makefile.in b/sim/testsuite/Makefile.in index 1f75db6..1e4604c 100644 --- a/sim/testsuite/Makefile.in +++ b/sim/testsuite/Makefile.in @@ -127,7 +127,6 @@ site.exp: Makefile @echo '## these variables are automatically generated by make ##' > $@-t @echo '# Do not edit here. If you wish to override these values' >> $@-t @echo '# edit the last section' >> $@-t - @echo 'set tool sim' >> $@-t @echo 'set srcdir $(srcdir)' >> $@-t @echo 'set objdir' `pwd` >> $@-t @echo 'set arch $(arch)' >> $@-t diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/aarch64/ChangeLog index f4671da..f4671da 100644 --- a/sim/testsuite/sim/aarch64/ChangeLog +++ b/sim/testsuite/aarch64/ChangeLog diff --git a/sim/testsuite/sim/aarch64/adds.s b/sim/testsuite/aarch64/adds.s index fdea5a7..fdea5a7 100644 --- a/sim/testsuite/sim/aarch64/adds.s +++ b/sim/testsuite/aarch64/adds.s diff --git a/sim/testsuite/sim/aarch64/addv.s b/sim/testsuite/aarch64/addv.s index 4da8935..4da8935 100644 --- a/sim/testsuite/sim/aarch64/addv.s +++ b/sim/testsuite/aarch64/addv.s diff --git a/sim/testsuite/sim/aarch64/allinsn.exp b/sim/testsuite/aarch64/allinsn.exp index 54d6478..54d6478 100644 --- a/sim/testsuite/sim/aarch64/allinsn.exp +++ b/sim/testsuite/aarch64/allinsn.exp diff --git a/sim/testsuite/sim/aarch64/bit.s b/sim/testsuite/aarch64/bit.s index 01a1d4e..01a1d4e 100644 --- a/sim/testsuite/sim/aarch64/bit.s +++ b/sim/testsuite/aarch64/bit.s diff --git a/sim/testsuite/sim/aarch64/cmtst.s b/sim/testsuite/aarch64/cmtst.s index 7e6a4c3..7e6a4c3 100644 --- a/sim/testsuite/sim/aarch64/cmtst.s +++ b/sim/testsuite/aarch64/cmtst.s diff --git a/sim/testsuite/sim/aarch64/cnt.s b/sim/testsuite/aarch64/cnt.s index b4be2e3..b4be2e3 100644 --- a/sim/testsuite/sim/aarch64/cnt.s +++ b/sim/testsuite/aarch64/cnt.s diff --git a/sim/testsuite/sim/aarch64/fcmXX.s b/sim/testsuite/aarch64/fcmXX.s index cc1a2a9..cc1a2a9 100644 --- a/sim/testsuite/sim/aarch64/fcmXX.s +++ b/sim/testsuite/aarch64/fcmXX.s diff --git a/sim/testsuite/sim/aarch64/fcmp.s b/sim/testsuite/aarch64/fcmp.s index fd826c4..fd826c4 100644 --- a/sim/testsuite/sim/aarch64/fcmp.s +++ b/sim/testsuite/aarch64/fcmp.s diff --git a/sim/testsuite/sim/aarch64/fcsel.s b/sim/testsuite/aarch64/fcsel.s index 5b8443c..5b8443c 100644 --- a/sim/testsuite/sim/aarch64/fcsel.s +++ b/sim/testsuite/aarch64/fcsel.s diff --git a/sim/testsuite/sim/aarch64/fcvtl.s b/sim/testsuite/aarch64/fcvtl.s index 8febc08..8febc08 100644 --- a/sim/testsuite/sim/aarch64/fcvtl.s +++ b/sim/testsuite/aarch64/fcvtl.s diff --git a/sim/testsuite/sim/aarch64/fcvtz.s b/sim/testsuite/aarch64/fcvtz.s index 311fc2e..311fc2e 100644 --- a/sim/testsuite/sim/aarch64/fcvtz.s +++ b/sim/testsuite/aarch64/fcvtz.s diff --git a/sim/testsuite/sim/aarch64/fminnm.s b/sim/testsuite/aarch64/fminnm.s index 43ccd7c..43ccd7c 100644 --- a/sim/testsuite/sim/aarch64/fminnm.s +++ b/sim/testsuite/aarch64/fminnm.s diff --git a/sim/testsuite/sim/aarch64/fstur.s b/sim/testsuite/aarch64/fstur.s index 80e5c67..80e5c67 100644 --- a/sim/testsuite/sim/aarch64/fstur.s +++ b/sim/testsuite/aarch64/fstur.s diff --git a/sim/testsuite/sim/aarch64/ldn_multiple.s b/sim/testsuite/aarch64/ldn_multiple.s index 285ef7e..285ef7e 100644 --- a/sim/testsuite/sim/aarch64/ldn_multiple.s +++ b/sim/testsuite/aarch64/ldn_multiple.s diff --git a/sim/testsuite/sim/aarch64/ldn_single.s b/sim/testsuite/aarch64/ldn_single.s index 9681520..9681520 100644 --- a/sim/testsuite/sim/aarch64/ldn_single.s +++ b/sim/testsuite/aarch64/ldn_single.s diff --git a/sim/testsuite/sim/aarch64/ldnr.s b/sim/testsuite/aarch64/ldnr.s index 7126c46..7126c46 100644 --- a/sim/testsuite/sim/aarch64/ldnr.s +++ b/sim/testsuite/aarch64/ldnr.s diff --git a/sim/testsuite/sim/aarch64/mla.s b/sim/testsuite/aarch64/mla.s index e3ea836..e3ea836 100644 --- a/sim/testsuite/sim/aarch64/mla.s +++ b/sim/testsuite/aarch64/mla.s diff --git a/sim/testsuite/sim/aarch64/mls.s b/sim/testsuite/aarch64/mls.s index 5c9e225..5c9e225 100644 --- a/sim/testsuite/sim/aarch64/mls.s +++ b/sim/testsuite/aarch64/mls.s diff --git a/sim/testsuite/sim/aarch64/mul.s b/sim/testsuite/aarch64/mul.s index 783dba7..783dba7 100644 --- a/sim/testsuite/sim/aarch64/mul.s +++ b/sim/testsuite/aarch64/mul.s diff --git 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b/sim/testsuite/bfin/c_progctrl_except_rtx.S index 9cacc28..9cacc28 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_except_rtx.S +++ b/sim/testsuite/bfin/c_progctrl_except_rtx.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_excpt.S b/sim/testsuite/bfin/c_progctrl_excpt.S index 625a5c0..625a5c0 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_excpt.S +++ b/sim/testsuite/bfin/c_progctrl_excpt.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s b/sim/testsuite/bfin/c_progctrl_jump_pcpr.s index 727025c..727025c 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_jump_pcpr.s +++ b/sim/testsuite/bfin/c_progctrl_jump_pcpr.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s b/sim/testsuite/bfin/c_progctrl_jump_pr.s index 8b77c31..8b77c31 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_jump_pr.s +++ b/sim/testsuite/bfin/c_progctrl_jump_pr.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_nop.s b/sim/testsuite/bfin/c_progctrl_nop.s index 77f744b..77f744b 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_nop.s +++ b/sim/testsuite/bfin/c_progctrl_nop.s diff --git a/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S b/sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S index 9444f5d..9444f5d 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_raise_rt_i_n.S +++ b/sim/testsuite/bfin/c_progctrl_raise_rt_i_n.S diff --git a/sim/testsuite/sim/bfin/c_progctrl_rts.s b/sim/testsuite/bfin/c_progctrl_rts.s index 3aa3bed..3aa3bed 100644 --- a/sim/testsuite/sim/bfin/c_progctrl_rts.s +++ b/sim/testsuite/bfin/c_progctrl_rts.s diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s b/sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s index 2d27849..2d27849 100644 --- a/sim/testsuite/sim/bfin/c_ptr2op_pr_neg_pr.s +++ b/sim/testsuite/bfin/c_ptr2op_pr_neg_pr.s diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s b/sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s index dabd216..dabd216 100644 --- a/sim/testsuite/sim/bfin/c_ptr2op_pr_sft_2_1.s +++ b/sim/testsuite/bfin/c_ptr2op_pr_sft_2_1.s diff --git a/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s b/sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s index dc6e2e8..dc6e2e8 100644 --- a/sim/testsuite/sim/bfin/c_ptr2op_pr_shadd_1_2.s +++ b/sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s b/sim/testsuite/bfin/c_pushpopmultiple_dp.s index 5d7de57..5d7de57 100644 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp.s +++ b/sim/testsuite/bfin/c_pushpopmultiple_dp.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s b/sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s index 78dae01..78dae01 100644 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_dp_pair.s +++ b/sim/testsuite/bfin/c_pushpopmultiple_dp_pair.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s b/sim/testsuite/bfin/c_pushpopmultiple_dreg.s index ca1ebf1..ca1ebf1 100644 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_dreg.s +++ b/sim/testsuite/bfin/c_pushpopmultiple_dreg.s diff --git a/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s b/sim/testsuite/bfin/c_pushpopmultiple_preg.s index 15c1937..15c1937 100644 --- a/sim/testsuite/sim/bfin/c_pushpopmultiple_preg.s +++ b/sim/testsuite/bfin/c_pushpopmultiple_preg.s diff --git a/sim/testsuite/sim/bfin/c_regmv_acc_acc.s b/sim/testsuite/bfin/c_regmv_acc_acc.s index 08e4414..08e4414 100644 --- a/sim/testsuite/sim/bfin/c_regmv_acc_acc.s +++ b/sim/testsuite/bfin/c_regmv_acc_acc.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s b/sim/testsuite/bfin/c_regmv_dag_lz_dep.s index fb95a73..fb95a73 100644 --- a/sim/testsuite/sim/bfin/c_regmv_dag_lz_dep.s +++ b/sim/testsuite/bfin/c_regmv_dag_lz_dep.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s b/sim/testsuite/bfin/c_regmv_dr_acc_acc.s index 6af3d04..6af3d04 100644 --- a/sim/testsuite/sim/bfin/c_regmv_dr_acc_acc.s +++ b/sim/testsuite/bfin/c_regmv_dr_acc_acc.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s b/sim/testsuite/bfin/c_regmv_dr_dep_nostall.s index 118274d..118274d 100644 --- a/sim/testsuite/sim/bfin/c_regmv_dr_dep_nostall.s +++ b/sim/testsuite/bfin/c_regmv_dr_dep_nostall.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_dr.s b/sim/testsuite/bfin/c_regmv_dr_dr.s index e1fb658..e1fb658 100644 --- a/sim/testsuite/sim/bfin/c_regmv_dr_dr.s +++ b/sim/testsuite/bfin/c_regmv_dr_dr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s b/sim/testsuite/bfin/c_regmv_dr_imlb.s index 01650b0..01650b0 100644 --- a/sim/testsuite/sim/bfin/c_regmv_dr_imlb.s +++ b/sim/testsuite/bfin/c_regmv_dr_imlb.s diff --git a/sim/testsuite/sim/bfin/c_regmv_dr_pr.s b/sim/testsuite/bfin/c_regmv_dr_pr.s index fd8967c..fd8967c 100644 --- a/sim/testsuite/sim/bfin/c_regmv_dr_pr.s +++ b/sim/testsuite/bfin/c_regmv_dr_pr.s diff --git a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s b/sim/testsuite/bfin/c_regmv_imlb_dep_nostall.s index cda1fb1..cda1fb1 100644 --- a/sim/testsuite/sim/bfin/c_regmv_imlb_dep_nostall.s +++ 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