diff options
| -rw-r--r-- | sim/mips/ChangeLog | 8 | ||||
| -rw-r--r-- | sim/mips/interp.c | 10 |
2 files changed, 17 insertions, 1 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog index 465f42c..c70e6f6 100644 --- a/sim/mips/ChangeLog +++ b/sim/mips/ChangeLog @@ -1,3 +1,11 @@ +1998-12-30 Frank Ch. Eigler <fche@cygnus.com> + + * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. +start-sanitize-sky + * interp.c (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook. + Call sim_engine_halt on BreakPoint. +end-sanitize-sky + Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> * configure.in, configure (mips64vr5*-*-*): Added missing ;; in diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 4a666d3..811307f 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -1941,6 +1941,11 @@ signal_exception (SIM_DESC sd, /* Ensure that any active atomic read/modify/write operation will fail: */ LLBIT = 0; + /* Save registers before interrupt dispatching */ +#ifdef SIM_CPU_EXCEPTION_TRIGGER + SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia); +#endif + /* First, handle any simulator specific magic exceptions. These are not "real" exceptions, but are exceptions which the simulator uses to implement different features. */ @@ -2144,10 +2149,13 @@ signal_exception (SIM_DESC sd, sim_stopped, SIM_SIGFPE); break; + case BreakPoint: + sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP); + break; + case TLBModification: case TLBLoad: case TLBStore: - case BreakPoint: case SystemCall: case Trap: sim_engine_restart (SD, CPU, NULL, PC); |