diff options
| -rw-r--r-- | binutils/NEWS | 3 | ||||
| -rw-r--r-- | opcodes/riscv-dis.c | 8 |
2 files changed, 10 insertions, 1 deletions
diff --git a/binutils/NEWS b/binutils/NEWS index 50c40af..92cc950 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,8 @@ -*- text -*- +* RISC-V disassembly now supports -M,max option like QEMU to dump instruction + without checking architecture support as usual. + Changes in 2.43: * The MIPS port now supports microMIPS MT Application Specific Extension diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 551d57e..80018db 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -80,6 +80,9 @@ static const char (*riscv_fpr_names)[NRC]; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; +/* If set, disassemble without checking architectire string, just like what + we did at the beginning. */ +static bool all_ext = false; /* Set default RISC-V disassembler options. */ @@ -103,6 +106,8 @@ parse_riscv_dis_option_without_args (const char *option) riscv_gpr_names = riscv_gpr_names_numeric; riscv_fpr_names = riscv_fpr_names_numeric; } + else if (strcmp (option, "max") == 0) + all_ext = true; else return false; return true; @@ -968,7 +973,8 @@ riscv_disassemble_insn (bfd_vma memaddr, if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) continue; /* Is this instruction supported by the current architecture? */ - if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) + if (!all_ext + && !riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) continue; /* It's a match. */ |