aboutsummaryrefslogtreecommitdiff
path: root/sim
diff options
context:
space:
mode:
authorChris Demetriou <cgd@google.com>2002-06-03 22:30:52 +0000
committerChris Demetriou <cgd@google.com>2002-06-03 22:30:52 +0000
commite80fc1523d15f2ff344ab9ef6798765dab9ca0db (patch)
tree874033c1785d2f5e88e00923f3933bb7b5c2510c /sim
parentbad673a9cb51c25370660c88887d0ad3b34b007b (diff)
downloadgdb-e80fc1523d15f2ff344ab9ef6798765dab9ca0db.zip
gdb-e80fc1523d15f2ff344ab9ef6798765dab9ca0db.tar.gz
gdb-e80fc1523d15f2ff344ab9ef6798765dab9ca0db.tar.bz2
2002-06-03 Chris Demetriou <cgd@broadcom.com>
* cp1.c: fix formatting of switch case and default labels. * interp.c: Likewise. * sim-main.c: Likewise.
Diffstat (limited to 'sim')
-rw-r--r--sim/mips/ChangeLog6
-rw-r--r--sim/mips/cp1.c22
-rw-r--r--sim/mips/interp.c10
-rw-r--r--sim/mips/sim-main.c36
4 files changed, 40 insertions, 34 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index d3408fc..ecdecf4 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,5 +1,11 @@
2002-06-03 Chris Demetriou <cgd@broadcom.com>
+ * cp1.c: fix formatting of switch case and default labels.
+ * interp.c: Likewise.
+ * sim-main.c: Likewise.
+
+2002-06-03 Chris Demetriou <cgd@broadcom.com>
+
* cp1.c: Clean up comments which describe FP formats.
(FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
diff --git a/sim/mips/cp1.c b/sim/mips/cp1.c
index 3b1cac2..c6476a3 100644
--- a/sim/mips/cp1.c
+++ b/sim/mips/cp1.c
@@ -176,7 +176,7 @@ value_fpr (SIM_DESC sd,
}
break;
- default :
+ default:
err = -1;
break;
}
@@ -216,8 +216,8 @@ store_fpr (SIM_DESC sd,
{
case fmt_uninterpreted_32:
fmt = fmt_uninterpreted;
- case fmt_single :
- case fmt_word :
+ case fmt_single:
+ case fmt_word:
if (STATE_VERBOSE_P (SD))
sim_io_eprintf (SD,
"Warning: PC 0x%s: interp.c store_fpr DEADCODE\n",
@@ -229,13 +229,13 @@ store_fpr (SIM_DESC sd,
case fmt_uninterpreted_64:
fmt = fmt_uninterpreted;
case fmt_uninterpreted:
- case fmt_double :
- case fmt_long :
+ case fmt_double:
+ case fmt_long:
FGR[fpr] = value;
FPR_STATE[fpr] = fmt;
break;
- default :
+ default:
FPR_STATE[fpr] = fmt_unknown;
err = -1;
break;
@@ -247,8 +247,8 @@ store_fpr (SIM_DESC sd,
{
case fmt_uninterpreted_32:
fmt = fmt_uninterpreted;
- case fmt_single :
- case fmt_word :
+ case fmt_single:
+ case fmt_word:
FGR[fpr] = (value & 0xFFFFFFFF);
FPR_STATE[fpr] = fmt;
break;
@@ -256,8 +256,8 @@ store_fpr (SIM_DESC sd,
case fmt_uninterpreted_64:
fmt = fmt_uninterpreted;
case fmt_uninterpreted:
- case fmt_double :
- case fmt_long :
+ case fmt_double:
+ case fmt_long:
if ((fpr & 1) == 0)
{
/* even register number only */
@@ -274,7 +274,7 @@ store_fpr (SIM_DESC sd,
}
break;
- default :
+ default:
FPR_STATE[fpr] = fmt_unknown;
err = -1;
break;
diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 805f72a..35016e3 100644
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -1223,7 +1223,7 @@ sim_monitor (SIM_DESC sd,
break;
}
- case 28 : /* PMON flush_cache */
+ case 28: /* PMON flush_cache */
break;
case 55: /* void get_mem_info(unsigned int *ptr) */
@@ -1242,7 +1242,7 @@ sim_monitor (SIM_DESC sd,
break;
}
- case 158 : /* PMON printf */
+ case 158: /* PMON printf */
/* in: A0 = pointer to format string */
/* A1 = optional argument 1 */
/* A2 = optional argument 2 */
@@ -1671,7 +1671,7 @@ signal_exception (SIM_DESC sd,
switch (exception) {
- case DebugBreakPoint :
+ case DebugBreakPoint:
if (! (Debug & Debug_DM))
{
if (INDELAYSLOT())
@@ -1694,7 +1694,7 @@ signal_exception (SIM_DESC sd,
}
break;
- case ReservedInstruction :
+ case ReservedInstruction:
{
va_list ap;
unsigned int instruction;
@@ -1845,7 +1845,7 @@ signal_exception (SIM_DESC sd,
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGTRAP);
- default : /* Unknown internal exception */
+ default: /* Unknown internal exception */
PC = EPC;
sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGABRT);
diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c
index 7b3e6c6..edee498 100644
--- a/sim/mips/sim-main.c
+++ b/sim/mips/sim-main.c
@@ -163,35 +163,35 @@ load_memory (SIM_DESC SD,
switch (AccessLength)
{
- case AccessLength_QUADWORD :
+ case AccessLength_QUADWORD:
{
unsigned_16 val = sim_core_read_aligned_16 (CPU, cia, read_map, pAddr);
value1 = VH8_16 (val);
value = VL8_16 (val);
break;
}
- case AccessLength_DOUBLEWORD :
+ case AccessLength_DOUBLEWORD:
value = sim_core_read_aligned_8 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_SEPTIBYTE :
+ case AccessLength_SEPTIBYTE:
value = sim_core_read_misaligned_7 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_SEXTIBYTE :
+ case AccessLength_SEXTIBYTE:
value = sim_core_read_misaligned_6 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_QUINTIBYTE :
+ case AccessLength_QUINTIBYTE:
value = sim_core_read_misaligned_5 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_WORD :
+ case AccessLength_WORD:
value = sim_core_read_aligned_4 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_TRIPLEBYTE :
+ case AccessLength_TRIPLEBYTE:
value = sim_core_read_misaligned_3 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_HALFWORD :
+ case AccessLength_HALFWORD:
value = sim_core_read_aligned_2 (CPU, cia, read_map, pAddr);
break;
- case AccessLength_BYTE :
+ case AccessLength_BYTE:
value = sim_core_read_aligned_1 (CPU, cia, read_map, pAddr);
break;
default:
@@ -292,34 +292,34 @@ store_memory (SIM_DESC SD,
switch (AccessLength)
{
- case AccessLength_QUADWORD :
+ case AccessLength_QUADWORD:
{
unsigned_16 val = U16_8 (MemElem1, MemElem);
sim_core_write_aligned_16 (CPU, cia, write_map, pAddr, val);
break;
}
- case AccessLength_DOUBLEWORD :
+ case AccessLength_DOUBLEWORD:
sim_core_write_aligned_8 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_SEPTIBYTE :
+ case AccessLength_SEPTIBYTE:
sim_core_write_misaligned_7 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_SEXTIBYTE :
+ case AccessLength_SEXTIBYTE:
sim_core_write_misaligned_6 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_QUINTIBYTE :
+ case AccessLength_QUINTIBYTE:
sim_core_write_misaligned_5 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_WORD :
+ case AccessLength_WORD:
sim_core_write_aligned_4 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_TRIPLEBYTE :
+ case AccessLength_TRIPLEBYTE:
sim_core_write_misaligned_3 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_HALFWORD :
+ case AccessLength_HALFWORD:
sim_core_write_aligned_2 (CPU, cia, write_map, pAddr, MemElem);
break;
- case AccessLength_BYTE :
+ case AccessLength_BYTE:
sim_core_write_aligned_1 (CPU, cia, write_map, pAddr, MemElem);
break;
default: