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| author | Mike Frysinger <vapier@gentoo.org> | 2011-04-15 01:21:21 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-04-15 01:21:21 +0000 |
| commit | d2cfa400a11c869dd79f945fca68d62fdb85dd32 (patch) | |
| tree | 5b1f5a1c37647bbff50fbc2275da84e8640b5760 /sim | |
| parent | 96d1f342aa41a54b1a6b78b1e64d374e911ee7e0 (diff) | |
| download | gdb-d2cfa400a11c869dd79f945fca68d62fdb85dd32.zip gdb-d2cfa400a11c869dd79f945fca68d62fdb85dd32.tar.gz gdb-d2cfa400a11c869dd79f945fca68d62fdb85dd32.tar.bz2 | |
sim: bfin: handle implicit DISALGNEXCPT with video insns
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.
Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/bfin/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/bfin/bfin-sim.c | 24 |
2 files changed, 30 insertions, 0 deletions
diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog index d20ae6b..7bbd15e 100644 --- a/sim/bfin/ChangeLog +++ b/sim/bfin/ChangeLog @@ -1,3 +1,9 @@ +2011-04-14 Mike Frysinger <vapier@gentoo.org> + + * bfin-sim.c (decode_dsp32alu_0): Set DIS_ALGN_EXPT when handling + BYTEOP2P, BYTEOP3P, SAA, BYTEOP1P, BYTEOP16P, BYTEOP16M, BYTEPACK, + and BYTEUNPACK insns. + 2011-04-11 Mike Frysinger <vapier@gentoo.org> * dv-bfin_sic.c (bfin_sic_port_event): New helper function. diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 27112c6..f1500b0 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4214,6 +4214,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) tmp1 = ((((s1 >> 24) & 0xff) + ((s1 >> 16) & 0xff) + ((s0 >> 24) & 0xff) + ((s0 >> 16) & 0xff) + i) >> 2) & 0xff; SET_DREG (dst0, (tmp1 << (16 + (HL * 8))) | (tmp0 << (HL * 8))); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if ((aop == 0 || aop == 1) && s == 0 && aopcde == 8) { @@ -4330,6 +4333,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) tmp1 = (bs32)(bs16)(s0 >> 16) + ((s1 >> (16 + (8 * !HL))) & 0xff); SET_DREG (dst0, (CLAMP (tmp0, 0, 255) << ( 0 + (8 * HL))) | (CLAMP (tmp1, 0, 255) << (16 + (8 * HL)))); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if ((aop == 0 || aop == 1) && aopcde == 16) { @@ -4779,6 +4785,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) STORE (AXREG (0), 0); STORE (AWREG (1), (s1H << 16) | (s1L & 0xFFFF)); STORE (AXREG (1), 0); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if (aop == 3 && aopcde == 18) { @@ -4813,6 +4822,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) (((((s0 >> 8) & 0xff) + ((s1 >> 8) & 0xff) + !aop) >> 1) << 8) | (((((s0 >> 16) & 0xff) + ((s1 >> 16) & 0xff) + !aop) >> 1) << 16) | (((((s0 >> 24) & 0xff) + ((s1 >> 24) & 0xff) + !aop) >> 1) << 24)); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if (aop == 0 && aopcde == 21) { @@ -4845,6 +4857,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) SET_DREG (dst1, ((((s0 >> 16) & 0xff) + ((s1 >> 16) & 0xff)) << 0) | ((((s0 >> 24) & 0xff) + ((s1 >> 24) & 0xff)) << 16)); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if (aop == 1 && aopcde == 21) { @@ -4877,6 +4892,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) SET_DREG (dst1, (((((s0 >> 16) & 0xff) - ((s1 >> 16) & 0xff)) << 0) & 0xffff) | (((((s0 >> 24) & 0xff) - ((s1 >> 24) & 0xff)) << 16))); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if (aop == 1 && aopcde == 7) { @@ -4973,6 +4991,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) (((DREG (src0) >> 16) & 0xff) << 8) | (((DREG (src1) >> 0) & 0xff) << 16) | (((DREG (src1) >> 16) & 0xff) << 24)); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if (aop == 1 && aopcde == 24) { @@ -4998,6 +5019,9 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) byted = (comb_src >> (24 + 8 * order)); SET_DREG (dst0, bytea | ((bu32)byteb << 16)); SET_DREG (dst1, bytec | ((bu32)byted << 16)); + + /* Implicit DISALGNEXCPT in parallel. */ + DIS_ALGN_EXPT |= 1; } else if (aopcde == 13) { |