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authorReuben Thomas <rrt@sc3d.org>2022-03-24 12:05:21 +0000
committerSimon Marchi <simon.marchi@efficios.com>2022-03-24 10:34:51 -0400
commitc41524681bf2dad22390fe2b1cfbdeac1576e1e5 (patch)
treefba248f858280ed0b4acadaeb0ab93e3c71a23e3 /sim
parentf1a45585865a724d83133a2299768b5953d2ed94 (diff)
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sim: fix “alligned” typos
Change-Id: Ifd574e38524dd4f1cf0fc003e0c5c7499abc84a0
Diffstat (limited to 'sim')
-rw-r--r--sim/common/sim-core.h4
-rw-r--r--sim/ppc/hw_init.c2
-rw-r--r--sim/ppc/std-config.h2
3 files changed, 4 insertions, 4 deletions
diff --git a/sim/common/sim-core.h b/sim/common/sim-core.h
index 5f152ee..df4e3e1 100644
--- a/sim/common/sim-core.h
+++ b/sim/common/sim-core.h
@@ -248,7 +248,7 @@ extern void *sim_core_trans_addr
order (including xor endian). Should the transfer fail, the
operation shall abort (no return).
- ALIGNED assumes yhat the specified ADDRESS is correctly alligned
+ ALIGNED assumes that the specified ADDRESS is correctly aligned
for an N byte transfer (no alignment checks are made). Passing an
incorrectly aligned ADDRESS is erroneous.
@@ -256,7 +256,7 @@ extern void *sim_core_trans_addr
of an N byte transfer. Action, as defined by WITH_ALIGNMENT, being
taken should the check fail.
- MISSALIGNED transfers the data regardless.
+ MISALIGNED transfers the data regardless.
Misaligned xor-endian accesses are broken into a sequence of
transfers each <= WITH_XOR_ENDIAN bytes */
diff --git a/sim/ppc/hw_init.c b/sim/ppc/hw_init.c
index 3d58833..66f2058 100644
--- a/sim/ppc/hw_init.c
+++ b/sim/ppc/hw_init.c
@@ -576,7 +576,7 @@ create_ppc_elf_stack_frame(device *me,
const unsigned sizeof_argv = sizeof_arguments(argv);
const unsigned_word start_argv = start_envp - sizeof_argv;
- /* link register save address - alligned to a 16byte boundary */
+ /* link register save address - aligned to a 16byte boundary */
const unsigned_word top_of_stack = ((start_argv
- 2 * sizeof(unsigned_word))
& ~0xf);
diff --git a/sim/ppc/std-config.h b/sim/ppc/std-config.h
index 0619d1d..e02d594 100644
--- a/sim/ppc/std-config.h
+++ b/sim/ppc/std-config.h
@@ -183,7 +183,7 @@ extern int current_environment;
This model. Instead allows both little and big endian modes to
either take exceptions or handle miss aligned transfers.
- If 0 is specified then for big-endian mode miss alligned accesses
+ If 0 is specified then for big-endian mode miss aligned accesses
are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
processor will fault on them (STRICT_ALIGNMENT). */