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| author | Jeff Law <law@redhat.com> | 1996-12-02 07:38:10 +0000 |
|---|---|---|
| committer | Jeff Law <law@redhat.com> | 1996-12-02 07:38:10 +0000 |
| commit | af388638ae837bb9c54f7b5bc5a16b5148474188 (patch) | |
| tree | 716e620af50e04899ac2f943899b8d8ff614fdd4 /sim | |
| parent | 5840a0e5535fbec7d9039e982577b51209d60feb (diff) | |
| download | gdb-af388638ae837bb9c54f7b5bc5a16b5148474188.zip gdb-af388638ae837bb9c54f7b5bc5a16b5148474188.tar.gz gdb-af388638ae837bb9c54f7b5bc5a16b5148474188.tar.bz2 | |
* simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)".
Along with some compiler, bfd, assembler changes this fixes 90 or so
c-torture execution failures.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/mn10300/ChangeLog | 2 | ||||
| -rw-r--r-- | sim/mn10300/simops.c | 10 |
2 files changed, 7 insertions, 5 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index cd5d1fb..8d86ab7 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -1,5 +1,7 @@ Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com) + * simops.c: Fix "movdm, an", "movbu dm, (an)", and "movhu dm, (an)". + * simops.c: Fix "mov am, dn". * simops.c: Fix more bugs in "add imm,an" and diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c index b4e3014..07a0fb1 100644 --- a/sim/mn10300/simops.c +++ b/sim/mn10300/simops.c @@ -77,7 +77,7 @@ void OP_80 () /* mov dm, an */ void OP_F1E0 () { - State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 3)]; + State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)]; } /* mov am, dn */ @@ -551,8 +551,8 @@ void OP_FCA80000 () /* movbu dm, (an) */ void OP_F050 () { - store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1, - State.regs[REG_D0 + (insn & 0x3)]); + store_mem (State.regs[REG_A0 + (insn & 0x3)], 1, + State.regs[REG_D0 + ((insn & 0xc) >> 2)]); } /* movbu dm, (d8,an) */ @@ -696,8 +696,8 @@ void OP_FCAC0000 () /* movhu dm, (an) */ void OP_F070 () { - store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 2, - State.regs[REG_D0 + (insn & 0x3)]); + store_mem (State.regs[REG_A0 + (insn & 0x3)], 2, + State.regs[REG_D0 + ((insn & 0xc) >> 2)]); } /* movhu dm, (d8,an) */ |