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authorNick Clifton <nickc@redhat.com>2002-05-27 13:30:36 +0000
committerNick Clifton <nickc@redhat.com>2002-05-27 13:30:36 +0000
commit7378e198a59805a4edf671498e01b800b3de5a6d (patch)
tree440d0bc4ebbeebb461ad380ef5ca62957beae6a1 /sim
parent3139facc61e1f4b0af8b814d6775590188b3d79c (diff)
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Thumb BL instruction: Do not set LR to pc + 2, it has already been advanced.
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog5
-rw-r--r--sim/arm/thumbemu.c10
2 files changed, 11 insertions, 4 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index 9739fe1..f20ed35 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,8 @@
+2002-05-27 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * thumbemu.c (ARMul_ThumbDecode, Case 31): Do not set LR to pc +
+ 2, it has already been advanced.
+
2002-05-23 Nick Clifton <nickc@cambridge.redhat.com>
* thumbemu.c (ARMul_ThumbDecode): When decoding a BLX(1)
diff --git a/sim/arm/thumbemu.c b/sim/arm/thumbemu.c
index 283e7d5..1b28edf 100644
--- a/sim/arm/thumbemu.c
+++ b/sim/arm/thumbemu.c
@@ -489,7 +489,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
if r14 is not suitably initialised. */
{
ARMword tmp = (pc + 2);
-
+
state->Reg[15] = ((state->Reg[14] + ((tinstr & 0x07FF) << 1))
& 0xFFFFFFFC);
CLEART;
@@ -509,8 +509,9 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
second half of this BL, and if it is we simulate it
immediately. */
state->Reg[14] = state->Reg[15] \
- +(((tinstr & 0x07FF) << 12) \
- |((tinstr & (1 << 10)) ? 0xFF800000 : 0));
+ + (((tinstr & 0x07FF) << 12) \
+ | ((tinstr & (1 << 10)) ? 0xFF800000 : 0));
+
valid = t_branch; /* in-case we don't have the 2nd half */
tinstr = next_instr; /* move the instruction down */
pc += 2; /* point the pc at the 2nd half */
@@ -543,7 +544,8 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
the simulation of it on its own, with undefined results if
r14 is not suitably initialised. */
{
- ARMword tmp = (pc + 2);
+ ARMword tmp = pc;
+
state->Reg[15] = (state->Reg[14] + ((tinstr & 0x07FF) << 1));
state->Reg[14] = (tmp | 1);
valid = t_branch;