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authorNick Clifton <nickc@redhat.com>2002-05-29 19:01:36 +0000
committerNick Clifton <nickc@redhat.com>2002-05-29 19:01:36 +0000
commit5aa682b2e0d66c71c6c336b5b864418aefcf2d43 (patch)
tree885a6c0f11d57801a5b0cfe268f0e8f7cdc4c6ad /sim
parent4182591fce9f672b648e8dcfcf33d0df556b7a22 (diff)
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Set the FSR and FAR registers if a Data Abort is detected.
Diffstat (limited to 'sim')
-rw-r--r--sim/arm/ChangeLog5
-rw-r--r--sim/arm/armcopro.c9
2 files changed, 13 insertions, 1 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index b5b17f2..85de967 100644
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,8 @@
+2002-05-29 Nick Clifton <nickc@cambridge.redhat.com>
+
+ * armcopro.c (XScale_check_memacc): Set the FSR and FAR registers
+ if a Data Abort is detected.
+
2002-05-27 Nick Clifton <nickc@cambridge.redhat.com>
* armvirt.c (GetWord): Only perform access checks if 'check'
diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c
index 8b04186..2c2ca85 100644
--- a/sim/arm/armcopro.c
+++ b/sim/arm/armcopro.c
@@ -479,7 +479,14 @@ XScale_check_memacc (ARMul_State * state, ARMword * address, int store)
/* Check alignment fault enable/disable. */
if ((read_cp15_reg (1, 0, 0) & ARMul_CP15_R1_ALIGN) && (* address & 3))
- ARMul_Abort (state, ARMul_DataAbortV);
+ {
+ /* Set the FSR and FAR.
+ Do not use XScale_set_fsr_far as this checks the DCSR register. */
+ write_cp15_reg (state, 5, 0, 0, ARMul_CP15_R5_MMU_EXCPT);
+ write_cp15_reg (state, 6, 0, 0, * address);
+
+ ARMul_Abort (state, ARMul_DataAbortV);
+ }
if (XScale_debug_moe (state, -1))
return;