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| author | Tristan Gingold <gingold@adacore.com> | 2009-11-12 15:17:42 +0000 |
|---|---|---|
| committer | Tristan Gingold <gingold@adacore.com> | 2009-11-12 15:17:42 +0000 |
| commit | 33bcfade88c909dad35b582bd8b0e6f9f5d1e395 (patch) | |
| tree | 8c8efad74dc2abb07da9345f270d34d9605a3013 /sim | |
| parent | f24fce77816b17011fdd159f529d1b2dceb4fdac (diff) | |
| download | gdb-33bcfade88c909dad35b582bd8b0e6f9f5d1e395.zip gdb-33bcfade88c909dad35b582bd8b0e6f9f5d1e395.tar.gz gdb-33bcfade88c909dad35b582bd8b0e6f9f5d1e395.tar.bz2 | |
2009-11-12 Tristan Gingold <gingold@adacore.com>
* avr/interp.c (sim_load): Clear memory before loading.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/avr/interp.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index 6a5e74e..18f555c 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,7 @@ +2009-11-12 Tristan Gingold <gingold@adacore.com> + + * avr/interp.c (sim_load): Clear memory before loading. + 2009-11-09 Tristan Gingold <gingold@adacore.com> * avr/interp.c (sim_resume): Fix typo for OP_ret. diff --git a/sim/avr/interp.c b/sim/avr/interp.c index 903370f..8d267dd 100644 --- a/sim/avr/interp.c +++ b/sim/avr/interp.c @@ -1793,6 +1793,10 @@ sim_load (SIM_DESC sd, char *prog, bfd *abfd, int from_tty) { bfd *prog_bfd; + /* Clear all the memory. */ + memset (sram, 0, sizeof (sram)); + memset (flash, 0, sizeof (flash)); + prog_bfd = sim_load_file (sd, myname, callback, prog, abfd, sim_kind == SIM_OPEN_DEBUG, 0, sim_write); |