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authorChris Demetriou <cgd@google.com>2002-12-31 21:31:32 +0000
committerChris Demetriou <cgd@google.com>2002-12-31 21:31:32 +0000
commit28f50ac8150565bd8a4198e2fd0959aa0e5bb4df (patch)
tree547734b29baaddef735127330797b868b192bda0 /sim
parente78b5cfeaf98c0e5ebed98b57d5e2c736c99c71a (diff)
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2002-12-31 Chris Demetriou <cgd@broadcom.com>
* sim-main.h (check_branch_bug, mark_branch_bug): Remove. * mips.igen: Remove all invocations of check_branch_bug and mark_branch_bug.
Diffstat (limited to 'sim')
-rw-r--r--sim/mips/ChangeLog6
-rw-r--r--sim/mips/mips.igen36
-rw-r--r--sim/mips/sim-main.h4
3 files changed, 6 insertions, 40 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index c92eb06..0fe7841 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,9 @@
+2002-12-31 Chris Demetriou <cgd@broadcom.com>
+
+ * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
+ * mips.igen: Remove all invocations of check_branch_bug and
+ mark_branch_bug.
+
2002-12-16 Chris Demetriou <cgd@broadcom.com>
* tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 39267a0..3d4eeb0 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -565,10 +565,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -588,10 +586,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -614,10 +610,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -638,13 +632,11 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -664,7 +656,6 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
@@ -672,7 +663,6 @@
executed */
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -694,10 +684,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] >= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -720,10 +708,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -743,12 +729,10 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] > 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -771,12 +755,10 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -796,10 +778,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] <= 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -822,10 +802,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -846,7 +824,6 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
@@ -854,7 +831,6 @@
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -874,13 +850,11 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if (RS == 31)
Unpredictable ();
RA = (CIA + 8);
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -902,12 +876,10 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
/* NOTE: The branch occurs AFTER the next instruction has been
executed */
if ((signed_word) GPR[RS] < 0)
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -930,10 +902,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
}
@@ -953,10 +923,8 @@
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
- check_branch_bug ();
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
{
- mark_branch_bug (NIA+offset);
DELAY_SLOT (NIA + offset);
}
else
@@ -3792,13 +3760,11 @@
*mipsIII:
{
check_fpu (SD_);
- check_branch_bug ();
TRACE_BRANCH_INPUT (PREVCOC1());
if (PREVCOC1() == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
TRACE_BRANCH_RESULT (dest);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
@@ -3824,11 +3790,9 @@
*r3900:
{
check_fpu (SD_);
- check_branch_bug ();
if (GETFCC(CC) == TF)
{
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
- mark_branch_bug (dest);
DELAY_SLOT (dest);
}
else if (ND)
diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index fed625e..3cb9b35 100644
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -423,10 +423,6 @@ struct _sim_cpu {
hilo_history lo_history;
#define LOHISTORY (&(CPU)->lo_history)
-#define check_branch_bug()
-#define mark_branch_bug(TARGET)
-
-
sim_cpu_base base;
};