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| author | Andrew Cagney <cagney@redhat.com> | 1997-09-19 06:39:21 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-19 06:39:21 +0000 |
| commit | a276b6f057a0f2a6e1432117a55614d3df6148f5 (patch) | |
| tree | 99ff3385e8fb5a0c469b287f1bc4d91f0c66b0c3 /sim/v850/ChangeLog | |
| parent | 4410c4b9254f6b29bab904a01cddd0ded8f51365 (diff) | |
| download | gdb-a276b6f057a0f2a6e1432117a55614d3df6148f5.zip gdb-a276b6f057a0f2a6e1432117a55614d3df6148f5.tar.gz gdb-a276b6f057a0f2a6e1432117a55614d3df6148f5.tar.bz2 | |
Clean up tracing for Bcond & jmp insns.
Fix computation of disp16 and disp22.
Clean up tracing of sld* insns.
Diffstat (limited to 'sim/v850/ChangeLog')
| -rw-r--r-- | sim/v850/ChangeLog | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index cfcf3bb..4c21399 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,8 +1,28 @@ Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com> + * v850.igen (disp16): Use EXTEND16 to sign extend disp. + (disp22): Only shift left by 1, not 2. + ("jmp"): Ensure PC is 2 byte aligned. + + * simops.c, v850.igen: Move "Bcond", "jr", "jarl" code to + v850.igen. Fix tracing. + + * simops.c (OP_300, OP_400, OP_500): Move "sdl.b", "sld.h", + "sld.w" insns to v850.igen. Fix tracing. +start-sanitize-v850eq + (OP_70): Ditto for "sld.hu". +end-sanitize-v850eq + + * v850.igen: Clarify tracing of "sld.b", "sld.h" et.al. + +end-sanitize-v850eq * simops.c (condition_met): Make global. - * sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0): Define. + * sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0, TRACE_LD, + TRACE_ST): Define. +start-sanitize-v850eq + (TRACE_LD_NAME): Define. +end-sanitize-v850eq start-sanitize-v850e * simops.c: Move "cmov", "cmov imm" to v850.igen, fix. |