c80 simulator fixes.

6 files changed, 92 insertions, 26 deletions

diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index ac4ffa5..8df333e 100644
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,3 +1,27 @@
+Mon May 12 11:12:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
+ 	rDest + 1. Also done by Michael Meissner  <meissner@cygnus.com>
+	(do_st): Converse for store.
+
+	* misc.c (tic80_trace_fpu2i): Correct printf format for int type.
+
+Sun May 11 11:02:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
+ 	was cleared.
+
+	* interp.c (engine_step): New function.  Single step the simulator
+ 	taking care of cntrl-c during a step.
+
+	* sim-calls.c (sim_resume): Differentiate between stepping and
+ 	running so that a cntrl-c during a step is reported.
+
+Sun May 11 10:54:31 1997  Mark Alexander    <marka@cygnus.com>
+
+	* sim-calls.c (sim_fetch_register): Use correct reg base.
+	(sim_store_register): Ditto.
+
 Sun May 11 10:25:14 1997  Michael Meissner  <meissner@cygnus.com>
 
 	* cpu.h (tic80_trace_shift): Add declaration.
diff --git a/sim/tic80/insns b/sim/tic80/insns
index 5a4110b..d924005 100644
--- a/sim/tic80/insns
+++ b/sim/tic80/insns
@@ -633,7 +633,6 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink,
 // ld[{.b.h.d}]
 void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 	unsigned32 addr;
-	unsigned64 u64;
 	switch (sz)
 	  {
 	  case 0:
@@ -655,15 +654,18 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
 	    GPR(Dest) = MEM (signed, addr, 4);
 	    break;
 	  case 3:
-	    if (Dest & 0x1)
-	      engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
-	                    cia.ip, Dest);
-	    addr = Base + (S ? (Offset << 3) : Offset);
-	    if (m)
-	      *rBase = addr;
-	    u64 = MEM (signed, addr, 8);
-	    GPR(Dest) = (unsigned32) u64;
-	    GPR(Dest+1) = (unsigned32) (u64 >> 32);
+	    {
+	      signed64 val;
+	      if (Dest & 0x1)
+	        engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
+	                      cia.ip, Dest);
+	      addr = Base + (S ? (Offset << 3) : Offset);
+	      if (m)
+	        *rBase = addr;
+	      val = MEM (signed, addr, 8);
+	      GPR(Dest + 1) = VH4_8 (val);
+	      GPR(Dest + 0) = VL4_8 (val);
+	    }
 	    break;
 	  default:
 	    addr = -1;
@@ -898,7 +900,6 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
 // st[{.b|.h|.d}]
 void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
 	unsigned32 addr;
-	unsigned64 u64;
 	switch (sz)
 	  {
 	  case 0:
@@ -914,13 +915,16 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
 	    STORE (addr, 4, GPR(Source));
 	    break;
 	  case 3:
-	    if (Source & 0x1)
-	      engine_error (SD, CPU, cia, "0x%lx: st.d with odd source register %d",
-	                    cia.ip, Source);
-	    addr = Base + (S ? (Offset << 3) : Offset);
-	    u64 = GPR (Source);
-	    u64 |= (((unsigned64) GPR (Source+1)) << 32);
-	    STORE (addr, 8, u64);
+	    {
+	      signed64 val;
+	      if (Source & 0x1)
+	        engine_error (SD, CPU, cia,
+	                      "0x%lx: st.d with odd source register %d",
+	                      cia.ip, Source);
+	      addr = Base + (S ? (Offset << 3) : Offset);
+	      val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
+	      STORE (addr, 8, val);
+	    }
 	    break;
 	  default:
 	    addr = -1;
diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c
index b8ba567..8fda287 100644
--- a/sim/tic80/interp.c
+++ b/sim/tic80/interp.c
@@ -129,3 +129,30 @@ engine_run_until_stop (SIM_DESC sd,
       engine_halt (sd, cpu, cia, sim_stopped, SIGINT);
     }
 }
+
+
+void
+engine_step (SIM_DESC sd)
+{
+  if (!setjmp (sd->path_to_halt))
+    {
+      instruction_address cia;
+      sim_cpu *cpu = STATE_CPU (sd, 0);
+      sd->halt_ok = 1;
+      setjmp (sd->path_to_restart);
+      sd->restart_ok = 1;
+      cia = cpu->cia;
+      if (cia.ip == -1)
+	{
+	  /* anulled instruction */
+	  cia.ip = cia.dp;
+	  cia.dp = cia.dp + sizeof (instruction_word);
+	}
+      else
+	{
+	  instruction_word insn = IMEM (cia.ip);
+	  cia = idecode_issue (sd, insn, cia);
+	}
+      engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
+    }
+}
diff --git a/sim/tic80/misc.c b/sim/tic80/misc.c
index b9af1b8..e24efd3 100644
--- a/sim/tic80/misc.c
+++ b/sim/tic80/misc.c
@@ -282,7 +282,7 @@ tic80_trace_fpu2i (SIM_DESC sd,
 
   trace_one_insn (sd, cpu, cia.ip, 1,
 		  itable[indx].file, itable[indx].line_nr, "fpu",
-		  "%-*s %*f %*f => 0x%.*lx %-*s",
+		  "%-*s %*f %*f => 0x%.*lx %-*ld",
 		  tic80_size_name, itable[indx].name,
 		  SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1),
 		  SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2),
diff --git a/sim/tic80/sim-calls.c b/sim/tic80/sim-calls.c
index 23b3860..ae3f2ab 100644
--- a/sim/tic80/sim-calls.c
+++ b/sim/tic80/sim-calls.c
@@ -178,7 +178,7 @@ void
 sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf)
 {
   if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
-    *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - A0_REGNUM]);
+    *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]);
   else if (regnr == PC_REGNUM)
     *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip);
   else if (regnr == NPC_REGNUM)
@@ -195,7 +195,7 @@ void
 sim_store_register (SIM_DESC sd, int regnr, unsigned char *buf)
 {
   if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
-    STATE_CPU (sd, 0)->reg[regnr - A0_REGNUM] = T2H_4 (*(unsigned32*)buf);
+    STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM] = T2H_4 (*(unsigned32*)buf);
   else if (regnr == PC_REGNUM)
     STATE_CPU (sd, 0)->cia.ip = T2H_4 (*(unsigned32*)buf);
   else if (regnr == NPC_REGNUM)
@@ -233,9 +233,17 @@ volatile int keep_running = 1;
 void
 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc)
 {
-  *reason = simulation.reason;
-  *sigrc = simulation.siggnal;
-  keep_running = 1; /* ready for next run */
+  if (!keep_running)
+    {
+      *reason = sim_stopped;
+      *sigrc = SIGINT;
+      keep_running = 0;
+    }
+  else
+    {
+      *reason = simulation.reason;
+      *sigrc = simulation.siggnal;
+    }
 }
 
 
@@ -251,8 +259,9 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
 {
   /* keep_running = 1 - in sim_stop_reason */
   if (step)
-    keep_running = 0;
-  engine_run_until_stop(sd, &keep_running);
+    engine_step (sd);
+  else
+    engine_run_until_stop (sd, &keep_running);
 }
 
 void
diff --git a/sim/tic80/sim-main.h b/sim/tic80/sim-main.h
index 1992f29..be4e88d 100644
--- a/sim/tic80/sim-main.h
+++ b/sim/tic80/sim-main.h
@@ -101,5 +101,7 @@ extern void engine_run_until_stop
 (SIM_DESC sd,
  volatile int *keep_running);
 
+extern void engine_step
+(SIM_DESC sd);
 
 #endif