o Make tic80 insn file more `cache ready'

o	Have igen always zero r0 instead of constantly checking if
	the designated register is r0.

7 files changed, 202 insertions, 174 deletions

diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index 8f9ffd0..81a7ad3 100644
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,3 +1,20 @@
+Fri May 16 11:57:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* ic (compute): Drop check for REG == 0, now always forced to
+ 	zero.
+
+	* cpu.h (GPR_SET): New macro update the gpr.
+	* insns (do_add): Use GPR_SET to update the GPR register.
+
+	* sim-calls.c (sim_fetch_register): Pretend that r0 is zero.
+
+	* Makefile.in (tmp-igen): Specify zero-r0 so that every
+ 	instruction clears r0.
+
+	* interp.c (engine_run_until_stop): Igen now generates code to
+ 	clear r0.
+	(engine_step): Ditto.
+
 Thu May 15 11:45:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* insns (do_shift): When rot==0 and zero/sign merge treat it as
diff --git a/sim/tic80/Makefile.in b/sim/tic80/Makefile.in
index 0e9dc25..dbfb4b6 100644
--- a/sim/tic80/Makefile.in
+++ b/sim/tic80/Makefile.in
@@ -92,6 +92,7 @@ tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen
 		-F f \
 		-G direct-access \
 		-G delayed-branch \
+		-G zero-r0 \
 		-F short,emul \
 		-B 32 -H 31 \
 		-o $(srcdir)/dc \
diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h
index 0027af0..d3d14b6 100644
--- a/sim/tic80/cpu.h
+++ b/sim/tic80/cpu.h
@@ -152,6 +152,7 @@ struct _sim_cpu {
 };
 
 #define GPR(N) ((CPU)->reg[N])
+#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
 #define ACC(N) ((CPU)->acc[N])
 #define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
 
diff --git a/sim/tic80/ic b/sim/tic80/ic
index 0fbbb5e..54a2550 100644
--- a/sim/tic80/ic
+++ b/sim/tic80/ic
@@ -2,19 +2,25 @@ compute:Dest:Dest:
 compute:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])
 #
 compute:Source1:Source1:
-compute:Source1:rSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
+compute:Source1:vSource1:signed_word:(GPR (Source1) + 0)
+#compute:Source1:vSource1:signed_word:(Source1 == 0 ? 0 : (CPU)->reg[Source1])
 #
 compute:Source2:Source2:
-compute:Source2:rSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
+compute:Source2:vSource2:signed_word:(GPR (Source2) + 0)
+#compute:Source2:vSource2:signed_word:(Source2 == 0 ? 0 : (CPU)->reg[Source2])
 #
 compute:Source:Source:
-compute:Source:rSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
+compute:Source:vSource:signed_word:(GPR (Source) + 0)
+#compute:Source:vSource:signed_word:(Source == 0 ? 0 : (CPU)->reg[Source])
 #
 compute:IndOff:IndOff:
-compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
+compute:IndOff:rIndOff:signed_word:(GPR (IndOff) + 0)
+#compute:IndOff:rIndOff:signed_word:(IndOff == 0 ? 0 : (CPU)->reg[IndOff])
 #
 compute:Base:Base:
-compute:Base:rBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
+compute:Base:vBase:signed_word:(GPR (Base) + 0)
+compute:Base:rBase:signed_word:(&GPR (Base))
+#compute:Base:vBase:signed_word:(Base == 0 ? 0 : (CPU)->reg[Base])
 #
 compute:Link:Link:
 compute:Link:rLink:signed_word:(&(CPU)->reg[Link])
@@ -40,4 +46,5 @@ compute:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)
 #
 compute:UCRN:UCRN:
 compute:INDCR:INDCR:
-compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])
+compute:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)
+#compute:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])
diff --git a/sim/tic80/insns b/sim/tic80/insns
index 7a15fc7..182fcbd 100644
--- a/sim/tic80/insns
+++ b/sim/tic80/insns
@@ -48,80 +48,82 @@ instruction_address::function::do_branch:int annul, address_word target, int rLi
 	return nia;
 
 // Signed Integer Add - add source1, source2, dest
-void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2
-	ALU_BEGIN (Source1);
-	ALU_ADD (Source2);
-	ALU_END (*rDest);
-	TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
+void::function::do_add:unsigned32 *rDest, signed32 source1, signed32 source2
+	unsigned32 result;
+	ALU_BEGIN (source1);
+	ALU_ADD (source2);
+	ALU_END (result);
+	*rDest = result;
+	TRACE_ALU3 (MY_INDEX, result, source1, source2);
 	/* FIXME - a signed add may cause an exception */
 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i
-	do_add (_SD, rDest, vSource1, rSource2);
+	do_add (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r
-	do_add (_SD, rDest, rSource1, rSource2);
+	do_add (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l
 	long_immediate (LongSignedImmediate);
-	do_add (_SD, rDest, LongSignedImmediate, rSource2);
+	do_add (_SD, rDest, LongSignedImmediate, vSource2);
 
 
 // Unsigned Integer Add - addu source1, source2, dest
-void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
-	unsigned32 result = Source1 + Source2;
-	TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
+void::function::do_addu:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
+	unsigned32 result = source1 + source2;
+	TRACE_ALU3 (MY_INDEX, result, source1, source2);
 	*rDest = result;
 
 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i
-	do_addu (_SD, rDest, vSource1, rSource2);
+	do_addu (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r
-	do_addu (_SD, rDest, rSource1, rSource2);
+	do_addu (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l
 	long_immediate (LongSignedImmediate);
-	do_addu (_SD, rDest, LongSignedImmediate, rSource2);
+	do_addu (_SD, rDest, LongSignedImmediate, vSource2);
 
 
-void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2
-	unsigned32 result = Source1 & Source2;
-	TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
+void::function::do_and:signed32 *rDest, signed32 source1, signed32 source2
+	unsigned32 result = source1 & source2;
+	TRACE_ALU3 (MY_INDEX, result, source1, source2);
 	*rDest = result;
 
 
 // and, and.tt
 31.Dest,26.Source2,21.0b0010001,14.UnsignedImmediate::::and.tt i
-	do_and (_SD, rDest, vSource1, rSource2);
+	do_and (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r
-	do_and (_SD, rDest, rSource1, rSource2);
+	do_and (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l
 	long_immediate (LongSignedImmediate);
-	do_and (_SD, rDest, LongSignedImmediate, rSource2);
+	do_and (_SD, rDest, LongSignedImmediate, vSource2);
 
 
 // and.ff
 31.Dest,26.Source2,21.0b0011000,14.UnsignedImmediate::::and.ff i
-	do_and (_SD, rDest, ~vSource1, ~rSource2);
+	do_and (_SD, rDest, ~vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r
-	do_and (_SD, rDest, ~rSource1, ~rSource2);
+	do_and (_SD, rDest, ~vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l
 	long_immediate (LongSignedImmediate);
-	do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2);
+	do_and (_SD, rDest, ~LongSignedImmediate, ~vSource2);
 
 
 // and.ft
 31.Dest,26.Source2,21.0b0010100,14.UnsignedImmediate::::and.ft i
-	do_and (_SD, rDest, ~vSource1, rSource2);
+	do_and (_SD, rDest, ~vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r
-	do_and (_SD, rDest, ~rSource1, rSource2);
+	do_and (_SD, rDest, ~vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l
 	long_immediate (LongSignedImmediate);
-	do_and (_SD, rDest, ~LongSignedImmediate, rSource2);
+	do_and (_SD, rDest, ~LongSignedImmediate, vSource2);
 
 
 // and.tf
 31.Dest,26.Source2,21.0b0010010,14.UnsignedImmediate::::and.tf i
-	do_and (_SD, rDest, vSource1, ~rSource2);
+	do_and (_SD, rDest, vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r
-	do_and (_SD, rDest, rSource1, ~rSource2);
+	do_and (_SD, rDest, vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l
 	long_immediate (LongSignedImmediate);
-	do_and (_SD, rDest, LongSignedImmediate, ~rSource2);
+	do_and (_SD, rDest, LongSignedImmediate, ~vSource2);
 
 
 // bbo.[a]
@@ -139,12 +141,12 @@ instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsig
 	TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 	return nia;
 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i
-	nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset);
+	nia = do_bbo (_SD, nia, BITNUM, vSource, A, vSignedOffset);
 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r
-	nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff);
+	nia = do_bbo (_SD, nia, BITNUM, vSource, A, rIndOff);
 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l
 	long_immediate (LongSignedImmediate);
-	nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
+	nia = do_bbo (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
 
 
 // bbz[.a]
@@ -162,12 +164,12 @@ instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsig
 	TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target);
 	return nia;
 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i
-	nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset);
+	nia = do_bbz (_SD, nia, BITNUM, vSource, A, vSignedOffset);
 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r
-	nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff);
+	nia = do_bbz (_SD, nia, BITNUM, vSource, A, rIndOff);
 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l
 	long_immediate (LongSignedImmediate);
-	nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate);
+	nia = do_bbz (_SD, nia, BITNUM, vSource, A, LongSignedImmediate);
 
 
 // bcnd[.a]
@@ -202,12 +204,12 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign
 	TRACE_COND_BR(MY_INDEX, condition, source, target);
 	return nia;
 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i
-	nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset);
+	nia = do_bcnd (_SD, nia, Code, vSource, A, vSignedOffset);
 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r
-	nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff);
+	nia = do_bcnd (_SD, nia, Code, vSource, A, rIndOff);
 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l
 	long_immediate (LongSignedImmediate);
-	nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate);
+	nia = do_bcnd (_SD, nia, Code, vSource, A, LongSignedImmediate);
 
 
 // br[.a] - see bbz[.a]
@@ -296,7 +298,7 @@ void::function::do_cmnd:signed32 source
 31./,21.0b0000010,14.UI::::cmnd i
 	do_cmnd (_SD, UI);
 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r
-	do_cmnd (_SD, rSource);
+	do_cmnd (_SD, vSource);
 31./,21.0b110000010,12.1,11./::::cmnd l
 	long_immediate (LongUnsignedImmediate);
 	do_cmnd (_SD, LongUnsignedImmediate);
@@ -315,22 +317,22 @@ unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned
 	if (u1 <  u2) field |= 0x100;
 	if (u1 >= u2) field |= 0x200;
 	return field;
-void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
+void::function::do_cmp:unsigned32 *rDest, unsigned32 source1, unsigned32 source2
 	unsigned32 field = 0;
-	field |= cmp_vals (_SD, Source1, Source1, Source2, Source2) << 20;
-	field |= cmp_vals (_SD, (signed16)Source1, (unsigned16)Source1,
-			   (signed16)Source2, (unsigned16)Source2) << 10;
-	field |= cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1,
-			    (signed8)Source2, (unsigned8)Source2);
-	TRACE_ALU3 (MY_INDEX, field, Source1, Source2);
+	field |= cmp_vals (_SD, source1, source1, source2, source2) << 20;
+	field |= cmp_vals (_SD, (signed16)source1, (unsigned16)source1,
+			   (signed16)source2, (unsigned16)source2) << 10;
+	field |= cmp_vals (_SD, (signed8)source1, (unsigned8)source1,
+			    (signed8)source2, (unsigned8)source2);
+	TRACE_ALU3 (MY_INDEX, field, source1, source2);
 	*rDest = field;
 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i
-	do_cmp (_SD, rDest, vSource1, rSource2);
+	do_cmp (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r
-	do_cmp (_SD, rDest, rSource1, rSource2);
+	do_cmp (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l
 	long_immediate (LongSignedImmediate);
-	do_cmp (_SD, rDest, LongSignedImmediate, rSource2);
+	do_cmp (_SD, rDest, LongSignedImmediate, vSource2);
 
 
 // dcache
@@ -348,33 +350,33 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 
 
 // dld[{.b|.h|.d}]
-void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
-	do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset);
+void::function::do_dld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
+	do_ld (_SD, Dest, base, rBase, m, sz, S, offset);
 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r
-	do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
+	do_dld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l
 	long_immediate (LongSignedImmediateOffset);
-	do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
+	do_dld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 
 
 // dld.u[{.b|.h|.d}]
-void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
-	do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset);
+void::function::do_dld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
+	do_ld_u (_SD, rDest, base, rBase, m, sz, S, offset);
 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r
-	do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
+	do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l
 	long_immediate (LongSignedImmediateOffset);
-	do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
+	do_dld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 
 
 // dst[{.b|.h|.d}]
-void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
-	do_st (_SD, Source, Base, rBase, m, sz, S, Offset);
+void::function::do_dst:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
+	do_st (_SD, Source, base, rBase, m, sz, S, offset);
 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r
-	do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
+	do_dst (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l
 	long_immediate (LongSignedImmediateOffset);
-	do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
+	do_dst (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 
 
 // estop
@@ -404,8 +406,8 @@ sim_fpu::function::get_fp_reg:int reg, unsigned32 val, int precision
 	      engine_error (SD, CPU, cia, "DP FP register must be even");
 	    if (reg <= 1)
 	      engine_error (SD, CPU, cia, "DP FP register must be >= 2");
-	    return sim_fpu_64to (INSERTED64 (GPR(reg + 1), 63, 32)
-	                         | INSERTED64 (GPR(reg), 31, 0));
+	    return sim_fpu_64to (INSERTED64 (GPR (reg + 1), 63, 32)
+	                         | INSERTED64 (GPR (reg), 31, 0));
 	  case 2: /* 32 bit signed integer */
 	    return sim_fpu_i32to (val);
 	  case 3: /* 32 bit unsigned integer */
@@ -454,17 +456,17 @@ void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2
 	set_fp_reg (_SD, Dest, ans, PD);
 31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r
 	do_fadd (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source1, rSource1, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source1, vSource1, P1),
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_fadd (_SD, Dest, PD,
 	         get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 
 
 // fcmp.{s|d}{s|d}{s|d}
-void::function::do_fcmp:int Dest, sim_fpu s1, sim_fpu s2
+void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2
 	unsigned32 result = 0;
 	if (sim_fpu_is_nan (s1) || sim_fpu_is_nan (s2))
 	  result |= BIT32 (30);
@@ -486,17 +488,17 @@ void::function::do_fcmp:int Dest, sim_fpu s1, sim_fpu s2
 	    if (sim_fpu_is_le (s1, sim_fpu_i32to (0))
 	        || sim_fpu_is_ge (s1, s2)) result |= BIT32(29);
 	  }
-	GPR (Dest) = result;
+	*rDest = result;
 	TRACE_FPU2I (MY_INDEX, result, s1, s2);
 31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r
-	do_fcmp (_SD, Dest,
-	         get_fp_reg (_SD, Source1, rSource1, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	do_fcmp (_SD, rDest,
+	         get_fp_reg (_SD, Source1, vSource1, P1),
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l
 	long_immediate (SinglePrecisionFloatingPoint);
-	do_fcmp (_SD, Dest,
+	do_fcmp (_SD, rDest,
 	         get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 
 
 
@@ -507,13 +509,13 @@ void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
 	set_fp_reg (_SD, Dest, ans, PD);
 31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r
 	do_fdiv (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source1, rSource1, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source1, vSource1, P1),
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_fdiv (_SD, Dest, PD,
 	         get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 
 
 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
@@ -541,13 +543,13 @@ void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
 	  }
 31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
 	do_fmpy (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source1, rSource1, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source1, vSource1, P1),
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_fmpy (_SD, Dest, PD,
 	         get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 
 
 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u}
@@ -556,7 +558,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
 	TRACE_FPU1 (MY_INDEX, s1);
 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r
 	do_frnd (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source, rSource, P1));
+	         get_fp_reg (_SD, Source, vSource, P1));
 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_frnd (_SD, Dest, PD,
@@ -566,7 +568,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
 // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r
 	do_frnd (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source, rSource, P1));
+	         get_fp_reg (_SD, Source, vSource, P1));
 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_frnd (_SD, Dest, PD,
@@ -576,7 +578,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
 // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r
 	do_frnd (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source, rSource, P1));
+	         get_fp_reg (_SD, Source, vSource, P1));
 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_frnd (_SD, Dest, PD,
@@ -586,7 +588,7 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
 // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u}
 31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r
 	do_frnd (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source, rSource, P1));
+	         get_fp_reg (_SD, Source, vSource, P1));
 31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_frnd (_SD, Dest, PD,
@@ -597,9 +599,9 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1
 #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 #	sim_io_error ("fsqrt");
 31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r
-#	do_fsqrt (_SD, rDest, rSource1, rSource2);
+#	do_fsqrt (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l
-#	do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2);
+#	do_fsqrt (_SD, rDest, LongSignedImmediate, vSource2);
 
 
 // fsub.{s|d}{s|d}{s|d}
@@ -609,13 +611,13 @@ void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2
 	set_fp_reg (_SD, Dest, ans, PD);
 31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r
 	do_fsub (_SD, Dest, PD,
-	         get_fp_reg (_SD, Source1, rSource1, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source1, vSource1, P1),
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l
 	long_immediate (SinglePrecisionFloatingPoint);
 	do_fsub (_SD, Dest, PD,
 	         get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1),
-	         get_fp_reg (_SD, Source2, rSource2, P2));
+	         get_fp_reg (_SD, Source2, vSource2, P2));
 
 
 // illop
@@ -638,33 +640,33 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink,
 	                (unsigned long) nia.dp);
 	return nia;
 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i
-	nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase);
+	nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, vBase);
 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r
-	nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase);
+	nia = do_jsr (_SD, nia, rLink, A, vSource1, vBase);
 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l
 	long_immediate (LongSignedImmediate);
-	nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase);
+	nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, vBase);
 
 
 // ld[{.b.h.d}]
-void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
+void::function::do_ld:int Dest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 	unsigned32 addr;
 	switch (sz)
 	  {
 	  case 0:
-	    addr = Base + (S ? (Offset << 0) : Offset);
+	    addr = base + (S ? (offset << 0) : offset);
 	    if (m)
 	      *rBase = addr;
 	    GPR(Dest) = MEM (signed, addr, 1);
 	    break;
 	  case 1:
-	    addr = Base + (S ? (Offset << 1) : Offset);
+	    addr = base + (S ? (offset << 1) : offset);
 	    if (m)
 	      *rBase = addr;
 	    GPR(Dest) = MEM (signed, addr, 2);
 	    break;
 	  case 2:
-	    addr = Base + (S ? (Offset << 2) : Offset);
+	    addr = base + (S ? (offset << 2) : offset);
 	    if (m)
 	      *rBase = addr;
 	    GPR(Dest) = MEM (signed, addr, 4);
@@ -675,7 +677,7 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
 	      if (Dest & 0x1)
 	        engine_error (SD, CPU, cia, "0x%lx: ld.d to odd register %d",
 	                      cia.ip, Dest);
-	      addr = Base + (S ? (Offset << 3) : Offset);
+	      addr = base + (S ? (offset << 3) : offset);
 	      if (m)
 	        *rBase = addr;
 	      val = MEM (signed, addr, 8);
@@ -687,27 +689,27 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int
 	    addr = -1;
 	    engine_error (SD, CPU, cia, "ld - invalid sz %d", sz);
 	  }
-	TRACE_LD (MY_INDEX, GPR(Dest), m, S, Base, Offset);
+	TRACE_LD (MY_INDEX, GPR(Dest), m, S, base, offset);
 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i
-	do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
+	do_ld (_SD, Dest, vBase, rBase, m, sz, 0, vSignedOffset);
 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r
-	do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff);
+	do_ld (_SD, Dest, vBase, rBase, m, sz, S, rIndOff);
 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l
 	long_immediate (LongSignedImmediateOffset);
-	do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
+	do_ld (_SD, Dest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 
 
 // ld.u[{.b.h.d}]
-void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
+void::function::do_ld_u:unsigned32 *rDest, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 	unsigned32 addr;
 	switch (sz)
 	  {
 	  case 0:
-	    addr = Base + (S ? (Offset << 0) : Offset);
+	    addr = base + (S ? (offset << 0) : offset);
 	    *rDest = MEM (unsigned, addr, 1);
 	    break;
 	  case 1:
-	    addr = Base + (S ? (Offset << 1) : Offset);
+	    addr = base + (S ? (offset << 1) : offset);
 	    *rDest = MEM (unsigned, addr, 2);
 	    break;
 	  default:
@@ -716,23 +718,23 @@ void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, i
 	  }
 	if (m)
 	  *rBase = addr;
-	TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset);
+	TRACE_LD (MY_INDEX, m, S, *rDest, base, offset);
 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i
-	do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
+	do_ld_u (_SD, rDest, vBase, rBase, m, sz, 0, vSignedOffset);
 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r
-	do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff);
+	do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, rIndOff);
 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l
 	long_immediate (LongSignedImmediateOffset);
-	do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
+	do_ld_u (_SD, rDest, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 
 
 // lmo
 31.Dest,26.Source,21.0b111111000,12.0,11./::::lmo
 	int b;
 	for (b = 0; b < 32; b++)
-	  if (rSource & BIT32 (31 - b))
+	  if (vSource & BIT32 (31 - b))
 	    break;
-	TRACE_ALU2 (MY_INDEX, b, rSource);
+	TRACE_ALU2 (MY_INDEX, b, vSource);
 	*rDest = b;
 	
 
@@ -747,42 +749,42 @@ void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2
 
 // or, or.tt
 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i
-	do_or (_SD, rDest, vSource1, rSource2);
+	do_or (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r
-	do_or (_SD, rDest, rSource1, rSource2);
+	do_or (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l
 	long_immediate (LongUnsignedImmediate);
-	do_or (_SD, rDest, LongUnsignedImmediate, rSource2);
+	do_or (_SD, rDest, LongUnsignedImmediate, vSource2);
 
 
 // or.ff
 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i
-	do_or (_SD, rDest, ~vSource1, ~rSource2);
+	do_or (_SD, rDest, ~vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r
-	do_or (_SD, rDest, ~rSource1, ~rSource2);
+	do_or (_SD, rDest, ~vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l
 	long_immediate (LongUnsignedImmediate);
-	do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2);
+	do_or (_SD, rDest, ~LongUnsignedImmediate, ~vSource2);
 
 
 // or.ft
 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i
-	do_or (_SD, rDest, ~vSource1, rSource2);
+	do_or (_SD, rDest, ~vSource1, vSource2);
 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r
-	do_or (_SD, rDest, ~rSource1, rSource2);
+	do_or (_SD, rDest, ~vSource1, vSource2);
 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l
 	long_immediate (LongUnsignedImmediate);
-	do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2);
+	do_or (_SD, rDest, ~LongUnsignedImmediate, vSource2);
 
 
 // or.tf
 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i
-	do_or (_SD, rDest, vSource1, ~rSource2);
+	do_or (_SD, rDest, vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r
-	do_or (_SD, rDest, rSource1, ~rSource2);
+	do_or (_SD, rDest, vSource1, ~vSource2);
 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l
 	long_immediate (LongUnsignedImmediate);
-	do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2);
+	do_or (_SD, rDest, LongUnsignedImmediate, ~vSource2);
 
 
 // rdcr
@@ -802,11 +804,11 @@ void::function::do_rdcr:unsigned32 Dest, int cr
 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo
 	int b;
 	for (b = 0; b < 32; b++)
-	  if (rSource & BIT32 (b))
+	  if (vSource & BIT32 (b))
 	    break;
 	if (b < 32)
 	  b = 31 - b;
-	TRACE_ALU2 (MY_INDEX, b, rSource);
+	TRACE_ALU2 (MY_INDEX, b, vSource);
 	*rDest = b;
 
 
@@ -820,9 +822,9 @@ void::function::do_rdcr:unsigned32 Dest, int cr
 
 
 // sl.{d|e|i}{m|s|z}
-void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate
+void::function::do_shift:int Dest, unsigned32 source, int Merge, int i, int n, int EndMask, int Rotate
 	/* see 10-30 for a reasonable description */
-	unsigned32 input = GPR (Source);
+	unsigned32 input = source;
 	unsigned32 rotated;
 	unsigned32 endmask;
 	unsigned32 shiftmask;
@@ -831,12 +833,12 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
 	/* rotate the source */
 	if (n)
 	  {
-	    rotated = ROTR32 (GPR (Source), Rotate);
+	    rotated = ROTR32 (source, Rotate);
 	    nRotate = (- Rotate) & 31;
 	  }
 	else
 	  {
-	    rotated = ROTL32 (GPR (Source), Rotate);
+	    rotated = ROTL32 (source, Rotate);
 	    nRotate = Rotate;
 	  }
 	/* form the end mask */
@@ -867,7 +869,7 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
 	  default:
 	    engine_error (SD, CPU, cia,
 	                  "0x%lx: Invalid merge (%d) for shift",
-	                  cia.ip, Source);
+	                  cia.ip, source);
 	    shiftmask = 0;
 	  }
 	/* and the composite mask */
@@ -894,14 +896,14 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
 	  default:
 	    engine_error (SD, CPU, cia,
 	                  "0x%lx: Invalid merge (%d)",
-	                  cia.ip, Source);
+	                  cia.ip, source);
 
 	  }
 	TRACE_SHIFT (MY_INDEX, GPR (Dest), input, i, n, Merge, EndMask, Rotate);
 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i
-	do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate);
+	do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, Rotate);
 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r
-	do_shift (_SD, Dest, Source, Merge, i, n, EndMask, GPR (RotReg) & 31);
+	do_shift (_SD, Dest, vSource, Merge, i, n, EndMask, GPR (RotReg) & 31);
 
 
 // sli.{d|e|i}{m|s|z} - see shift
@@ -920,20 +922,20 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
 
 
 // st[{.b|.h|.d}]
-void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset
+void::function::do_st:int Source, unsigned32 base, unsigned32 *rBase, int m , int sz, int S, unsigned32 offset
 	unsigned32 addr;
 	switch (sz)
 	  {
 	  case 0:
-	    addr = Base + (S ? (Offset << 0) : Offset);
+	    addr = base + (S ? (offset << 0) : offset);
 	    STORE (addr, 1, GPR(Source));
 	    break;
 	  case 1:
-	    addr = Base + (S ? (Offset << 1) : Offset);
+	    addr = base + (S ? (offset << 1) : offset);
 	    STORE (addr, 2, GPR(Source));
 	    break;
 	  case 2:
-	    addr = Base + (S ? (Offset << 2) : Offset);
+	    addr = base + (S ? (offset << 2) : offset);
 	    STORE (addr, 4, GPR(Source));
 	    break;
 	  case 3:
@@ -943,7 +945,7 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
 	        engine_error (SD, CPU, cia,
 	                      "0x%lx: st.d with odd source register %d",
 	                      cia.ip, Source);
-	      addr = Base + (S ? (Offset << 3) : Offset);
+	      addr = base + (S ? (offset << 3) : offset);
 	      val = (V4_H8 (GPR(Source + 1)) | V4_L8 (GPR(Source)));
 	      STORE (addr, 8, val);
 	    }
@@ -954,14 +956,14 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in
 	  }
 	if (m)
 	  *rBase = addr;
-	TRACE_ST (MY_INDEX, Source, m, S, Base, Offset);
+	TRACE_ST (MY_INDEX, Source, m, S, base, offset);
 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i
-	do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset);
+	do_st (_SD, Source, vBase, rBase, m, sz, 0, vSignedOffset);
 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r
-	do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff);
+	do_st (_SD, Source, vBase, rBase, m, sz, S, rIndOff);
 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l
 	long_immediate (LongSignedImmediateOffset);
-	do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset);
+	do_st (_SD, Source, vBase, rBase, m, sz, S, LongSignedImmediateOffset);
 
 
 // sub
@@ -971,12 +973,12 @@ void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2
 	ALU_END (*rDest);
 	TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2);
 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i
-	do_sub (_SD, rDest, vSource1, rSource2);
+	do_sub (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r
-	do_sub (_SD, rDest, rSource1, rSource2);
+	do_sub (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l
 	long_immediate (LongSignedImmediate);
-	do_sub (_SD, rDest, LongSignedImmediate, rSource2);
+	do_sub (_SD, rDest, LongSignedImmediate, vSource2);
 
 
 // subu
@@ -986,16 +988,16 @@ void::function::do_subu:unsigned32 *rDest, unsigned32 Source1, signed32 Source2
 	*rDest = result;
 // NOTE - the book has 15.1 which conflicts with subu.
 31.Dest,26.Source2,21.0b101101,15.1,14.UnsignedImmediate::::subu i
-	do_subu (_SD, rDest, vSource1, rSource2);
+	do_subu (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r
-	do_subu (_SD, rDest, rSource1, rSource2);
+	do_subu (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l
 	long_immediate (LongSignedImmediate);
-	do_subu (_SD, rDest, LongSignedImmediate, rSource2);
+	do_subu (_SD, rDest, LongSignedImmediate, vSource2);
 
 
 // swcr
-void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
+void::function::do_swcr:int Dest, signed32 source, signed32 cr
 	tic80_control_regs reg = tic80_index2cr (cr);
 	/* cache the old CR value */
 	unsigned32 old_cr = CR (cr);
@@ -1004,22 +1006,22 @@ void::function::do_swcr:int Dest, signed32 rSource, signed32 cr
 	  switch (reg)
 	    {
 	    case INTPEN_CR:
-	      CR (cr) &= ~rSource;
+	      CR (cr) &= ~source;
 	      break;
 	    default:
-	      CR (cr) = rSource;
+	      CR (cr) = source;
 	      break;
 	    }
 	/* Finish off the read */
 	GPR (Dest) = old_cr;
-	TRACE_SINK3 (MY_INDEX, rSource, cr, Dest);
+	TRACE_SINK3 (MY_INDEX, source, cr, Dest);
 31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i
-	do_swcr (_SD, Dest, rSource, UCRN);
+	do_swcr (_SD, Dest, vSource, UCRN);
 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r
-	do_swcr (_SD, Dest, rSource, UCRN);
+	do_swcr (_SD, Dest, vSource, UCRN);
 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l
 	long_immediate (LongUnsignedControlRegister);
-	do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister);
+	do_swcr (_SD, Dest, vSource, LongUnsignedControlRegister);
 
 
 // trap
@@ -1163,28 +1165,28 @@ void::function::do_trap:unsigned32 trap_number
 
 
 // xnor
-void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2
-	unsigned32 result = ~ (Source1 ^ Source2);
-	TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
+void::function::do_xnor:signed32 *rDest, signed32 source1, signed32 source2
+	unsigned32 result = ~ (source1 ^ source2);
+	TRACE_ALU3 (MY_INDEX, result, source1, source2);
 	*rDest = result;
 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i
-	do_xnor (_SD, rDest, vSource1, rSource2);
+	do_xnor (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r
-	do_xnor (_SD, rDest, rSource1, rSource2);
+	do_xnor (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l
 	long_immediate (LongUnsignedImmediate);
-	do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2);
+	do_xnor (_SD, rDest, LongUnsignedImmediate, vSource2);
 
 
 // xor
-void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2
-	unsigned32 result = Source1 ^ Source2;
-	TRACE_ALU3 (MY_INDEX, result, Source1, Source2);
+void::function::do_xor:signed32 *rDest, signed32 source1, signed32 source2
+	unsigned32 result = source1 ^ source2;
+	TRACE_ALU3 (MY_INDEX, result, source1, source2);
 	*rDest = result;
 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i
-	do_xor (_SD, rDest, vSource1, rSource2);
+	do_xor (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010110,12.0,11./,4.Source1::::xor r
-	do_xor (_SD, rDest, rSource1, rSource2);
+	do_xor (_SD, rDest, vSource1, vSource2);
 31.Dest,26.Source2,21.0b110010110,12.1,11./::::xor l
 	long_immediate (LongUnsignedImmediate);
-	do_xor (_SD, rDest, LongUnsignedImmediate, rSource2);
+	do_xor (_SD, rDest, LongUnsignedImmediate, vSource2);
diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c
index e013302..24cfad1 100644
--- a/sim/tic80/interp.c
+++ b/sim/tic80/interp.c
@@ -114,7 +114,6 @@ engine_run_until_stop (SIM_DESC sd,
       do
 	{
 	  instruction_word insn = IMEM (cia);
-	  cpu->reg[0] = 0;		/* force r0 to always contain 0 */
 	  cia = idecode_issue (sd, insn, cia);
 	}
       while (*keep_running);
@@ -136,7 +135,6 @@ engine_step (SIM_DESC sd)
       sd->restart_ok = 1;
       cia = cpu->cia;
       insn = IMEM (cia);
-      cpu->reg[0] = 0;		/* force r0 to always contain 0 */
       cia = idecode_issue (sd, insn, cia);
       engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP);
     }
diff --git a/sim/tic80/sim-calls.c b/sim/tic80/sim-calls.c
index 3677d8c..dd54184 100644
--- a/sim/tic80/sim-calls.c
+++ b/sim/tic80/sim-calls.c
@@ -177,7 +177,9 @@ sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
 void
 sim_fetch_register (SIM_DESC sd, int regnr, unsigned char *buf)
 {
-  if (regnr >= R0_REGNUM && regnr <= Rn_REGNUM)
+  if (regnr == R0_REGNUM)
+    memset (buf, 0, sizeof (unsigned32));
+  else if (regnr > R0_REGNUM && regnr <= Rn_REGNUM)
     *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->reg[regnr - R0_REGNUM]);
   else if (regnr == PC_REGNUM)
     *(unsigned32*)buf = H2T_4 (STATE_CPU (sd, 0)->cia.ip);