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authorAndrew Cagney <cagney@redhat.com>1997-05-15 16:39:38 +0000
committerAndrew Cagney <cagney@redhat.com>1997-05-15 16:39:38 +0000
commit07b4c0a66c431fdd3fae16977ce862b657569ffb (patch)
tree4be1fa948a5863ec20bfc825cc6a3ec96beb958a /sim/tic80
parent4cc56716560b564c7b7f27e5eae03f9366f7ecab (diff)
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Remove some of the flake from the c80 floating point.
Diffstat (limited to 'sim/tic80')
-rw-r--r--sim/tic80/ChangeLog8
-rw-r--r--sim/tic80/Makefile.in1
-rw-r--r--sim/tic80/insns48
3 files changed, 46 insertions, 11 deletions
diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index 89ebd48..8f9ffd0 100644
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,5 +1,13 @@
Thu May 15 11:45:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
+ * insns (do_shift): When rot==0 and zero/sign merge treat it as
+ 32.
+ (set_fp_reg): For interger conversion, use sim-fpu fpu2i
+ functions.
+ (do_fmpy): Perform iii and uuu using integer arithmetic.
+
+ * Makefile.in (ENGINE_H): Assume everything depends on the fpu.
+
* insns (get_fp_reg): Use sim_fpu_u32to to perform unsigned
conversion.
(do_fcmp): Update to use new fp compare functions. Make reg nr arg
diff --git a/sim/tic80/Makefile.in b/sim/tic80/Makefile.in
index eb3f943..0e9dc25 100644
--- a/sim/tic80/Makefile.in
+++ b/sim/tic80/Makefile.in
@@ -140,6 +140,7 @@ ENGINE_H = \
$(srcdir)/../common/sim-alu.h \
$(srcdir)/../common/sim-core.h \
$(srcdir)/../common/sim-events.h \
+ $(srcdir)/../common/sim-fpu.h \
idecode.o: $(ENGINE_H)
semantics.o: $(ENGINE_H)
diff --git a/sim/tic80/insns b/sim/tic80/insns
index ff80bff..7a15fc7 100644
--- a/sim/tic80/insns
+++ b/sim/tic80/insns
@@ -434,13 +434,15 @@ void::function::set_fp_reg:int Dest, sim_fpu val, int PD
break;
}
case 2: /* signed */
- /* FIXME - rounding */
- GPR (Dest) = sim_fpu_2d (val);
- break;
+ {
+ GPR (Dest) = sim_fpu_to32i (val);
+ break;
+ }
case 3: /* unsigned */
- /* FIXME - rounding */
- GPR (Dest) = sim_fpu_2d (val);
- break;
+ {
+ GPR (Dest) = sim_fpu_to32u (val);
+ break;
+ }
default:
engine_error (SD, CPU, cia, "Unsupported FP precision");
}
@@ -516,9 +518,27 @@ void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2
// fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u}
void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2
- sim_fpu ans = sim_fpu_mul (s1, s2);
- TRACE_FPU3 (MY_INDEX, ans, s1, s2);
- set_fp_reg (_SD, Dest, ans, PD);
+ switch (PD)
+ {
+ case 2: /* signed */
+ {
+ GPR (Dest) = sim_fpu_to64i (s1) * sim_fpu_to64i (s2);
+ TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
+ break;
+ }
+ case 3: /* unsigned */
+ {
+ GPR (Dest) = sim_fpu_to64u (s1) * sim_fpu_to64u (s2);
+ TRACE_FPU2I (MY_INDEX, GPR (Dest), s1, s2);
+ break;
+ }
+ default:
+ {
+ sim_fpu ans = sim_fpu_mul (s1, s2);
+ set_fp_reg (_SD, Dest, ans, PD);
+ TRACE_FPU3 (MY_INDEX, ans, s1, s2);
+ }
+ }
31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r
do_fmpy (_SD, Dest, PD,
get_fp_reg (_SD, Source1, rSource1, P1),
@@ -832,8 +852,14 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM
case 0: case 1: case 2:
shiftmask = ~ (unsigned32)0; /* disabled */
break;
- case 3: case 4: case 5:
- shiftmask = ((1 << nRotate) - 1); /* enabled */
+ case 3: case 5: /* enabled - 0 -> 32 */
+ if (nRotate == 0)
+ shiftmask = ~ (unsigned32)0;
+ else
+ shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
+ break;
+ case 4:
+ shiftmask = ((1 << nRotate) - 1); /* enabled - 0 -> 0 */
break;
case 6: case 7:
shiftmask = ~((1 << nRotate) - 1); /* inverted */