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| author | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-05-16 03:27:40 +0000 |
| commit | 37a684b84d5c722848ebdc7203052d65c6b35e30 (patch) | |
| tree | 3d7fa5b15efab746e9b8cc87449fa8664b6ed359 /sim/tic80/interp.c | |
| parent | 77bd8dfa1f3678ea3c3d05f40de29a36802d21f5 (diff) | |
| download | gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.zip gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.gz gdb-37a684b84d5c722848ebdc7203052d65c6b35e30.tar.bz2 | |
o Make tic80 insn file more `cache ready'
o Have igen always zero r0 instead of constantly checking if
the designated register is r0.
Diffstat (limited to 'sim/tic80/interp.c')
| -rw-r--r-- | sim/tic80/interp.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c index e013302..24cfad1 100644 --- a/sim/tic80/interp.c +++ b/sim/tic80/interp.c @@ -114,7 +114,6 @@ engine_run_until_stop (SIM_DESC sd, do { instruction_word insn = IMEM (cia); - cpu->reg[0] = 0; /* force r0 to always contain 0 */ cia = idecode_issue (sd, insn, cia); } while (*keep_running); @@ -136,7 +135,6 @@ engine_step (SIM_DESC sd) sd->restart_ok = 1; cia = cpu->cia; insn = IMEM (cia); - cpu->reg[0] = 0; /* force r0 to always contain 0 */ cia = idecode_issue (sd, insn, cia); engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP); } |