From 37a684b84d5c722848ebdc7203052d65c6b35e30 Mon Sep 17 00:00:00 2001 From: Andrew Cagney Date: Fri, 16 May 1997 03:27:40 +0000 Subject: o Make tic80 insn file more `cache ready' o Have igen always zero r0 instead of constantly checking if the designated register is r0. --- sim/tic80/interp.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'sim/tic80/interp.c') diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c index e013302..24cfad1 100644 --- a/sim/tic80/interp.c +++ b/sim/tic80/interp.c @@ -114,7 +114,6 @@ engine_run_until_stop (SIM_DESC sd, do { instruction_word insn = IMEM (cia); - cpu->reg[0] = 0; /* force r0 to always contain 0 */ cia = idecode_issue (sd, insn, cia); } while (*keep_running); @@ -136,7 +135,6 @@ engine_step (SIM_DESC sd) sd->restart_ok = 1; cia = cpu->cia; insn = IMEM (cia); - cpu->reg[0] = 0; /* force r0 to always contain 0 */ cia = idecode_issue (sd, insn, cia); engine_halt (sd, cpu, cia, sim_stopped, SIGTRAP); } -- cgit v1.1