sim: riscv: new port

This is a hand-written implementation that should have fairly complete
coverage for the base integer instruction set ("i"), and for the atomic
("a") and integer multiplication+division ("m") extensions.  It also
covers 32-bit & 64-bit targets.

The unittest coverage is a bit weak atm, but should get better.

5 files changed, 81 insertions, 0 deletions

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 4271705..3b2b8df 100644
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2021-02-04  Mike Frysinger  <vapier@gentoo.org>
+
+	* riscv/: New directory.
+
 2021-01-15  Mike Frysinger  <vapier@gentoo.org>
 
 	* Makefile.in (site.exp): Delete tool setting.
diff --git a/sim/testsuite/riscv/ChangeLog b/sim/testsuite/riscv/ChangeLog
new file mode 100644
index 0000000..c222209
--- /dev/null
+++ b/sim/testsuite/riscv/ChangeLog
@@ -0,0 +1,3 @@
+2021-02-04  Mike Frysinger  <vapier@gentoo.org>
+
+	* allinsn.exp, pass.s, testutils.inc: New files.
diff --git a/sim/testsuite/riscv/allinsn.exp b/sim/testsuite/riscv/allinsn.exp
new file mode 100644
index 0000000..03bec1b
--- /dev/null
+++ b/sim/testsuite/riscv/allinsn.exp
@@ -0,0 +1,15 @@
+# RISC-V simulator testsuite.
+
+if [istarget riscv*-*] {
+    # all machines
+    set all_machs "riscv"
+
+    foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.s]] {
+	# If we're only testing specific files and this isn't one of them,
+	# skip it.
+	if ![runtest_file_p $runtests $src] {
+	    continue
+	}
+	run_sim_test $src $all_machs
+    }
+}
diff --git a/sim/testsuite/riscv/pass.s b/sim/testsuite/riscv/pass.s
new file mode 100644
index 0000000..bd428ca
--- /dev/null
+++ b/sim/testsuite/riscv/pass.s
@@ -0,0 +1,7 @@
+# check that the sim doesn't die immediately.
+# mach: riscv
+
+.include "testutils.inc"
+
+	start
+	pass
diff --git a/sim/testsuite/riscv/testutils.inc b/sim/testsuite/riscv/testutils.inc
new file mode 100644
index 0000000..b9680b9
--- /dev/null
+++ b/sim/testsuite/riscv/testutils.inc
@@ -0,0 +1,52 @@
+# MACRO: exit
+	.macro exit nr
+	li a0, \nr
+	# The exit utility function.
+	li a7, 93;
+	# Trigger OS trap.
+	ecall;
+	.endm
+
+# MACRO: pass
+# Write 'pass' to stdout and quit.
+	.macro pass
+	# syscall write().
+	li a7, 64;
+	# Use stdout.
+	li a0, 1;
+	# Point to the string.
+	lla a1, 1f;
+	# Number of bytes to write.
+	li a2, 5;
+	# Trigger OS trap.
+	ecall;
+	exit 0;
+	.data
+	1: .asciz "pass\n"
+	.endm
+
+# MACRO: fail
+# Write 'fail' to stdout and quit.
+	.macro fail
+	# syscall write().
+	li a7, 64;
+	# Use stdout.
+	li a0, 1;
+	# Point to the string.
+	lla a1, 1f;
+	# Number of bytes to write.
+	li a2, 5;
+	# Trigger OS trap.
+	ecall;
+	exit 0;
+	.data
+	1: .asciz "fail\n"
+	.endm
+
+# MACRO: start
+# All assembler tests should start with a call to "start".
+	.macro start
+	.text
+.global _start
+_start:
+	.endm