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authorDimitar Dimitrov <dimitar@dinux.eu>2022-11-11 20:14:13 +0200
committerDimitar Dimitrov <dimitar@dinux.eu>2022-11-12 15:10:07 +0200
commit7bee555bb712b74749b749d80566f9c0d2094312 (patch)
tree3a88471f78ae789677ea9146ba39f886601d58d0 /sim/testsuite/pru
parent7149607f6ae572fa198116b0d0fb69a3e0fde458 (diff)
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sim: pru: Fix behaviour when loop count is zero
If the counter for LOOP instruction is provided by a register with value zero, then the instruction must cause a PC jump directly to the loop end. But in that particular case simulator must not initialize its internal loop variables, because loop body will not be executed. Instead, simulator must obtain the loop's end address directly from the LOOP instruction. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
Diffstat (limited to 'sim/testsuite/pru')
-rw-r--r--sim/testsuite/pru/loop-zero.s41
1 files changed, 41 insertions, 0 deletions
diff --git a/sim/testsuite/pru/loop-zero.s b/sim/testsuite/pru/loop-zero.s
new file mode 100644
index 0000000..65330f2
--- /dev/null
+++ b/sim/testsuite/pru/loop-zero.s
@@ -0,0 +1,41 @@
+# Check that loop insn works if register value is zero.
+# mach: pru
+
+# Copyright (C) 2022 Free Software Foundation, Inc.
+# Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
+#
+# This file is part of the GNU simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+.include "testutils.inc"
+
+ start
+
+ ldi r25, 0
+ ldi r27, 0
+ ldi r28, 10
+
+ loop 1f, r25
+ add r27, r27, 1
+ add r28, r28, 1
+1:
+
+ qbne F, r25, 0
+ qbne F, r27, 0
+ qbne F, r28, 10
+
+ pass
+
+F: fail