import gdb-2000-01-05 snapshot

26 files changed, 562 insertions, 5 deletions

diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index de4a22c..1d73e29 100644
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,3 +1,15 @@
+Mon Jan  3 00:17:28 2000  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* t-ae-ld-d.s, t-ae-ld-i.s, t-ae-ld-id.s, t-ae-ld-im.s ,
+ 	t-ae-ld-ip.s, t-ae-ld2w-d.s, t-ae-ld2w-i.s, t-ae-ld2w-id.s ,
+ 	t-ae-ld2w-im.s, t-ae-ld2w-ip.s, t-ae-st-d.s, t-ae-st-i.s ,
+ 	t-ae-st-id.s, t-ae-st-im.s, t-ae-st-ip.s, t-ae-st-is.s ,
+ 	t-ae-st2w-d.s, t-ae-st2w-i.s, t-ae-st2w-id.s, t-ae-st2w-im.s ,
+ 	t-ae-st2w-ip.s, t-ae-st2w-is.s: New tests.  Check that an address
+ 	exception occures when a word/two-word load/store is not word
+ 	aligned.
+	* Makefile.in (TESTS): Update.
+
 Fri Oct 29 18:36:34 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 
 	* t-mvtc.s: Check that the user can not modify the DM bit in the
diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in
index b170f37..079f95d 100644
--- a/sim/testsuite/d10v-elf/Makefile.in
+++ b/sim/testsuite/d10v-elf/Makefile.in
@@ -60,6 +60,29 @@ TESTS = \
 	t-sub2w.ok \
 	t-sub.ok \
 	t-subi.ok \
+	t-ae-ld-d.ok \
+	t-ae-ld-i.ok \
+	t-ae-ld-id.ok \
+	t-ae-ld-im.ok \
+	t-ae-ld-ip.ok \
+	t-ae-ld2w-d.ok \
+	t-ae-ld2w-i.ok \
+	t-ae-ld2w-id.ok \
+	t-ae-ld2w-im.ok \
+	t-ae-ld2w-ip.ok \
+	t-ae-st-d.ok \
+	t-ae-st-i.ok \
+	t-ae-st-id.ok \
+	t-ae-st-im.ok \
+	t-ae-st-ip.ok \
+	t-ae-st-is.ok \
+	t-ae-st2w-d.ok \
+	t-ae-st2w-i.ok \
+	t-ae-st2w-id.ok \
+	t-ae-st2w-im.ok \
+	t-ae-st2w-ip.ok \
+	t-ae-st2w-is.ok \
+	t-mod-ld-pre.ok \
 #
 
 AS_FOR_TARGET = `\
diff --git a/sim/testsuite/d10v-elf/t-ae-ld-d.s b/sim/testsuite/d10v-elf/t-ae-ld-d.s
new file mode 100644
index 0000000..1be783f
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld-d.s
@@ -0,0 +1,13 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld
+	
+	ld r8,@0x4000
+test_ld:
+	ld r8,@0x4001
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld-i.s b/sim/testsuite/d10v-elf/t-ae-ld-i.s
new file mode 100644
index 0000000..42168e1
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld-i.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld
+	
+	ldi r10, #0x4000
+	ld r8, @r10
+
+	ldi r10, #0x4001
+test_ld:
+	ld r8,@r10
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld-id.s b/sim/testsuite/d10v-elf/t-ae-ld-id.s
new file mode 100644
index 0000000..86b7382
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld-id.s
@@ -0,0 +1,15 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld
+	
+	ldi r10, #0x4001
+	ld r8, @(1,r10)
+
+test_ld:
+	ld r8,@(2,r10)
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld-im.s b/sim/testsuite/d10v-elf/t-ae-ld-im.s
new file mode 100644
index 0000000..08e2ba6
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld-im.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld
+	
+	ldi r10, #0x4000
+	ld r8, @r10-
+
+	ldi r10, #0x4001
+test_ld:
+	ld r8,@r10-
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld-ip.s b/sim/testsuite/d10v-elf/t-ae-ld-ip.s
new file mode 100644
index 0000000..cad6660
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld-ip.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld
+	
+	ldi r10, #0x4000
+	ld r8, @r10+
+
+	ldi r10, #0x4001
+test_ld:
+	ld r8,@r10+
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-d.s b/sim/testsuite/d10v-elf/t-ae-ld2w-d.s
new file mode 100644
index 0000000..c8254ab
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld2w-d.s
@@ -0,0 +1,13 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w
+	
+	ld2w r8,@0x4000
+test_ld2w:
+	ld2w r8,@0x4001
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-i.s b/sim/testsuite/d10v-elf/t-ae-ld2w-i.s
new file mode 100644
index 0000000..4b32df5
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld2w-i.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w
+	
+	ldi r10, #0x4000
+	ld2w r8, @r10
+
+	ldi r10, #0x4001
+test_ld2w:
+	ld2w r8,@r10
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-id.s b/sim/testsuite/d10v-elf/t-ae-ld2w-id.s
new file mode 100644
index 0000000..906b2a0
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld2w-id.s
@@ -0,0 +1,14 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w
+	
+	ldi r10, #0x4001
+	ld2w r8,@(1,r10)
+test_ld2w:
+	ld2w r8,@(2,r10)
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-im.s b/sim/testsuite/d10v-elf/t-ae-ld2w-im.s
new file mode 100644
index 0000000..71a7286
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld2w-im.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w
+	
+	ldi r10, #0x4000
+	ld2w r8, @r10-
+
+	ldi r10, #0x4001
+test_ld2w:
+	ld2w r8,@r10-
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s b/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s
new file mode 100644
index 0000000..38cfab6
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-ld2w-ip.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_ld2w
+	
+	ldi r10, #0x4000
+	ld2w r8, @r10+
+
+	ldi r10, #0x4001
+test_ld2w:
+	ld2w r8,@r10+
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st-d.s b/sim/testsuite/d10v-elf/t-ae-st-d.s
new file mode 100644
index 0000000..1f0edd8
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st-d.s
@@ -0,0 +1,13 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
+	
+	st r8,@0x4000
+test_st:
+	st r8,@0x4001
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st-i.s b/sim/testsuite/d10v-elf/t-ae-st-i.s
new file mode 100644
index 0000000..1524598
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st-i.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
+	
+	ldi r10,#0x4000
+	st r8, @r10
+
+	ldi r10,#0x4001
+test_st:
+	st r8,@r10
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st-id.s b/sim/testsuite/d10v-elf/t-ae-st-id.s
new file mode 100644
index 0000000..4caa1b4fa
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st-id.s
@@ -0,0 +1,14 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
+	
+	ldi r10,#0x4001
+	st r8, @(1,r10)
+test_st:
+	st r8,@(2,r10)
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st-im.s b/sim/testsuite/d10v-elf/t-ae-st-im.s
new file mode 100644
index 0000000..d4c8baf
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st-im.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
+	
+	ldi r10,#0x4000
+	st r8, @r10-
+
+	ldi r10,#0x4001
+test_st:
+	st r8,@r10-
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st-ip.s b/sim/testsuite/d10v-elf/t-ae-st-ip.s
new file mode 100644
index 0000000..e3a02ee
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st-ip.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
+	
+	ldi r10,#0x4000
+	st r8, @r10+
+
+	ldi r10,#0x4001
+test_st:
+	st r8,@r10+
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st-is.s b/sim/testsuite/d10v-elf/t-ae-st-is.s
new file mode 100644
index 0000000..4868780
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st-is.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st
+	
+	ldi sp,#0x4000
+	st r8, @-SP
+
+	ldi sp,#0x4001
+test_st:
+	st r8,@-SP
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-d.s b/sim/testsuite/d10v-elf/t-ae-st2w-d.s
new file mode 100644
index 0000000..a0d9c31
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st2w-d.s
@@ -0,0 +1,13 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
+	
+	st2w r8,@0x4000
+test_st2w:
+	st2w r8,@0x4001
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-i.s b/sim/testsuite/d10v-elf/t-ae-st2w-i.s
new file mode 100644
index 0000000..8c24bc9
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st2w-i.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
+	
+	ldi r10, #0x4000
+	st2w r8, @r10
+
+	ldi r10, #0x4001
+test_st2w:
+	st2w r8,@r10
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-id.s b/sim/testsuite/d10v-elf/t-ae-st2w-id.s
new file mode 100644
index 0000000..bfbfd4d
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st2w-id.s
@@ -0,0 +1,14 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
+	
+	ldi r10, #0x4001
+	st2w r8, @(1,r10)
+test_st2w:
+	st2w r8,@(2,r10)
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-im.s b/sim/testsuite/d10v-elf/t-ae-st2w-im.s
new file mode 100644
index 0000000..ee0a9eb
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st2w-im.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
+	
+	ldi r10, #0x4000
+	st2w r8, @r10-
+
+	ldi r10, #0x4001
+test_st2w:
+	st2w r8,@r10-
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-ip.s b/sim/testsuite/d10v-elf/t-ae-st2w-ip.s
new file mode 100644
index 0000000..dc911f7
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st2w-ip.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
+	
+	ldi r10, #0x4000
+	st2w r8, @r10+
+
+	ldi r10, #0x4001
+test_st2w:
+	st2w r8,@r10+
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-ae-st2w-is.s b/sim/testsuite/d10v-elf/t-ae-st2w-is.s
new file mode 100644
index 0000000..e39d71c
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-ae-st2w-is.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	PSW_BITS = 0
+	point_dmap_at_imem
+	check_interrupt (VEC_AE&DMAP_MASK)+DMAP_BASE PSW_BITS test_st2w
+	
+	ldi sp, #0x4004
+	st2w r8, @-SP
+
+	ldi sp, #0x4005
+test_st2w:
+	st2w r8,@-SP
+	nop
+	exit47
diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i
index 2f54d1c..f424acf 100644
--- a/sim/testsuite/d10v-elf/t-macros.i
+++ b/sim/testsuite/d10v-elf/t-macros.i
@@ -21,6 +21,20 @@ _start:
 	.endm
 
 
+	.macro exit1
+	ldi r4, 1
+	ldi r0, 1
+	trap 15
+	.endm
+
+
+	.macro exit2
+	ldi r4, 1
+	ldi r0, 2
+	trap 15
+	.endm
+
+
 	.macro load reg val
 	ldi \reg, #\val
 	.endm
@@ -128,6 +142,53 @@ _start:
 	.endm
 
 
+;;; Blat our DMAP registers so that they point at on-chip imem
+	.macro point_dmap_at_imem
+	.text
+	ldi r2, MAP_INSN | 0xf
+	st r2, @(DMAP_REG,r0)
+	ldi r2, MAP_INSN
+	st r2, @(IMAP1_REG,r0)
+	.endm
+
+;;; Patch VEC so that it jumps back to code that checks PSW
+;;; and then exits with success.
+	.macro check_interrupt vec psw src
+;;; Patch the interrupt vector's AE entry with a jmp to success
+	.text
+	ldi r4, #1f
+	ldi r5, \vec
+	;; 	
+	ld2w r2, @(0,r4)
+	st2w r2, @(0,r5)
+	ld2w r2, @(4,r4)
+	st2w r2, @(4,r5)
+	;; 	
+	bra 9f
+	nop
+;;; Code that gets patched into the interrupt vector
+	.data
+1:	ldi r1, 2f@word
+	jmp r1
+;;; Successfull trap jumps back to here
+	.text
+;;; Verify the PSW
+2:	mvfc	r2, cr0
+	cmpeqi	r2, #\psw
+	brf0t	3f
+	nop
+	exit1
+;;; Verify the original addr
+3:	mvfc	r2, bpc
+	cmpeqi	r2, #\src@word
+	brf0t	4f
+	exit2
+4:	exit0
+;;; continue as normal
+9:	
+	.endm
+
+
 	PSW_SM = 0x8000
 	PSW_01 = 0x4000
 	PSW_EA = 0x2000
@@ -159,12 +220,14 @@ _start:
 
 ;;;
 
-	VEC_RI   = 0x3fc00
-	VEC_BAE  = 0x3fc04
-	VEC_RIE  = 0x3fc08
-	VEC_AE   = 0x3fc0c
-	VEC_TRAP = 0x3fc10
+	VEC_RI   = 0x3ff00
+	VEC_BAE  = 0x3ff04
+	VEC_RIE  = 0x3ff08
+	VEC_AE   = 0x3ff0c
+	VEC_TRAP = 0x3ff10
 	VEC_DBT  = 0x3ff50
 	VEC_SDBT = 0x3fff4
 	VEC_DBI  = 0x3ff58
 	VEC_EI   = 0x3ff5c
+
+
diff --git a/sim/testsuite/d10v-elf/t-mod-ld-pre.s b/sim/testsuite/d10v-elf/t-mod-ld-pre.s
new file mode 100644
index 0000000..4536e03
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-mod-ld-pre.s
@@ -0,0 +1,126 @@
+.include "t-macros.i"
+
+.section        .rodata
+ 
+        .text
+        .globl  main
+        .type   main,@function
+main:
+    mvfc        r0, PSW             ||  ldi.s       r14, #0
+    ldi.l       r2, 0x100               ; MOD_E
+    ldi.l       r3, 0x108               ; MOD_S
+ 
+test_mod_dec_ld:
+    mvtc        r2, MOD_E           ||  bseti       r0, #7
+    mvtc        r3, MOD_S
+    mvtc        r0, PSW                 ; modulo mode enable
+    mv          r1,r3                           ; r1=0x108
+    ld          r4, @r1-        ||      nop     ; r1=0x106
+    ld          r4, @r1-        ||      nop     ; r1=0x104
+    ld          r4, @r1-        ||      nop     ; r1=0x102
+    ld          r4, @r1-        ||      nop     ; r1=0x100
+    ld          r4, @r1-        ||      nop     ; r1=0x108 
+    ld          r4, @r1-        ||      nop     ; r1=0x106 
+ 
+    cmpeqi      r1,#0x106
+    brf0f       _ERR            ;  branch to error
+ 
+test_mod_inc_ld:
+    mvtc        r2, MOD_S
+    mvtc        r3, MOD_E
+    mv          r1,r2                           ; r1=0x100
+    ld          r4, @r1+        ||      nop     ; r1=0x102
+    ld          r4, @r1+        ||      nop     ; r1=0x104
+    ld          r4, @r1+        ||      nop     ; r1=0x106
+    ld          r4, @r1+        ||      nop     ; r1=0x108
+    ld          r4, @r1+        ||      nop     ; r1=0x100
+    ld          r4, @r1+        ||      nop     ; r1=0x102
+ 
+    cmpeqi      r1,#0x102
+    brf0f       _ERR
+ 
+test_mod_dec_ld2w:
+    mvtc        r2, MOD_E
+    mvtc        r3, MOD_S
+    mv          r1,r3                           ; r1=0x108
+    ld2W        r4, @r1-        ||      nop     ; r1=0x104
+    ld2W        r4, @r1-        ||      nop     ; r1=0x100
+    ld2W        r4, @r1-        ||      nop     ; r1=0x108 
+    ld2W        r4, @r1-        ||      nop     ; r1=0x104 
+ 
+    cmpeqi      r1,#0x104
+    brf0f       _ERR            ; <= branch to error
+ 
+test_mod_inc_ld2w:
+    mvtc        r2, MOD_S
+    mvtc        r3, MOD_E           ||  BCLRI       r0, #7
+    mv          r1,r2                           ; r1=0x100
+    ld2W        r4, @r1+        ||      nop     ; r1=0x104
+    ld2W        r4, @r1+        ||      nop     ; r1=0x108
+    ld2W        r4, @r1+        ||      nop     ; r1=0x100
+    ld2W        r4, @r1+        ||      nop     ; r1=0x104
+ 
+    cmpeqi      r1,#0x104
+    brf0f       _ERR
+ 
+test_mod_dec_ld_dis:
+    mvtc        r0, PSW                 ; modulo mode disable
+    mvtc        r2, MOD_E
+    mvtc        r3, MOD_S
+    mv          r1,r3                           ; r1=0x108
+    ld          r4, @r1-        ||      nop     ; r1=0x106
+    ld          r4, @r1-        ||      nop     ; r1=0x104
+    ld          r4, @r1-        ||      nop     ; r1=0x102
+    ld          r4, @r1-        ||      nop     ; r1=0x100
+    ld          r4, @r1-        ||      nop     ; r1=0xFE
+    ld          r4, @r1-        ||      nop     ; r1=0xFC
+ 
+    cmpeqi      r1,#0xFC
+    brf0f       _ERR
+ 
+test_mod_inc_ld_dis:
+    mvtc        r2, MOD_S
+    mvtc        r3, MOD_E
+    mv          r1,r2                           ; r1=0x100
+    ld          r4, @r1+        ||      nop     ; r1=0x102
+    ld          r4, @r1+        ||      nop     ; r1=0x104
+    ld          r4, @r1+        ||      nop     ; r1=0x106
+    ld          r4, @r1+        ||      nop     ; r1=0x108
+    ld          r4, @r1+        ||      nop     ; r1=0x10A
+    ld          r4, @r1+        ||      nop     ; r1=0x10C
+ 
+    cmpeqi      r1,#0x10C
+    brf0f       _ERR
+ 
+test_mod_dec_ld2w_dis:
+    mvtc        r2, MOD_E
+    mvtc        r3, MOD_S
+    mv          r1,r3                           ; r1=0x108
+    ld2W        r4, @r1-        ||      nop     ; r1=0x104
+    ld2W        r4, @r1-        ||      nop     ; r1=0x100
+    ld2W        r4, @r1-        ||      nop     ; r1=0xFC
+    ld2W        r4, @r1-        ||      nop     ; r1=0xF8
+ 
+    cmpeqi      r1,#0xF8
+    brf0f       _ERR
+
+ test_mod_inc_ld2w_dis:
+    mvtc        r2, MOD_S
+    mvtc        r3, MOD_E
+    mv          r1,r2                           ; r1=0x100
+    ld2W        r4, @r1+        ||      nop     ; r1=0x104
+    ld2W        r4, @r1+        ||      nop     ; r1=0x108
+    ld2W        r4, @r1+        ||      nop     ; r1=0x10C
+    ld2W        r4, @r1+        ||      nop     ; r1=0x110
+ 
+    cmpeqi      r1,#0x110
+    brf0f       _ERR 
+
+_OK:
+	exit0
+ 
+_ERR:
+	exit47
+
+ 
+