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| author | Andrew Cagney <cagney@redhat.com> | 1998-02-15 23:21:19 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1998-02-15 23:21:19 +0000 |
| commit | b104806fd3d786560fcb451fb7c8a46a95f0fc79 (patch) | |
| tree | ce2759f1a2c888a604c3013a516b73955c8bec25 /sim/testsuite/d10v-elf | |
| parent | 97908603a4b9f1d8b0a58d72b881245b889fac1f (diff) | |
| download | gdb-b104806fd3d786560fcb451fb7c8a46a95f0fc79.zip gdb-b104806fd3d786560fcb451fb7c8a46a95f0fc79.tar.gz gdb-b104806fd3d786560fcb451fb7c8a46a95f0fc79.tar.bz2 | |
Test the RDT and DBT instructions.
Diffstat (limited to 'sim/testsuite/d10v-elf')
| -rw-r--r-- | sim/testsuite/d10v-elf/t-dbt.s | 33 | ||||
| -rw-r--r-- | sim/testsuite/d10v-elf/t-rdt.s | 18 |
2 files changed, 51 insertions, 0 deletions
diff --git a/sim/testsuite/d10v-elf/t-dbt.s b/sim/testsuite/d10v-elf/t-dbt.s new file mode 100644 index 0000000..8c51847 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-dbt.s @@ -0,0 +1,33 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_DM + +;;; Blat our DMAP registers so that they point at on-chip imem + + ldi r2, MAP_INSN | 0xf + st r2, @(DMAP_REG,r0) + ldi r2, MAP_INSN + st r2, @(IMAP1_REG,r0) + +;;; Patch the interrupt vector's dbt entry with a jmp to success + + ldi r4, #trap + ldi r5, (VEC_DBT & DMAP_MASK) + DMAP_BASE + ld2w r2, @(0,r4) + st2w r2, @(0,r5) + ld2w r2, @(4,r4) + st2w r2, @(4,r5) + +test_dbt: + dbt -> nop + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 + + .data +trap: ldi r1, success@word + jmp r1 diff --git a/sim/testsuite/d10v-elf/t-rdt.s b/sim/testsuite/d10v-elf/t-rdt.s new file mode 100644 index 0000000..661b583 --- /dev/null +++ b/sim/testsuite/d10v-elf/t-rdt.s @@ -0,0 +1,18 @@ +.include "t-macros.i" + + start + + PSW_BITS = PSW_C|PSW_F0|PSW_F1 + + ldi r6, #success@word + mvtc r6, dpc + ldi r6, #PSW_BITS + mvtc r6, dpsw + +test_rdt: + RTD + exit47 + +success: + checkpsw2 1 PSW_BITS + exit0 |