* d10v_sim.h (SEXT56): Define.

* simops.c (OP_4201): For "rac", sign extend 56 bit value before
it is shifted.
* d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using
SIGNED64 macro.

6 files changed, 182 insertions, 1 deletions

diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize
index 2f3a8d8..6c46ef1 100644
--- a/sim/testsuite/d10v-elf/.Sanitize
+++ b/sim/testsuite/d10v-elf/.Sanitize
@@ -12,6 +12,7 @@ loop.s
 t-macros.i
 t-mac.s
 t-msbu.s
+t-rac.s
 t-rachi.s
 t-rep.s
 t-mulxu.s
diff --git a/sim/testsuite/d10v-elf/ChangeLog b/sim/testsuite/d10v-elf/ChangeLog
index a6f0854..29be1fb 100644
--- a/sim/testsuite/d10v-elf/ChangeLog
+++ b/sim/testsuite/d10v-elf/ChangeLog
@@ -1,6 +1,15 @@
+Wed Dec  3 16:35:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* t-rac.s: New files.
+	
+	* t-macros.i: Add macros for checking psw and 2w quantities.
+
+	* Makefile.in (TESTS): Update.
+
 Tue Dec  2 11:01:36 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
-	* t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s: New files.
+	* t-sub2w.s, t-mulxu.s, t-mac.s, t-mvtac.s, t-msbu.s, t-sub.s: New
+ 	files.
   	
 	* Makefile.in: Update.
 
diff --git a/sim/testsuite/d10v-elf/Makefile.in b/sim/testsuite/d10v-elf/Makefile.in
index c89ffb2..df43e19 100644
--- a/sim/testsuite/d10v-elf/Makefile.in
+++ b/sim/testsuite/d10v-elf/Makefile.in
@@ -44,9 +44,11 @@ TESTS = \
 	t-mvtac.ok \
 	t-msbu.ok \
 	t-mulxu.ok \
+	t-rac.ok \
 	t-rachi.ok \
 	t-rep.ok \
 	t-sub2w.ok \
+	t-sub.ok \
 	t-subi.ok \
 #
 
diff --git a/sim/testsuite/d10v-elf/t-macros.i b/sim/testsuite/d10v-elf/t-macros.i
new file mode 100644
index 0000000..83029b5
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-macros.i
@@ -0,0 +1,127 @@
+	.macro start
+	.text
+	.align 2
+	.globl _start
+_start:
+	.endm
+
+
+	.macro exit47
+	ldi r6, 1
+	ldi r2, 47
+	trap 15
+	.endm
+
+
+	.macro exit0
+	ldi r6, 1
+	ldi r2, 0
+	trap 15
+	.endm
+
+
+	.macro load reg val
+	ldi \reg, #\val
+	.endm
+
+
+	.macro load2w reg hi lo
+	ld2w \reg, @(1f,r0)
+	.data
+	.align 2
+1:	.short \hi
+	.short \lo
+	.text
+	.endm
+
+
+	.macro check exit reg val
+	cmpeqi	\reg, #\val
+	brf0t 1f
+0:	ldi r6, 1
+	ldi r2, \exit
+	trap 15
+1:
+	.endm
+
+
+	.macro check2w2 exit reg hi lo
+	st2w	\reg, @(1f,r0)
+	ld	r2, @(1f, r0)
+	cmpeqi	r2, #\hi
+	brf0f	0f
+	ld	r2, @(1f + 2, r0)
+	cmpeqi	r2, #\lo
+	brf0f	0f
+	bra	2f
+0:	ldi r6, 1
+	ldi r2, \exit
+	trap 15
+	.data
+	.align 2
+1:	.long 0
+	.text
+2:
+	.endm
+
+
+	.macro loadacc2 acc guard hi lo
+	ldi	r2, #\lo
+	mvtaclo	r2, \acc
+	ldi	r2, #\hi
+	mvtachi	r2, \acc
+	ldi	r2, #\guard
+	mvtacg	r2, \acc
+	.endm
+
+
+	.macro checkacc2 exit acc guard hi lo
+	ldi	r2, #\guard
+	mvfacg	r3, \acc
+	cmpeq	r2, r3
+	brf0f	0f
+	ldi	r2, #\hi
+	mvfachi	r3, \acc
+	cmpeq	r2, r3
+	brf0f	0f
+	ldi	r2, #\lo
+	mvfaclo	r3, \acc
+	cmpeq	r2, r3
+	brf0f	0f
+	bra	4f
+0:	ldi r6, 1
+	ldi r2, \exit
+	trap 15
+4:
+	.endm
+
+
+	.macro loadpsw2 val
+	ldi r2, #\val
+	mvtc	r2, cr0
+	.endm
+
+
+	.macro checkpsw2 exit val
+	mvfc	r2, cr0
+	cmpeqi	r2, #\val
+	brf0t	1f
+	ldi r6, 1
+	ldi r2, \exit
+	trap 15
+1:
+	.endm
+
+
+	.macro hello
+	;; 4:write (1, string, strlen (string))
+	ldi r6, 4
+	ldi r2, 1
+	ldi r3, 1f
+	ldi r4, 2f-1f-1
+	trap 15
+	.section	.rodata
+1:	.string "Hello World!\n"
+2:	.align 2
+	.text
+	.endm
diff --git a/sim/testsuite/d10v-elf/t-rac.s b/sim/testsuite/d10v-elf/t-rac.s
new file mode 100644
index 0000000..f212311
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-rac.s
@@ -0,0 +1,16 @@
+.include "t-macros.i"
+
+	start
+
+	;; clear FX
+	loadpsw2 0x8004
+	loadacc2 a0 0x80 0x0000 0x0000
+	loadacc2 a1 0x00 0x0000 0x5000
+	load r10 0x0123
+	load r11 0x4567
+test_rac1:
+	RAC	r10, a0, #-2
+	checkpsw2 1 0x8008
+	check2w2 2 r10 0x8000 0x0000
+
+	exit0
diff --git a/sim/testsuite/d10v-elf/t-rep.s b/sim/testsuite/d10v-elf/t-rep.s
new file mode 100644
index 0000000..b539bd2
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-rep.s
@@ -0,0 +1,26 @@
+.include "t-macros.i"
+
+	start
+
+
+	
+	# Check that the instruction @REP_E is executed when it
+	# is reached using a branch instruction
+	
+	ldi r2, 1
+test_rep_1:
+	rep r2, end_rep_1
+	nop || nop
+	nop || nop
+	nop || nop
+	nop || nop
+	ldi r3, 46
+	bra end_rep_1
+	ldi r3, 42
+end_rep_1:
+	addi r3, 1
+
+	check 1 r3 47
+			
+
+	exit0