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authorJoern Rennecke <joern.rennecke@embecosm.com>2002-06-18 15:54:44 +0000
committerJoern Rennecke <joern.rennecke@embecosm.com>2002-06-18 15:54:44 +0000
commitdc9feb5c97ab95cb328406040f47f20f986f0e58 (patch)
tree958f0c1b482059b8253b4133e76d07a477b50b9e /sim/sh
parent7ece0d85fda7871a1fc520016c38694441f14558 (diff)
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* interp.c (sim_resume): Fix setting of bus error for
instruction fetch.
Diffstat (limited to 'sim/sh')
-rw-r--r--sim/sh/ChangeLog5
-rw-r--r--sim/sh/interp.c2
2 files changed, 6 insertions, 1 deletions
diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index a18645f..d8a8f70 100644
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -1,3 +1,8 @@
+Tue Jun 18 16:53:11 2002 J"orn Rennecke <joern.rennecke@superh.com>
+
+ * interp.c (sim_resume): Fix setting of bus error for
+ instruction fetch.
+
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
diff --git a/sim/sh/interp.c b/sim/sh/interp.c
index 286dd2d..6abff00 100644
--- a/sim/sh/interp.c
+++ b/sim/sh/interp.c
@@ -1717,7 +1717,7 @@ sim_resume (sd, step, siggnal)
}
/* Check for SIGBUS due to insn fetch. */
else if (! saved_state.asregs.exception)
- saved_state.asregs.exception == SIGBUS;
+ saved_state.asregs.exception = SIGBUS;
saved_state.asregs.ticks += get_now () - tick_start;
saved_state.asregs.cycles += cycles;