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author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:05 +0100 |
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committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:05 +0100 |
commit | 7da28504bf86cbdf93965c953979d276db3616d0 (patch) | |
tree | 0df0f0e1b4635f6a850daf451e817337e43c9576 /sim/ppc/spreg-gen.py | |
parent | 61dac77e931e254a3caeb4d924999e11875308d0 (diff) | |
download | gdb-7da28504bf86cbdf93965c953979d276db3616d0.zip gdb-7da28504bf86cbdf93965c953979d276db3616d0.tar.gz gdb-7da28504bf86cbdf93965c953979d276db3616d0.tar.bz2 |
aarch64: Move w12-w15 range check to libopcodes
In SME, the vector select register had to be in the range
w12-w15, so it made sense to enforce that during parsing.
However, SME2 adds instructions for which the range is
w8-w11 instead.
This patch therefore moves the range check from the parsing
stage to the constraint-checking stage.
Also, the previous error used a capitalised range W12-W15,
whereas other register range errors used lowercase ranges
like p0-p7. A quick internal poll showed a preference for
the lowercase form, so the patch uses that.
The patch uses "selection register" rather than "vector
select register" so that the terminology extends more
naturally to PSEL.
Diffstat (limited to 'sim/ppc/spreg-gen.py')
0 files changed, 0 insertions, 0 deletions