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| author | Joel Sherrill <joel.sherrill@oarcorp.com> | 2008-12-15 19:48:06 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@oarcorp.com> | 2008-12-15 19:48:06 +0000 |
| commit | e3b96e32ca8e5a127ee4142a36480ae60cb2693e (patch) | |
| tree | 534343ad8e680baa96a5ae1acb65cad2ad51b010 /sim/ppc/ppc-spr-table | |
| parent | 7df76b802e634c6e20446de04a60aea149fbc459 (diff) | |
| download | gdb-e3b96e32ca8e5a127ee4142a36480ae60cb2693e.zip gdb-e3b96e32ca8e5a127ee4142a36480ae60cb2693e.tar.gz gdb-e3b96e32ca8e5a127ee4142a36480ae60cb2693e.tar.bz2 | |
2008-12-15 Joel Sherrill <joel.sherrill@oarcorp.com>
* ppc-instructions, ppc-spr-table: Add ability
to read tbrl and tbru special registers.
Diffstat (limited to 'sim/ppc/ppc-spr-table')
| -rw-r--r-- | sim/ppc/ppc-spr-table | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/ppc/ppc-spr-table b/sim/ppc/ppc-spr-table index 221ccbe..e224df9 100644 --- a/sim/ppc/ppc-spr-table +++ b/sim/ppc/ppc-spr-table @@ -32,6 +32,8 @@ SDR1:25:0:0 SRR0:26:0:0 SRR1:27:0:0 VRSAVE:256:0:0 +TBRL:268:0:0 +TBRU:269:0:0 SPRG0:272:0:0 SPRG1:273:0:0 SPRG2:274:0:0 |